CN220067398U - Level shift circuit, driving chip and electronic equipment - Google Patents
Level shift circuit, driving chip and electronic equipment Download PDFInfo
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- CN220067398U CN220067398U CN202320657503.0U CN202320657503U CN220067398U CN 220067398 U CN220067398 U CN 220067398U CN 202320657503 U CN202320657503 U CN 202320657503U CN 220067398 U CN220067398 U CN 220067398U
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Abstract
The utility model provides a level shift circuit, comprising: a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a first resistor, a second resistor, and a first diode; the grid electrode of the first transistor is used for inputting a low-voltage control signal, and the first signal output end is used for outputting a high-voltage control signal; the level shift circuit is used for generating the high-voltage control signal according to the input low-voltage control signal and outputting the high-voltage control signal through a first output end. The technical scheme provided by the utility model can reduce the static current, thereby reducing the power consumption; the high-performance analog-digital hybrid chip has the advantages of high stability, high response speed, low power consumption, full play of high working frequency and low power consumption of the power device, and can be widely applied to systems such as high-performance analog-digital hybrid chips.
Description
Technical Field
The present utility model relates to integrated circuits, and particularly to a level shift circuit, a driving chip, and an electronic device.
Background
The level shift circuit converts the low-voltage control signal into a high-voltage control signal, so that the control of the low-voltage logic on the high-voltage power output stage is realized, and the level shift circuit is widely applied. The control circuit and the high-voltage output driving circuit can be integrated together, so that high voltage resistance, high current and high precision are realized. The conventional level shift circuit converts a low-voltage control signal into a high-voltage control signal for driving an output stage PMOS tube which works under high voltage. The level shift circuit is used as a key circuit for connecting the control circuit and the output driving stage, so that on one hand, the level shift circuit is required to have high driving capability and meets the driving requirement of the output stage; on the other hand, the level shift circuit is also a high-voltage operation circuit, and requires a relatively low quiescent current, thereby reducing power consumption.
Disclosure of Invention
The utility model provides a level shift circuit, a driving chip and electronic equipment, which solve the problem of reducing the quiescent current in the level shift circuit.
According to a first aspect of the present utility model, there is provided a level shift circuit comprising:
a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a first resistor, a second resistor, a first diode, a first VDD terminal, and a first GND terminal;
the grid electrode of the first transistor is used for inputting a low-voltage control signal; the source electrode of the first transistor is connected with the source electrode of the second transistor; the source electrode of the second transistor is connected with the grid electrode and the drain electrode of the second transistor; the source electrode of the third transistor is connected with the source electrode of the second transistor; the drain electrode of the third transistor is connected with the drain electrode of the fourth transistor; the drain electrode of the first transistor is connected with the grid electrode of the third transistor and the grid electrode of the fourth transistor; the drain electrode of the third transistor and the drain electrode of the fourth transistor are connected with a first signal output end; the first signal output end is used for outputting a high-voltage control signal;
the drain electrode of the first transistor is also connected with the drain electrode of the fifth transistor; the source electrode of the fifth transistor is connected with the source electrode of the fourth transistor and the source electrode of the sixth transistor; a gate of the fifth transistor is connected with a gate of the sixth transistor; the drain electrode of the sixth transistor is connected with the grid electrode of the sixth transistor; the drain electrode of the sixth transistor is connected with the drain electrode of the seventh transistor; a source of the seventh transistor is connected with a source of the first transistor and a source of the eighth transistor; a gate of the seventh transistor is connected to a gate of the eighth transistor; the drain electrode of the eighth transistor is connected with the grid electrode of the eighth transistor; the drain electrode of the eighth transistor is connected with the first end of the second resistor; the source electrode of the eighth transistor is also connected with the anode of the first diode; the second end of the second resistor is connected with the first end of the first resistor and the cathode of the first diode; the second end of the first resistor is connected with the source electrode of the sixth transistor and the first VDD end; the positive electrode of the first diode is also connected with the first GND end. The first VDD terminal is used for inputting a first input voltage;
the level shift circuit is used for generating the high-voltage control signal according to the input low-voltage control signal and outputting the high-voltage control signal through a first output end.
Optionally, the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, and/or the eighth transistor are PMOS transistors or NMOS transistors.
Optionally, the voltage value of the low-voltage control signal is: 3.3V; the voltage value of the high-voltage control signal is 12V.
Optionally, the voltage value of the low-voltage control signal is: 3.3V; the voltage value of the high-voltage control signal is 18V.
Optionally, the voltage value of the low-voltage control signal is: 3.3V; the voltage value of the high-voltage control signal is 30V.
Optionally, the voltage value of the low-voltage control signal is: 5V; the voltage value of the high-voltage control signal is 12V.
Optionally, the voltage value of the low-voltage control signal is: 5V; the voltage value of the high-voltage control signal is 18V.
Optionally, the voltage value of the low-voltage control signal is: 5V; the voltage value of the high-voltage control signal is 30V.
According to a second aspect of the present utility model, there is provided a driving chip comprising the level shift circuit of any one of the first aspects of the present utility model.
According to a third aspect of the present utility model, there is provided an electronic device comprising the driving chip according to the second aspect of the present utility model.
The utility model provides a level shift circuit, comprising: a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a first resistor, a second resistor, and a first diode; the grid electrode of the first transistor is used for inputting a low-voltage control signal, and the first signal output end is used for outputting a high-voltage control signal; the level shift circuit is used for generating the high-voltage control signal according to the input low-voltage control signal and outputting the high-voltage control signal through a first output end. The technical scheme provided by the utility model can reduce the static current, thereby reducing the power consumption.
Drawings
Fig. 1 is a block diagram of a level shift circuit according to the present utility model;
fig. 2 is a waveform diagram of an input low-voltage control signal and an output high-voltage control signal in a level shift circuit according to the present utility model;
fig. 3 is a second waveform diagram of an input low-voltage control signal and an output high-voltage control signal in the level shift circuit according to the present utility model;
fig. 4 is a waveform diagram III of an input low-voltage control signal and an output high-voltage control signal in the level shift circuit according to the present utility model;
fig. 5 is a waveform diagram of an input low-voltage control signal and an output high-voltage control signal in the level shift circuit according to the present utility model;
fig. 6 is a fifth waveform diagram of an input low-voltage control signal and an output high-voltage control signal in the level shift circuit according to the present utility model;
fig. 7 is a waveform diagram sixth of an input low-voltage control signal and an output high-voltage control signal in the level shift circuit according to the present utility model;
reference numerals illustrate:
r1-a first resistor;
r2-a second resistor;
d1-a first diode;
M1-M8-first transistor-eighth transistor.
Detailed Description
The level shift circuit of the present utility model will be described in more detail below in conjunction with the schematic drawings, in which preferred embodiments of the present utility model are shown, it being understood that one skilled in the art may modify the utility model described herein while still achieving the advantageous effects of the utility model. Accordingly, the following description is to be construed as broadly known to those skilled in the art and not as limiting the utility model.
The utility model is more particularly described by way of example in the following paragraphs with reference to the drawings. Advantages and features of the utility model will become more apparent from the following description and from the claims. It should be noted that the drawings are in a very simplified form and are all to a non-precise scale, merely for convenience and clarity in aiding in the description of embodiments of the utility model.
Referring to fig. 1-7, according to an embodiment of the present utility model, a level shift circuit is provided, as shown in fig. 1, wherein M1-M8 represent first transistors-eighth transistors; specifically, the circuit includes:
a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a first resistor (shown as R1 in fig. 1), a second resistor (shown as R2 in fig. 1), a first diode (shown as D1 in fig. 1), a first VDD terminal, and a first GND terminal;
the grid electrode of the first transistor is used for inputting a low-voltage control signal; the source electrode of the first transistor is connected with the source electrode of the second transistor; the source electrode of the second transistor is connected with the grid electrode and the drain electrode of the second transistor; the source electrode of the third transistor is connected with the source electrode of the second transistor; the drain electrode of the third transistor is connected with the drain electrode of the fourth transistor; the drain electrode of the first transistor is connected with the grid electrode of the third transistor and the grid electrode of the fourth transistor; the drain electrode of the third transistor and the drain electrode of the fourth transistor are connected with a first signal output end; the first signal output end is used for outputting a high-voltage control signal;
the drain electrode of the first transistor is also connected with the drain electrode of the fifth transistor; the source electrode of the fifth transistor is connected with the source electrode of the fourth transistor and the source electrode of the sixth transistor; a gate of the fifth transistor is connected with a gate of the sixth transistor; the drain electrode of the sixth transistor is connected with the grid electrode of the sixth transistor; the drain electrode of the sixth transistor is connected with the drain electrode of the seventh transistor; a source of the seventh transistor is connected with a source of the first transistor and a source of the eighth transistor; a gate of the seventh transistor is connected to a gate of the eighth transistor; the drain electrode of the eighth transistor is connected with the grid electrode of the eighth transistor; the drain electrode of the eighth transistor is connected with the first end of the second resistor; the source electrode of the eighth transistor is also connected with the anode of the first diode; the second end of the second resistor is connected with the first end of the first resistor and the cathode of the first diode; the second end of the first resistor is connected with the source electrode of the sixth transistor and the first VDD end; the positive electrode of the first diode is also connected with the first GND end. The first VDD terminal is used for inputting a first input voltage;
the level shift circuit is used for generating the high-voltage control signal according to the input low-voltage control signal and outputting the high-voltage control signal through a first output end.
The technical scheme provided by the utility model skillfully designs a level shift circuit consisting of a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a first resistor, a second resistor and a first diode; the grid electrode of the first transistor is used for inputting a low-voltage control signal, and the first signal output end is used for outputting a high-voltage control signal; the level shift circuit is used for generating the high-voltage control signal according to the input low-voltage control signal and outputting the high-voltage control signal through a first output end. Therefore, the technical scheme provided by the utility model has the advantages of high stability, high response speed, low power consumption, full play of high working frequency and low power consumption of the power device, and can be widely applied to systems such as high-performance analog-digital hybrid chips.
In one embodiment, the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, or/and the eighth transistor are PMOS transistors or NMOS transistors.
In one embodiment, the voltage value of the low voltage control signal is: 3.3V; the voltage value of the high voltage control signal is 12V, as shown in fig. 2.
In one embodiment, the voltage value of the low voltage control signal is: 3.3V; the voltage value of the high voltage control signal is 18V, as shown in fig. 3.
In one embodiment, the voltage value of the low voltage control signal is: 3.3V; the voltage value of the high voltage control signal is 30V as shown in fig. 4.
In one embodiment, the voltage value of the low voltage control signal is: 5V; the voltage value of the high voltage control signal is 12V, as shown in fig. 5.
In one embodiment, the voltage value of the low voltage control signal is: 5V; the voltage value of the high voltage control signal is 18V as shown in fig. 6.
In one embodiment, the voltage value of the low voltage control signal is: 5V; the voltage value of the high voltage control signal is 30V as shown in fig. 7.
According to another embodiment of the present utility model, there is also provided a driving chip including the current amplifying circuit of any one of the foregoing embodiments of the present utility model.
According to an embodiment of the present utility model, there is further provided an electronic device including the driving chip according to the foregoing embodiment of the present utility model.
It will be apparent to those skilled in the art that various modifications and variations can be made to the present utility model without departing from the spirit or scope of the utility model. Thus, it is intended that the present utility model also include such modifications and alterations insofar as they come within the scope of the appended claims or the equivalents thereof.
Claims (10)
1. A level shift circuit, comprising:
a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a first resistor, a second resistor, a first diode, a first VDD terminal, and a first GND terminal;
the grid electrode of the first transistor is used for inputting a low-voltage control signal; the source electrode of the first transistor is connected with the source electrode of the second transistor; the source electrode of the second transistor is connected with the grid electrode and the drain electrode of the second transistor; the source electrode of the third transistor is connected with the source electrode of the second transistor; the drain electrode of the third transistor is connected with the drain electrode of the fourth transistor; the drain electrode of the first transistor is connected with the grid electrode of the third transistor and the grid electrode of the fourth transistor; the drain electrode of the third transistor and the drain electrode of the fourth transistor are connected with a first signal output end; the first signal output end is used for outputting a high-voltage control signal;
the drain electrode of the first transistor is also connected with the drain electrode of the fifth transistor; the source electrode of the fifth transistor is connected with the source electrode of the fourth transistor and the source electrode of the sixth transistor; a gate of the fifth transistor is connected with a gate of the sixth transistor; the drain electrode of the sixth transistor is connected with the grid electrode of the sixth transistor; the drain electrode of the sixth transistor is connected with the drain electrode of the seventh transistor; a source of the seventh transistor is connected with a source of the first transistor and a source of the eighth transistor; a gate of the seventh transistor is connected to a gate of the eighth transistor; the drain electrode of the eighth transistor is connected with the grid electrode of the eighth transistor; the drain electrode of the eighth transistor is connected with the first end of the second resistor; the source electrode of the eighth transistor is also connected with the anode of the first diode; the second end of the second resistor is connected with the first end of the first resistor and the cathode of the first diode; the second end of the first resistor is connected with the source electrode of the sixth transistor and the first VDD end; the positive electrode of the first diode is also connected with the first GND end; the first VDD terminal is used for inputting a first input voltage;
the level shift circuit is used for generating the high-voltage control signal according to the input low-voltage control signal and outputting the high-voltage control signal through a first output end.
2. The level shift circuit of claim 1, wherein the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, or/and the eighth transistor are PMOS transistors or NMOS transistors.
3. The level shift circuit of claim 2, wherein the voltage value of the low voltage control signal is: 3.3V; the voltage value of the high-voltage control signal is 12V.
4. The level shift circuit of claim 2, wherein the voltage value of the low voltage control signal is: 3.3V; the voltage value of the high-voltage control signal is 18V.
5. The level shift circuit of claim 2, wherein the voltage value of the low voltage control signal is: 3.3V; the voltage value of the high-voltage control signal is 30V.
6. The level shift circuit of claim 2, wherein the voltage value of the low voltage control signal is: 5V; the voltage value of the high-voltage control signal is 12V.
7. The level shift circuit of claim 2, wherein the voltage value of the low voltage control signal is: 5V; the voltage value of the high-voltage control signal is 18V.
8. The level shift circuit of claim 2, wherein the voltage value of the low voltage control signal is: 5V; the voltage value of the high-voltage control signal is 30V.
9. A driver chip comprising the level shift circuit of any one of claims 1-8.
10. An electronic device comprising the driver chip of claim 9.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202320657503.0U CN220067398U (en) | 2023-03-29 | 2023-03-29 | Level shift circuit, driving chip and electronic equipment |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202320657503.0U CN220067398U (en) | 2023-03-29 | 2023-03-29 | Level shift circuit, driving chip and electronic equipment |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN220067398U true CN220067398U (en) | 2023-11-21 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202320657503.0U Active CN220067398U (en) | 2023-03-29 | 2023-03-29 | Level shift circuit, driving chip and electronic equipment |
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| Country | Link |
|---|---|
| CN (1) | CN220067398U (en) |
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- 2023-03-29 CN CN202320657503.0U patent/CN220067398U/en active Active
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