CN109861684B - Cross-potential level shift circuit - Google Patents
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- CN109861684B CN109861684B CN201910075868.0A CN201910075868A CN109861684B CN 109861684 B CN109861684 B CN 109861684B CN 201910075868 A CN201910075868 A CN 201910075868A CN 109861684 B CN109861684 B CN 109861684B
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Abstract
The invention provides a level shift circuit of a cross potential, which comprises a voltage source, a voltage division module, an input signal processing module and an output signal processing module; the voltage source is used for providing a first conversion voltage and a grounding voltage; the voltage division module is used for carrying out voltage division operation on the first conversion voltage so as to provide a second conversion voltage; the input signal processing module is used for generating a corresponding intermediate signal according to the second conversion voltage, the grounding voltage and the input signal; the output signal processing module is used for generating an output signal according to the first conversion voltage, the grounding voltage and the intermediate signal, wherein the voltage of the output signal is higher than that of the input signal. The level shift circuit of the cross potential can realize the level shift circuit of the cross potential for converting the input signal with certain fluctuation of high potential and low potential into the output signal with stable high potential and low potential through the arrangement of the voltage division module, the input signal processing module and the output signal processing module.
Description
Technical Field
The present invention relates to the field of circuit design, and in particular, to a level shift circuit with a cross-potential.
Background
In recent years, with the development of integrated circuits and Systems On Chip (SOC), there are more and more voltage domains on one integrated circuit chip, and communication between these different voltage domains is required, so that level shift circuits are inevitably required. The level shift circuit functions to convert one level signal into another level signal, and thus the level shift circuit can be divided into a low-to-high level shift circuit and a high-to-low level shift circuit.
The existing level shift circuit generally has the following characteristics: the low potential of the output signal and the high potential of the input signal are the same, and the potential difference of the high potential of the output signal and the input signal is different, i.e., the shift high level or the shift low level is generated by the potential difference of the high potential of the output signal and the input signal.
However, in some circuit applications, it is desirable to use a level shifting circuit in which the potential difference between the high and low potentials of the input signal and the output signal is equal, and the low potential of the input signal and the output signal is different, and the high potential is different. If the output signal has stable high potential and low potential, but the high potential and low potential of the input signal have certain up-and-down fluctuation, the existing level shift circuit cannot meet the requirement of level shift.
Therefore, it is necessary to provide a level shift circuit with a cross-potential to solve the problems of the prior art.
Disclosure of Invention
The embodiment of the invention provides a level shift circuit capable of converting an input signal with certain fluctuation of high potential and low potential into a cross-potential output signal with stable high potential and low potential; the level shifting circuit solves the technical problem that the existing level shifting circuit can not convert an input signal with certain fluctuation of high potential and low potential into an output signal with stable high potential and low potential.
The embodiment of the invention provides a level shift circuit crossing potential, which comprises:
a voltage source for providing a first conversion voltage and a ground voltage
The voltage division module is used for carrying out voltage division operation on the first conversion voltage so as to provide a second conversion voltage;
the input signal processing module is used for generating a corresponding intermediate signal according to the second conversion voltage, the grounding voltage and the input signal; and
and the output signal processing module is used for generating the output signal according to the first conversion voltage, the grounding voltage and the intermediate signal, wherein the voltage of the output signal is higher than that of the input signal.
In the level shift circuit of the cross potential of the present invention, the voltage dividing module includes a first resistor and a second resistor, one end of the first resistor is connected to the conversion voltage end of the voltage source, the other end of the first resistor is connected to one end of the second resistor and the input signal processing module, and the other end of the second resistor is connected to the ground end of the voltage source.
In the level shift circuit of the present invention, the ratio of the first resistor to the sum of the resistances of the first resistor and the second resistor is greater than the ratio of the signal voltage shift amount of the input signal and the output signal to the voltage difference of the high level and the low level of the input signal.
In the level shift circuit of the cross potential, the input signal processing module comprises a first PMOS tube and a first NMOS tube, wherein the input end of the first PMOS tube is connected with the voltage dividing module, the control end of the first PMOS tube is connected with an input signal, and the output end of the first PMOS tube outputs the intermediate signal; the input end of the first NMOS tube is connected with the grounding end of the voltage source, the control end of the first NMOS tube is connected with an input signal, and the output end of the first NMOS tube outputs the intermediate signal.
In the level shift circuit of the cross potential of the invention, the output signal processing module comprises a second PMOS tube and a second NMOS tube, wherein the input end of the second PMOS tube is connected with the conversion voltage end of the voltage source, the control end of the second PMOS tube is connected with the intermediate signal, and the output end of the second PMOS tube outputs the output signal; the input end of the second NMOS tube is connected with the grounding end of the voltage source, the control end of the second NMOS tube is connected with the intermediate signal, and the output end of the second NMOS tube outputs the output signal.
The embodiment of the invention also provides a level shift circuit crossing potential, which comprises:
a voltage source for providing a conversion voltage and a first ground voltage
The voltage dividing module is used for dividing the first grounding voltage so as to provide a second grounding voltage;
the input signal processing module is used for generating a corresponding intermediate signal according to the conversion voltage, the second grounding voltage and the input signal; and
and the output signal processing module is used for generating the output signal according to the conversion voltage, the first grounding voltage and the intermediate signal, wherein the voltage of the output signal is lower than that of the input signal.
In the level shift circuit of the cross potential of the present invention, the voltage dividing module includes a first resistor and a second resistor, one end of the first resistor is connected to the conversion voltage end of the voltage source, the other end of the first resistor is connected to one end of the second resistor and the input signal processing module, and the other end of the second resistor is connected to the ground end of the voltage source.
In the level shift circuit of the present invention, the ratio of the second resistor to the sum of the resistances of the first resistor and the second resistor is greater than the ratio of the signal voltage shift amount of the input signal and the output signal to the voltage difference of the high level and the low level of the input signal.
In the level shift circuit of the cross potential of the invention, the input signal processing module comprises a first PMOS tube and a first NMOS tube, wherein the input end of the first PMOS tube is connected with the conversion voltage end of the voltage source, the control end of the first PMOS tube is connected with an input signal, and the output end of the first PMOS tube outputs the intermediate signal; the input end of the first NMOS tube is connected with the voltage dividing module, the control end of the first NMOS tube is connected with an input signal, and the output end of the first NMOS tube outputs the intermediate signal.
In the level shift circuit of the cross potential of the invention, the output signal processing module comprises a second PMOS tube and a second NMOS tube, wherein the input end of the second PMOS tube is connected with the conversion voltage end of the voltage source, the control end of the second PMOS tube is connected with the intermediate signal, and the output end of the second PMOS tube outputs the output signal; the input end of the second NMOS tube is connected with the grounding end of the voltage source, the control end of the second NMOS tube is connected with the intermediate signal, and the output end of the second NMOS tube outputs the output signal.
Compared with the prior art, the cross-potential level shift circuit can convert an input signal with certain fluctuation of high potential and low potential into a cross-potential level shift circuit with stable high potential and low potential output signal through the arrangement of the voltage division module, the input signal processing module and the output signal processing module; the technical problem that an existing level shift circuit cannot convert an input signal with certain fluctuation of high potential and low potential into an output signal with stable high potential and low potential is effectively solved.
Drawings
FIG. 1 is a schematic diagram of a first embodiment of a cross-potential level shift circuit according to the present invention;
FIG. 2 is a circuit diagram of a first embodiment of a cross-potential level shift circuit according to the present invention;
FIG. 3 is a circuit diagram of a level shift circuit of a second embodiment of the present invention;
FIG. 4 is a schematic diagram of a third embodiment of a cross-potential level shift circuit according to the present invention;
FIG. 5 is a circuit diagram of a third embodiment of a cross-potential level shift circuit according to the present invention;
fig. 6 is a specific circuit diagram of a fourth embodiment of the cross-potential level shift circuit of the present invention.
Detailed Description
The following description of the embodiments refers to the accompanying drawings, which illustrate specific embodiments in which the invention may be practiced.
Referring to fig. 1, fig. 1 is a schematic diagram of a first embodiment of a cross-potential level shift circuit according to the present invention. The level shift circuit of the present embodiment can realize a voltage stabilizing operation of a high level and a low level across a potential, that is, the high level and the low level of an input signal may have a certain voltage fluctuation, but the high level and the low level of an output signal are fixed, so that a voltage difference between the high level and the low level is also stable.
The level shift circuit of the present embodiment is a low-to-high level shift circuit. The cross-potential level shift circuit 10 includes a voltage source 11, a voltage dividing module 12, an input signal processing module 13, and an output signal processing module 14.
The voltage source 11 is used for providing a first conversion voltage VDD1 and a ground voltage GND1; the voltage dividing module 12 is used for performing voltage dividing operation on the first conversion voltage VDD1 to provide a second conversion voltage VBP; the input signal processing module 13 is configured to generate a corresponding intermediate signal INLB according to the second conversion voltage VBP, the ground voltage GND1, and the input signal INL; the output signal processing module 14 is configured to generate an output signal OUTH according to the first switching voltage VDD1, the ground voltage GND1, and the intermediate signal INLB, wherein the voltage of the output signal OUTH is higher than the voltage of the input signal INL.
Specifically, referring to fig. 2, fig. 2 is a specific circuit diagram of a first embodiment of a cross-potential level shift circuit according to the present invention. Wherein the voltage source 11 provides a first switching voltage VDD1 and a ground voltage GND1. The voltage dividing module 12 comprises a first resistor R11 and a second resistor R12, wherein one end of the first resistor R11 is connected with a conversion voltage end of the voltage source, namely, a first conversion voltage VDD1 is input; the other end of the first resistor R11 is respectively connected with one end of the second resistor R12 and the input signal processing module 13; the other end of the second resistor R12 is connected to the ground terminal of the voltage source, i.e. the input ground voltage GND1.
The input signal processing module 13 comprises a first PMOS tube M11 and a first NMOS tube M12, wherein the input end of the first PMOS tube M11 is connected with the voltage dividing module 12, namely the other end of the first resistor R11; the control end of the first PMOS tube M11 is connected with an input signal INL, the output end of the first PMOS tube M11 outputs an intermediate signal INLB, and the input end of the first NMOS tube M12 is connected with the grounding end of the voltage source 11, namely, the input grounding voltage GND1; the control end of the first NMOS tube M12 is connected to the input signal INL, and the output end of the first NMOS tube M12 outputs the intermediate signal INLB.
The output signal processing module 14 comprises a second PMOS tube M13 and a second NMOS tube M14, wherein the input end of the second PMOS tube M13 is connected with the conversion voltage end of the voltage source 11, namely, the first conversion voltage VDD is input; the control end of the second PMOS tube M13 is connected with the intermediate signal INLB; the output end of the second PMOS tube M13 outputs an output signal OUTH; the input end of the second NMOS tube M14 is connected with the grounding end of the voltage source 11, namely, the input grounding voltage GND1; the control end of the second NMOS transistor M14 is connected to the intermediate signal INLB, and the output end of the second NMOS transistor M14 outputs the output signal OUTH.
When the level shift circuit 10 of the present embodiment is used, the first resistor R11 and the second resistor R12 of the voltage division module divide the first switching voltage VDD1 to generate the second switching voltage VBP, wherein VBP is [ R12/(r11+r12) ] VDD1, when the input signal INL is between [ -R11/(r11+r12) ] VDD1 and the ground voltage GND1, the first PMOS transistor M11 is turned on, the first NMOS transistor M12 is turned off, and the intermediate signal INLB is [ R12/(r11+r12) ] VDD1; the second PMOS transistor M13 is turned off, and the second NMOS transistor M14 is turned on, and the output signal OUTH is the ground voltage GND1.
When the input signal INL is between [ R12/(r11+r12) ] VDD1 and the first switching voltage VDD1, the first PMOS transistor M11 is turned off and the first NMOS transistor M12 is turned on, and the intermediate signal INLB is the ground voltage GND1; the second PMOS transistor M13 is turned on, and the second NMOS transistor M14 is turned off, and the output signal OUTH is the first switching voltage VDD1.
Therefore, the low level signal of the input signal INL can fluctuate between [ -R11/(R11+R12) ] VDD1 to GND1, the high level signal of the input signal INL can fluctuate between [ R12/(R11+R12) ] VDD1 to VDD1, and the output signal can output a stable low level signal GND1 and a stable high level signal VDD1.
Of course, the ratio of the resistance sum of the first resistor R11 and the first resistor R11 to the second resistor R12 is larger than the ratio of the signal voltage shift amount of the input signal INL to the output signal OUTH to the voltage difference of the high level and the low level of the input signal INL. That is, the maximum shift of the signal voltages of the input signal INL and the output signal OUTH is [ R11/(r11+r12) ] VDD1, if the maximum shift of the signal voltages of the input signal INL and the output signal OUTH is greater than [ R11/(r11+r12) ] VDD1, that is, the low-potential signal of the input signal INL is less than [ -R11/(r11+r12) ] VDD1, since VBP is [ R12/(r11+r12) ] VDD1, the voltage between the source and the gate of the first PMOS transistor M11 may exceed VDD1, and an overvoltage risk may occur.
In the level shift circuit for converting low level into high level of the embodiment, the first PMOS transistor M11, the first NMOS transistor M12 and the second NMOS transistor M14 are all normal threshold voltage MOS transistors, and the second PMOS transistor M13 is a high threshold voltage MOS transistor, so as to reduce the leakage of the second PMOS transistor as much as possible. The voltage difference between any two ports of all MOS tubes in the level shift circuit does not exceed VDD, so that the overvoltage risk does not exist, and the operation stability of the level shift circuit is ensured.
The level shift circuit of the cross potential of the embodiment can realize the level shift circuit of the cross potential for converting the input signal with certain fluctuation of high potential and low potential into the output signal with stable high potential and low potential through the arrangement of the voltage division module, the input signal processing module and the output signal processing module.
Referring to fig. 3, fig. 3 is a specific circuit diagram of a second embodiment of a cross-potential level shift circuit according to the present invention. The schematic configuration of the level shift circuit of this embodiment is the same as that of the first embodiment described above. Based on the first embodiment, the level shift circuit of the present embodiment changes the first resistor and the second resistor of the voltage division module into the PMOS transistor MP11 and the PMOS transistor MP12, where the PMOS transistor MP11 and the PMOS transistor MP12 can also perform the voltage division operation on the first conversion voltage VDD.
The specific operation principle of the level shift circuit of this embodiment is the same as or similar to that described in the first embodiment of the level shift circuit, and specific reference is made to the description related to the first embodiment of the level shift circuit.
Referring to fig. 4, fig. 4 is a schematic structural diagram of a third embodiment of a cross-potential level shift circuit according to the present invention. The level shift circuit of the present embodiment is a high-to-low level shift circuit. The cross-potential level shift circuit 20 includes a voltage source 21, a voltage division module 22, an input signal processing module 23, and an output signal processing module 24.
The voltage source 21 is used for providing a switching voltage VDD2 and a first ground voltage GND2; the voltage dividing module 22 is used for performing voltage dividing operation on the first ground voltage GND2 to provide a second ground voltage VBN; the input signal processing module 23 is configured to generate a corresponding intermediate signal INHB according to the switching voltage VDD2, the second ground voltage VBN, and the input signal INH; the output signal processing module 24 is configured to generate an output signal OUTL according to the switching voltage VDD2, the first ground voltage GND2, and the intermediate signal INHB, wherein the voltage of the output signal OUTL is lower than the voltage of the input signal INH.
Specifically, referring to fig. 5, fig. 5 is a specific circuit diagram of a third embodiment of a cross-potential level shift circuit according to the present invention. Wherein the voltage source 21 provides a switching voltage VDD2 and a first ground voltage GND2. The voltage dividing module 22 comprises a first resistor R21 and a second resistor R22, wherein one end of the first resistor R21 is connected with a conversion voltage end of the voltage source 21, namely, the input conversion voltage VDD2; the other end of the first resistor R21 is respectively connected with one end of the second resistor R22 and the input signal processing module 23; the other end of the second resistor R22 is connected to the ground terminal of the voltage source 21, i.e., the first ground voltage GND2 is input.
The input signal processing module 23 includes a first PMOS transistor M21 and a first NMOS transistor M22, where an input end of the first PMOS transistor M21 is connected to a conversion voltage end of the voltage source 21, that is, an input conversion voltage VDD2; the control end of the first PMOS tube M21 is connected with an input signal INH, the output end of the first PMOS tube M21 outputs an intermediate signal INHB, and the input end of the first NMOS tube M22 is connected with the voltage dividing module 22; the control end of the first NMOS tube M22 is connected to the input signal INH, and the output end of the first NMOS tube M22 outputs the intermediate signal INHB.
The output signal processing module 24 includes a second PMOS transistor M23 and a second NMOS transistor M24, where an input end of the second PMOS transistor M23 is connected to a conversion voltage end of the voltage source 21, that is, an input conversion voltage VDD2; the control end of the second PMOS tube M23 is connected with the intermediate signal INHB; the output end of the second PMOS tube M23 outputs an output signal OUTL; the input end of the second NMOS tube M24 is connected with the grounding end of the voltage source 21, namely, the input grounding voltage GND2; the control end of the second NMOS transistor M24 is connected to the intermediate signal INHB, and the output end of the second NMOS transistor M24 outputs the output signal OUTL.
When the level shift circuit 20 of the present embodiment is used, the first resistor R21 and the second resistor R22 of the voltage division module 22 divide the first ground voltage GND2 to generate the second ground voltage VBN, where VBN is [ R22/(r21+r22) ] VDD2, and when the input signal INH is between the first ground voltage GND2 and [ R22/(r21+r22) ] VDD2, the first PMOS tube M21 is turned on, the first NMOS tube M22 is turned off, and the intermediate signal INHB is VDD2; the second PMOS transistor M23 is turned off, and the second NMOS transistor M24 is turned on, so that the output signal OUTL is the ground voltage GND2.
When the input signal INH is between VDD2 and [ (R21+2R22)/(R21+R22) ] VDD2, the first PMOS tube M21 is disconnected, the first NMOS tube M22 is connected, and the intermediate signal INHB is the second grounding voltage [ R22/(R21+R22) ] VDD2; the second PMOS transistor M23 is turned on, and the second NMOS transistor M24 is turned off, so that the output signal OUTL is the switching voltage VDD2.
Therefore, the low level signal of the input signal INH can fluctuate between GND2 and [ R22/(R21+R22) ] VDD2, the high level signal of the input signal INH can fluctuate between VDD2 and [ (R21+2R22)/(R21+R22) ] VDD2, and the output signal can output stable low level signal GND2 and high level signal VDD2.
Of course, the ratio of the second resistor R22 to the sum of the resistances of the first resistor R21 and the second resistor R22 is larger than the ratio of the signal voltage shift amount of the input signal INH and the output signal OUTL to the voltage difference of the high and low levels of the input signal INH. That is, the maximum shift of the signal voltages of the input signal INH and the output signal OUTL is [ r22/(r21+r22) ] VDD2, if the maximum shift of the signal voltages of the input signal INH and the output signal OUTL is greater than [ r22/(r21+r22) ] VDD2, that is, the high-potential signal of the input signal INH is greater than [ (r21+2r22)/(r21+r22) ] VDD, the voltage between the source and the gate of the first NMOS transistor M22 may exceed VDD2 due to VBN being [ r22/(r21+r22) ] VDD, and an overvoltage risk may occur.
In the level shift circuit for converting low level into high level of the embodiment, the first PMOS transistor M21, the first NMOS transistor M22 and the second NMOS transistor M24 are all normal threshold voltage MOS transistors, and the second PMOS transistor M23 is a high threshold voltage MOS transistor, so as to reduce the leakage of the second PMOS transistor M23 as much as possible. The voltage difference between any two ports of all MOS tubes in the level shift circuit does not exceed VDD, so that the overvoltage risk does not exist, and the operation stability of the level shift circuit is ensured.
The level shift circuit of the cross potential of the embodiment can realize the level shift circuit of the cross potential for converting the input signal with certain fluctuation of high potential and low potential into the output signal with stable high potential and low potential through the arrangement of the voltage division module, the input signal processing module and the output signal processing module.
Referring to fig. 6, fig. 6 is a specific circuit diagram of a fourth embodiment of a cross-potential level shift circuit according to the present invention. The schematic configuration of the level shift circuit of this embodiment is the same as that of the third embodiment of the level shift circuit described above. Based on the third embodiment, the level shift circuit of the present embodiment changes the first resistor and the second resistor of the voltage dividing module into the PMOS transistor MP21 and the PMOS transistor MP22, where the PMOS transistor MP21 and the PMOS transistor MP22 can also perform the voltage dividing operation on the first converted voltage VDD.
The specific operation principle of the level shift circuit of this embodiment is the same as or similar to that described in the first embodiment of the level shift circuit, and specific reference is made to the description related to the first embodiment of the level shift circuit.
The level shift circuit of the cross potential can realize the level shift circuit of the cross potential for converting an input signal with certain fluctuation of high potential and low potential into an output signal with stable high potential and low potential through the arrangement of the voltage division module, the input signal processing module and the output signal processing module; the technical problem that an existing level shift circuit cannot convert an input signal with certain fluctuation of high potential and low potential into an output signal with stable high potential and low potential is effectively solved.
In summary, although the embodiments of the present invention have been described above, the numbers before the embodiments are used for convenience of description, and the order of the embodiments of the present invention is not limited. Moreover, the above-mentioned embodiments are not intended to limit the present invention, and those skilled in the art can make various modifications and variations without departing from the spirit and scope of the present invention, so the scope of the present invention is defined by the claims.
Claims (6)
1. A level shift circuit across a potential, comprising:
a voltage source for providing a first conversion voltage and a ground voltage
The voltage division module is used for carrying out voltage division operation on the first conversion voltage so as to provide a second conversion voltage;
the input signal processing module is used for generating a corresponding intermediate signal according to the second conversion voltage, the grounding voltage and the input signal; and
the output signal processing module is used for generating the output signal according to the first conversion voltage, the grounding voltage and the intermediate signal, wherein the voltage of the output signal is higher than that of the input signal;
the input signal processing module comprises a first PMOS tube and a first NMOS tube, wherein the input end of the first PMOS tube is connected with the voltage dividing module, the control end of the first PMOS tube is connected with an input signal, and the output end of the first PMOS tube outputs the intermediate signal; the input end of the first NMOS tube is connected with the grounding end of the voltage source, the control end of the first NMOS tube is connected with an input signal, and the output end of the first NMOS tube outputs the intermediate signal;
the output signal processing module comprises a second PMOS tube and a second NMOS tube, wherein the input end of the second PMOS tube is connected with the conversion voltage end of the voltage source, the control end of the second PMOS tube is connected with the intermediate signal, and the output end of the second PMOS tube outputs the output signal; the input end of the second NMOS tube is connected with the grounding end of the voltage source, the control end of the second NMOS tube is connected with the intermediate signal, and the output end of the second NMOS tube outputs the output signal.
2. The cross-potential level shift circuit according to claim 1, wherein the voltage dividing module comprises a first resistor and a second resistor, one end of the first resistor is connected to the switching voltage end of the voltage source, the other end of the first resistor is connected to one end of the second resistor and the input signal processing module, respectively, and the other end of the second resistor is connected to the ground end of the voltage source.
3. The cross-potential level shift circuit according to claim 2, wherein a ratio of the first resistor to a sum of the first resistor and the second resistor is larger than a ratio of a signal voltage shift amount of the input signal to the output signal to a voltage difference of a high level and a low level of the input signal.
4. A level shift circuit across a potential, comprising:
a voltage source for providing a conversion voltage and a first ground voltage
The voltage dividing module is used for dividing the first grounding voltage so as to provide a second grounding voltage;
the input signal processing module is used for generating a corresponding intermediate signal according to the conversion voltage, the second grounding voltage and the input signal; and
the output signal processing module is used for generating the output signal according to the conversion voltage, the first grounding voltage and the intermediate signal, wherein the voltage of the output signal is lower than that of the input signal;
the input signal processing module comprises a first PMOS tube and a first NMOS tube, wherein the input end of the first PMOS tube is connected with the conversion voltage end of the voltage source, the control end of the first PMOS tube is connected with an input signal, and the output end of the first PMOS tube outputs the intermediate signal; the input end of the first NMOS tube is connected with the voltage dividing module, the control end of the first NMOS tube is connected with an input signal, and the output end of the first NMOS tube outputs the intermediate signal;
the output signal processing module comprises a second PMOS tube and a second NMOS tube, wherein the input end of the second PMOS tube is connected with the conversion voltage end of the voltage source, the control end of the second PMOS tube is connected with the intermediate signal, and the output end of the second PMOS tube outputs the output signal; the input end of the second NMOS tube is connected with the grounding end of the voltage source, the control end of the second NMOS tube is connected with the intermediate signal, and the output end of the second NMOS tube outputs the output signal.
5. The cross-potential level shift circuit of claim 4, wherein the voltage dividing module comprises a first resistor and a second resistor, one end of the first resistor is connected with a conversion voltage end of the voltage source, the other end of the first resistor is connected with one end of the second resistor and the input signal processing module respectively, and the other end of the second resistor is connected with a ground end of the voltage source.
6. The cross-potential level shift circuit of claim 5, wherein a ratio of the second resistor to a sum of the resistances of the first resistor and the second resistor is greater than a ratio of a signal voltage shift amount of the input signal to the output signal to a voltage difference of a high level and a low level of the input signal.
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| JP3233069B2 (en) * | 1997-06-09 | 2001-11-26 | 日本電気株式会社 | High withstand voltage level detection circuit |
| JP4571431B2 (en) * | 2004-04-30 | 2010-10-27 | ルネサスエレクトロニクス株式会社 | Signal amplification circuit |
| US7705630B1 (en) * | 2009-05-20 | 2010-04-27 | Ememory Technology Inc. | Negative voltage level shifter having simplified structure |
| CN205212814U (en) * | 2015-09-11 | 2016-05-04 | 英特格灵芯片(天津)有限公司 | Level conversion's device |
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Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103997334A (en) * | 2013-02-20 | 2014-08-20 | 精工电子有限公司 | Level shift circuit |
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| CN109861684A (en) | 2019-06-07 |
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