JP3233069B2 - High withstand voltage level detection circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a high withstand voltage level detecting circuit, and more particularly to a high withstand voltage level detecting circuit with high speed and low power consumption.

[0002]

2. Description of the Related Art Attenuating resistors of this kind of conventional high withstand voltage level detecting circuit are used as a level adjusting means for a supply signal in a tester for a semiconductor device, for example. Referring to FIG. 6 which shows a circuit diagram of an example of the above-described conventional high withstand voltage level detection circuit, this circuit has an input terminal 1
1 has an attenuating resistor 1 for dividing a high-voltage input signal supplied thereto and a level detecting circuit section 4 for detecting the divided signal and outputting the signal to an output terminal. The attenuating resistor 1 has one end connected to the input terminal. 11 and a variable resistor R2 having one end connected to the terminal 15 of the ground potential GND and the other end connected to each other.
The divided voltage is taken out from the connection point at the other end.

[0003] The level detection circuit section 4 is provided with a power supply voltage VDD1.
Element R connected at one end to the power supply terminal 14 to which
3 and the drain electrode of an N-channel MOS transistor N1 whose source electrode is connected to the ground terminal 15 are connected to each other, and the drain electrode of the N-channel MOS transistor N1 is connected to the power supply terminal 14 and the ground terminal 15. A drain electrode of the N-channel MOS transistor N2 is connected to an output terminal, while being connected to a gate electrode of a CMOS inverter for waveform shaping composed of a P-channel MOS transistor P1 and an N-channel MOS transistor N2 connected in series. It is configured.

In this conventional circuit, for example, 3.3 V or 5.0 V is applied to the power supply terminal 14, and the input terminal IN
11 is supplied with a high-voltage input signal at an amplitude voltage of, for example, 500 V, and the variable resistance element R of the attenuation resistor 1
At 1 and R2, for example, the voltage is divided to 5 V and taken out. When the divided voltage 5V is applied to the level detection circuit 4, the low-breakdown-voltage N-channel MOS transistor N1 of the level detection circuit 4 detects the input level based on the threshold Vt.

Therefore, the detection level is adjusted by adjusting the resistance ratio of the variable resistance elements R1 and R2 of the attenuation resistor 1 and by changing the N-channel MOS transistors having different thresholds Vt to the low withstand voltage N-channel MOS transistors N.
1 was used.

Referring to FIG. 7 showing a circuit diagram of another conventional example, this circuit has an attenuating resistor 1 and a level detecting circuit section 4, and one end of the attenuating resistor 1 has a power supply terminal of a power supply potential VDD1. 14 connected to the variable resistance element R1
And a variable resistance element R2 having one end connected to the input terminal 11.
Are connected to each other, and a divided voltage is taken out from the connection point of the other end.

[0007] The level detection circuit section 4 is provided with a power supply voltage VDD1.
Element R connected at one end to the power supply terminal 14 to which
3 and the drain electrode of an N-channel MOS transistor N1 whose source electrode is connected to the ground terminal 15 are connected to each other, and the drain electrode of the N-channel MOS transistor N1 is connected to the power supply terminal 14 and the ground terminal 15. A drain electrode of the N-channel MOS transistor N2 is connected to an output terminal, while being connected to a gate electrode of a CMOS inverter for waveform shaping composed of a P-channel MOS transistor P1 and an N-channel MOS transistor N2 connected in series. It is configured.

Referring to the conventional circuit having the above-described configuration,
In this conventional circuit, a negative power supply is used. For example, 3.3 V or 5.0 V is applied to the power supply terminal 11 as in the above-described example, and a high-voltage input signal is applied to the input terminal IN11 as an input signal, for example, an amplitude voltage of 500 V Is applied to the terminal 11 and divided by, for example, 5 V by the attenuating resistors R1 and R2 and taken out. When a voltage 5V divided from the power supply voltage VDD is applied to the level detection circuit section 4, the low-breakdown-voltage N-channel MOS transistor N1 of the level detection circuit section 4
Has detected the input level based on the threshold value Vt.

[0009]

In the above-described conventional high withstand voltage level detection circuit, the variable resistance element R2 of the attenuation resistor 1 having one end connected to the ground potential GND terminal 15 and the variable resistance element having one end connected to the input terminal 11 are provided. When the other ends of R1 are connected to each other and a divided voltage is taken out from the connection point of the other end, the power supply potential V
The other ends of the variable resistance element R1 of the attenuation resistor 1 connected to the power supply terminal 14 of the DD1 and the variable resistance element R2 connecting one end to the input terminal 11 are connected to each other. Also, when a high voltage input signal is always connected to the attenuating resistor, a current always flows and the current consumption is large.

There is also a method of increasing the resistance value of the attenuating resistor in order to suppress the current consumption. However, the resistance value, the resistance element, the gate electrode capacitance of the N-channel MOS transistor to which the resistance element is connected, and the connection between these elements are described. There is also a disadvantage that the time constant of the parasitic capacitance including the wiring capacitance increases, and the signal delay output from the high breakdown voltage level detection circuit increases.

SUMMARY OF THE INVENTION An object of the present invention is to provide a high withstand voltage level detection circuit that reduces power consumption and reduces signal delay.

[0012]

The high voltage level detection circuit according to the present invention is characterized by a switch means for inputting a high voltage input signal having a predetermined amplitude voltage and a cycle of a predetermined duty ratio, and this switch. Detecting first and second attenuating resistors for dividing the high-voltage input signal connected in series between an output terminal of the means and a ground potential, and detecting an effective level of the high-voltage input signal divided by the attenuating resistors; Level detecting means for outputting to the output terminal a first logic level based on a first power supply potential or a second power supply potential higher than the first power supply potential, and a transition for each rising or falling cycle of the high voltage input signal A third power supply potential or a first power supply potential higher than the first power supply potential in response to the logic signal of the first logic level given at the timing of the process.
Comprising of the level shifting means in a second logic level according to the power supply potential and outputs a control signal to said switch means, said high voltage input signal having a third power supply potential and equal level of the amplitude voltage, the logic signal is the The first logic level is applied to the first and second attenuating resistors only during the first logic level period, and is output from the level detection means at the first logic level.

[0013]

[0014]

[0015]

[0016]

[0017]

DESCRIPTION OF THE PREFERRED EMBODIMENTS First, an embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a circuit diagram of a high withstand voltage level detection circuit of the present invention, and FIG. 2 is a waveform diagram for explaining the operation of the circuit. Referring to FIG. 1, it is assumed that a first power supply potential VDD1 and a second power supply potential VDD2 higher than this potential are supplied as power supply voltages of the high breakdown voltage level detection circuit. This circuit is supplied with an attenuating resistor 1 for dividing an inputted high-voltage input signal, a high-withstand-voltage switch 2 for switching whether or not to apply the inputted high-voltage signal to the attenuating resistor 1, and a second power supply potential VDD2.
In response to a control signal, a level shift circuit unit 3 that controls conduction of the input switch 1 by a signal level-shifted to correspond to a high voltage signal, and a first power supply potential VDD1 are supplied. And a level detection circuit section 4 for detecting an effective level of the signal thus obtained by a threshold value of a transistor in an input stage and outputting the detected signal to an output terminal OUT12.

The attenuation resistor 1 has one end connected to the variable resistance element R1 having one end connected to the high voltage switch 2 and the other end connected to the variable resistance element R2 having the other end connected to the terminal 15 of the ground potential GND. Is configured to take out the divided voltage from the connection point.

The high voltage switch 2 comprises a high voltage P channel MOS transistor and a high voltage N channel MO.
It is composed of a transfer gate composed of an S transistor.

The level shift circuit section 3 includes a P-channel type M for connecting a drain electrode to a power supply terminal 16 of a second power supply voltage VDD2 higher than the first power supply voltage VDD1.
The gate electrodes of the OS transistors P2 and P3 are connected to the other drain electrode, and the drain electrode of the P-channel MOS transistor P2 is connected to the drain electrode of an N-channel MOS transistor N3 whose source electrode is connected to GND. P-channel type MOS transistor P3
Is connected to the drain electrode of an N-channel MOS transistor N4 whose source electrode is connected to GND, the gate electrode of this N-channel MOS transistor N4 is connected to the output terminal of the inverter 6, and its input terminal is connected to the N-channel MOS transistor N4. Connected commonly to the gate electrode of the MOS transistor N3 and the logic signal input terminal 13,
The control voltages on the P-channel side and the N-channel side of the high breakdown voltage switch are extracted from the drain electrodes of the OS transistors P2 and P3, respectively.

The level detection circuit section 4 is provided with a power supply voltage VDD1.
Element R connected at one end to the power supply terminal 14 to which
3 and the drain electrode of an N-channel MOS transistor N1 whose source electrode is connected to the ground terminal 15 are connected to each other, and the drain electrode of the N-channel MOS transistor N1 is connected to the power supply terminal 14 and the ground terminal 15. A gate is connected to a gate electrode of a waveform shaping CMOS inverter composed of a P-channel type MOS transistor P1 and an N-channel type MOS transistor N2 connected in series, and a drain electrode of the N-channel type MOS transistor N2 is connected to an output terminal OUT12. It is configured.

The operation of the high breakdown voltage level detection circuit having the above-described configuration will be described with reference to FIGS.

The power terminal 14 has, for example, VDD1 = 5.0.
VDD2 = 500V is applied to V and the power supply terminal 16,
A high voltage input signal is applied to the input terminal IN11 as an input signal, for example, with an amplitude voltage of 500 V and a duty of 50%. The variable resistance element R1 of the attenuation resistor 1 is set to 450 KΩ, the variable resistance element R2 is set to 50 KΩ, and the resistance element R3 is set to 10 KΩ. In FIG. 2, each voltage axis is simplified for easy understanding.

First, when the above-mentioned high voltage input signal 500V is applied to the input terminal 11 and a control pulse is not applied to the logic signal input terminal 13 yet and the logic signal input terminal 13 is in a low level state, the level shift circuit 3 N-channel type M
Since the gate electrode of the OS transistor N3 goes low and the gate electrode of the N-channel MOS transistor N4 goes high, the N-channel MOS transistor N
4 becomes conductive and its drain electrode goes to low level.

The P-channel type M
The potential of the gate electrode of OS transistor P2 is lowered, P-channel MOS transistor P2 is rendered conductive, and its drain electrode is raised to power supply voltage VDD2 level.

Therefore, the P-channel MOS transistor of the high breakdown voltage switch 2 to which the high level of the drain electrode of the P-channel MOS transistor P2 is supplied is turned off, and the low level of the drain electrode of the P-channel MOS transistor P3 is supplied. Since the N-channel type MOS transistor of the high breakdown voltage switch 2 is also turned off, the high breakdown voltage switch 2
The 00V input is cut off, no high voltage is supplied to the attenuator resistor 1, and the divided voltage is also 0V.

Since the input voltage to be detected in the level detection circuit section 4 is 0 V, the N-channel type MOS transistor 1 for level detection is in a non-conductive state, and the power supply voltage VDD1 of the drain electrode has the next-stage waveform shaping inverter. , And the inverted low level is output to the output terminal OUT12.

Next, a high voltage input signal 50 is input to the input terminal 11.
When 0V is applied, this voltage is changed from 0V to 500V.
A control pulse of 5 V is applied to the logic signal input terminal 13 in accordance with the timing of the process of transition to. Here, the description will be made at the timing of the process in which the high voltage input signal transitions from 0V to 500V, but the present invention is not limited to this, and the control pulse may be applied in the process of transitioning from 500V to 0V.

When the logic signal input terminal 13 is at the high level, the gate electrode of the N-channel MOS transistor N3 of the level shift circuit section 3 is at the high level.
Since the gate electrode of the channel type MOS transistor N4 is at a low level, the N-channel type MOS transistor N3 is changed from a non-conductive state to a conductive state, and its drain electrode is changed from a VDD2 level to a low level.

The P-channel type M is provided by this low leveler.
The potential of the gate electrode of the OS transistor P3 is lowered, the P-channel MOS transistor P3 changes from the non-conductive state to the conductive state, and its drain electrode is connected to the power supply voltage VDD.
You are raised to two levels.

Due to the state transition of the level shift circuit section 3, the P-channel type MOS transistor of the high breakdown voltage switch 2 to which the low level of the drain electrode of the P-channel type MOS transistor P2 is supplied is changed from the non-conductive state to the conductive state, Since the N-channel type MOS transistor of the high voltage switch 2 to which the high level of the drain electrode of the type MOS transistor P3 is supplied also changes from the non-conductive state to the conductive state, the high voltage switch 2 becomes conductive.

Therefore, 500 V of the high voltage input signal is applied to the attenuating resistor 1 only during the conduction period of the high voltage switch 2, and this period is a period during which the high voltage input signal transitions from 0V to 500V . in elevated variable resistor a predetermined voltage has R1 and the voltage dividing by the ratio of the resistance values of R2 (partial pressure levels this is adjusted to the vicinity of the threshold voltage of the next stage of the N-channel type MOS transistor 1) The signal is output to the level detection circuit unit 4 in the next stage.

The level detection circuit section 4 uses the voltage level obtained by dividing the high-voltage input signal to be detected as the N-channel type MOS transistor 1 for detecting the level. The signal is read at Vt, becomes conductive, and the drain electrode becomes low level. The low level is shaped by the next-stage waveform shaping inverter, and the inverted high-level pulse is output to the output terminal OUT12.

That is, by inputting a logic control signal from the outside and turning on the high withstand voltage switch only for the time required for level detection and connecting the high voltage input signal to the attenuating resistor 1, a high voltage is applied to the attenuating resistor only for the necessary time. Since the current flowing through this resistor also flows only for a short time, the current consumption is reduced.

Next, in a modification of the first embodiment, a first power supply voltage VDD1 and a third power supply voltage VSS, which is a negative high voltage, are supplied as power supply voltages. Referring to FIG. 3 which shows a circuit diagram of a high breakdown voltage level detection circuit to which a negative high voltage is applied, the high breakdown voltage level detection circuit includes an attenuation resistor 1, a high breakdown voltage switch 2, and a first power supply potential. It has a level shift circuit section 3 that operates between VDD1 and the third power supply potential VSS, and a level detection circuit section 4 that operates between the first power supply potential VDD1 and the ground potential GND.

The attenuating resistor 1 connects the other end of each of the variable resistance element R1 having one end connected to VDD1 and the variable resistance element R2 having one end connected to the output end of the high voltage switch 4, and connects the other end to each other. It is configured to take out the divided voltage from the point.

The high withstand voltage switch 2 is composed of a transfer gate composed of a high withstand voltage P-channel MOS transistor and a high withstand voltage N-channel MOS transistor as described above.

The level shift circuit section 3 connects the gate electrodes of the N-channel MOS transistors N3 and N4 respectively connecting the source power supply to VSS to the other drain electrode, and connects the drain electrode of the P-channel MOS transistor N3 to the other. The source electrode is connected to the drain electrode of the P-channel MOS transistor P2 connected to the first power supply voltage VDD1, and the N-channel MOS transistor N
4 is connected to the first power supply voltage VDD by the source electrode.
1 is connected to the drain electrode of the P-channel MOS transistor P3, the gate electrode of which is connected to the output terminal of the inverter 6, and whose input terminal is the gate electrode of the P-channel MOS transistor P2. And a common connection to the logic signal input terminal 13 so as to extract control voltages on the N-channel side and the P-channel side of the high breakdown voltage switch 2 from the drain electrodes of the N-channel MOS transistors N3 and N4, respectively.

Since the level detection circuit section 4 has the same configuration as that of the first embodiment, the description of the configuration here is omitted.

The circuit operation of the modified example described above basically operates according to the first embodiment. That is, for example, VDD1 = 5.0 V is applied to the power supply terminal 14 and VSS = −500 V is applied to the power supply terminal 17, and a negative high-voltage input signal is applied to the input terminal 11 with, for example, an amplitude voltage of 500 V and a duty of 50%. The variable resistance element R1 of the attenuation resistor 1 is set to 50 KΩ, the variable resistance element R2 is set to 450 KΩ, and the resistance element R3 is set to 10 KΩ.

First, when the above-mentioned negative polarity high voltage input signal -500 V is applied to the input terminal 11 and the control pulse is not yet applied to the negative polarity logic signal input terminal 13 and the input terminal 11 is at a high level. In other words, the gate electrode of the P-channel MOS transistor P3 of the level shift circuit section 3 is turned on because the high level of the logic signal is inverted by the inverter 6 and is in the low level state, and the drain electrode is raised to the VDD1 level.

The N-channel MOS transistor N3 to which this high level is applied becomes conductive, and its drain electrode is lowered to the VSS potential . On the other hand, the gate electrode of the P-channel MOS transistor P2 receives the high level of the logic control signal as it is, so that the P-channel MOS transistor P2 is off.

Therefore, the P-channel type MOS transistor of the high breakdown voltage switch 2 to which the high level of the drain electrode of the N-channel type MOS transistor N4 is supplied is turned off, and the low level of the drain electrode of the N-channel type MOS transistor N3 is supplied. Since the N-channel type MOS transistor of the high voltage switch 2 is also turned off, the high voltage switch 2
500 V is cut off, no negative high voltage is supplied to the attenuating resistor 1, and there is no output of the divided voltage.

Therefore, the input terminal of the next-stage level detection circuit section 4 is pulled up to VDD1 by the variable resistor R1, and the waveform shaping inverter outputs a low level to the output terminal OUT12.

Next, the high voltage input signal -5 is input to the input terminal 11.
When the control pulse applied to the logic signal input terminal 13 is in the ON state and the low level pulse is applied in the state where 00V is applied, the level shift circuit unit 3
Since the gate electrode of the P-channel MOS transistor P2 is at a low level, it is rendered conductive and its drain electrode is pulled up from the low level to the high level of VDD1.

N-channel MOS transistor N4 having this high level applied to its gate electrode is rendered conductive, and its drain electrode is changed from high level to ground potential GND.
To be reduced to On the other hand, since the low level of the logic signal is inverted by the inverter 6 and the gate electrode of the P-channel MOS transistor P3 is in a high-level state, the P-channel MOS transistor P3 is turned off.

Therefore, the N-channel MOS transistor of the high breakdown voltage switch 2 to which the high level of the drain electrode of the N-channel MOS transistor N3 is supplied is turned on, and the low level of the drain electrode of the N-channel MOS transistor N4 is supplied. Of high withstand voltage switch 2
Since the channel type MOS transistor also becomes conductive,
The high voltage switch 2 allows the high voltage input signal to be -50.
0 V is applied to the attenuating resistor 1 only during the conduction period of the high voltage switch 2.

Assuming that this period is a period in which the -500 V of the high voltage input signal transits to 0 V, the predetermined voltage that has risen during this transition period is divided by the ratio of the resistance values of the variable resistors R1 and R2. The voltage (this divided level is adjusted to the vicinity of the threshold voltage of the N-channel MOS transistor 1 in the next stage, as in the above-described embodiment) is output to the level detection circuit unit 4 in the next stage.

The level detection circuit section 4 applies the voltage level obtained by dividing the high voltage input signal to be detected to an N-channel type MOS transistor 1 for level detection. And the drain electrode becomes low level, the low level is shaped by the next-stage waveform shaping inverter, and the inverted high-level pulse is output to the output terminal OUT12.

Also in the case of this embodiment, a logic signal is inputted from the outside and the high voltage switch is turned on only for the time required for level detection, and the high voltage input signal is connected to the attenuating resistor 1, so that only the necessary time is detected. A high voltage is supplied to the attenuator resistor, and the current flowing through this resistor also flows only for a short time, so that the current consumption is reduced.

Referring to FIG. 4 showing a circuit diagram of the second embodiment, this high withstand voltage level detection circuit uses an attenuating resistor 1, a high withstand voltage switch 2, a level shift circuit section 3, and a comparator. A level detection circuit section 5 for adjusting the reference voltage of the comparator with a reference voltage variable resistor in order to adjust the detection level, and an inverter 6.

The attenuating resistor 1, the high voltage switch 2, and the level shift circuit 3 are the same as those in the first embodiment, and the description of the configuration is omitted here.

The level detection circuit section 5 has a first power supply voltage V
The source electrodes of P-channel MOS transistors P7 and P8 are connected to the drain electrode of P-channel MOS transistor P6 that connects the source electrode to DD1.
N-channel MOS transistors N5 and N5 are connected to the drain electrodes of channel MOS transistors P7 and P8, respectively.
The source electrode of N6 is connected, the respective gate electrodes are commonly connected to the drain electrode of N-channel MOS transistor N5, the source electrode is commonly connected to ground potential GND, and the gate electrode of P-channel MOS transistor P8 is variable. The resistors R6 and R7 are connected to the power supply voltage VDD1.
And a comparator for connecting a gate electrode of the P-channel MOS transistor P7 to a divided voltage output terminal of the attenuator resistor 1 and a gate electrode to a drain electrode. P
A constant current source in which two sets of channel type MOS transistors P4 and P5 are connected in series between power supply voltage VDD1 and ground potential GND, and the drain electrode of P channel type MOS transistor P4 is connected to the gate electrode of P channel type MOS transistor P6 of the comparator. And a P-channel MOS transistor P9 and an N-channel MOS transistor N connecting the drain electrode of N-channel MOS transistor N6 to the input terminal and the output terminal to output terminal OUT13.
And 7 inverters.

The operation of the high breakdown voltage level detection circuit having the above configuration will be described. Referring to FIG. 4 again, this circuit includes, for example, V
DD1 = 5.0 V and VDD2 = 5 at the power supply terminal 16
00V, and a high voltage input signal is input to the input terminal 11 as an input signal IN, for example, with an amplitude voltage of 500 V and a duty of 50.
Give in%. The resistance element R4 of the attenuation resistor 1 is 45
0 KΩ, the variable resistance element R6 is set to 100 KΩ, and the variable resistance element R7 is set to 150 KΩ.

First, when the control signal is not yet applied to the logic signal input terminal 13 and the logic signal input terminal 13 is at the low level while the input terminal 11 is supplied with the above-mentioned high voltage input signal 500 V, the level shifter 3 is used as described above. Since the drain electrode of the N-channel MOS transistor N3 is at a high level and the drain electrode of the N-channel MOS transistor N4 is at a low level,
Is in a cut-off state, a high voltage input signal is not applied to the attenuating resistor 1, and the gate electrode of the P-channel MOS transistor P7 of the level detection circuit section 5, that is, the potential of the comparison voltage input terminal is set to the ground potential by the resistance element R5. Pulled down.

Since the current flowing through the P-channel MOS transistor P7 and the N-channel MOS transistor N5 increases due to the decrease in the potential of the comparison voltage input terminal, the mirror-related P-channel MOS transistors P8 and N8 As for the current flowing through the MOS transistor N6, the current flowing through the P-channel type MOS transistor P6 is suppressed to a constant current, and the P-channel type
Since the gate electrode of the S transistor P8 is fixed to the reference voltage value determined by the variable resistors R6 and R7, the current decreases conversely, and the potential of the drain electrode of the N-channel MOS transistor N6 becomes high level. To rise. This high level is output as a low level to the output terminal OUT12 via the next-stage inverter.

Next, when a high-level (for example, 5 V) control pulse is applied to the logic signal input terminal 13 while the high-voltage input signal 500 V is continuously applied to the input terminal 11, the level shift circuit 3 The drain electrode of the N-channel MOS transistor N4 changes from low level to high level,
, Respectively, changes from a high level to a low level state, so that the high breakdown voltage switch 2 changes from a cut-off state to a conductive state.

Therefore, 500 V of the high voltage input signal is applied to the attenuating resistor 1 only during the conduction period of the high voltage switch 2, and this period is a period during which the high voltage input signal transitions from 0V to 500V. Is divided by the ratio of the resistance values of the resistance elements R1 and R2 (this division level is adjusted to a vicinity of a reference voltage determined by the division ratio of the variable resistors R6 and R7 of the next stage comparator). ) Is output to the next-stage level detection circuit section 5.

In the level detection circuit 5, the signal is supplied to the gate electrode (comparative voltage input terminal) of the P-channel MOS transistor P7 of the comparator.

Since the potential of the comparison voltage input terminal has risen from the pull-down state to the high level of the divided voltage, the P-channel MOS transistor P7 and the N-channel MO transistor
The current flowing through the S-transistor N5 changes from increasing to decreasing, and the current flowing through the P-channel MOS transistor P8 and the N-channel MOS transistor N6 in a mirror relationship is suppressed to a constant current flowing through the P-channel MOS transistor P6. And P-channel MOS
The gate electrode of the transistor P8 is connected to the variable resistors R6 and R6.
Since the reference voltage value is fixed at 7, the current conversely turns from decreasing to increasing, and the potential of the drain electrode of the N-channel MOS transistor N6 falls from high level to low level. This low level is output as a high level to the output terminal OUT12 via the next-stage inverter.

That is, also in the case of the second embodiment, by inputting a logic signal from the outside and turning on the high voltage switch only during the time required for level detection, and connecting the high voltage input signal to the attenuating resistor 1, A high voltage is supplied to the attenuator resistor only for a necessary time, and the current flowing through this resistor flows only for a short time, so that the current consumption is reduced.

Next, in a modification of the above-described second embodiment, a first power supply voltage VDD1 and a third power supply voltage VSS, which is a negative high voltage, are supplied as power supply voltages. Referring to Figure 5 showing a circuit diagram of the high voltage level detecting circuit for a negative polarity high voltage is applied as a signal, the high-voltage level detection circuit of this modification, attenuation resistor 1
A high withstand voltage switch 2, a level shift circuit section 3 operating between a first power supply potential VDD1 and a third power supply potential VSS, a first power supply potential VDD1 and a ground potential GND.
Level detection circuit unit 5 using a comparator operating between
And an inverter 6.

Among the components described above, the attenuation resistor 1, the high voltage switch 2, and the level shift circuit 3 are the same as those of the modification of the first embodiment.
The level detection circuit unit 5 using the comparator is the same as the configuration of the second embodiment described above, and the description of the configuration is omitted here.

The operation of the high breakdown voltage level detection circuit having the above configuration will be described. Referring to FIG. 5 again, this circuit includes a power supply terminal 11 like the modification of the first embodiment.
For example, VDD1 = 5.0 V and VDD2 = −50
0 V, and a high voltage input signal is input to the input terminal 11 as the input signal IN, for example, with an amplitude voltage of -500 V and a duty of 50.
Give in%. The resistance element R4 of the attenuation resistor 1 is 50
KΩ, the resistance element R5 is set at 450 KΩ, the variable resistance element R6 is set at 150 KΩ, and R7 is set at 100 KΩ, for example.

First, when the control signal is not applied to the logic signal input terminal 13 and the logic signal input terminal 13 is at the high level while the input terminal 11 is supplied with the above-mentioned high voltage input signal -500 V, as described above. Level shift circuit section 3
Since the drain electrode of the N-channel type MOS transistor N4 is at the high level and the drain electrode of the N-channel type MOS transistor N3 is at the low level, the high voltage switch 2 is in the cut-off state, and the attenuating resistor 1 has the high voltage input signal. And the potential at the comparison voltage input terminal of the level detection circuit unit 5 is pulled up to VDD1 by the resistance element R4.

Since the potential at the comparison voltage input terminal is pulled up, the current flowing through P-channel MOS transistor P7 and N-channel MOS transistor N5 decreases, so that P-channel MOS transistors P8 and N As for the current flowing through the channel type MOS transistor N6, the current flowing through the P channel type MOS transistor P6 is suppressed to a constant current, and the gate electrode of the P channel type MOS transistor P8 has a variable resistance R
6 and R7 are fixed to the reference voltage value, and conversely, the current increases, and the N-channel type M
The potential of the drain electrode of the OS transistor N6 drops to a low level. This low level is output as a high level to the output terminal OUT12 via the next-stage inverter.

Next, when a low-level control pulse is applied to the logic signal input terminal 13 while the high-voltage input signal -500 V is continuously applied to the input terminal 11, the N-channel MOS of the level shift circuit section 3 is turned on. Since the drain electrode of the transistor N3 transitions from low level to high level and the drain electrode of the N-channel MOS transistor N4 transitions from high level to low level, the high breakdown voltage switch 2 changes from the cut-off state to the conducting state. -500 V of the voltage input signal is applied to the attenuating resistor 1 only during the conduction period of the high voltage switch 2,
Since this period is a period in which -500 V of the high voltage input signal transits to 0 V, a predetermined voltage that has risen during this transition period is divided by the ratio of the resistance values of the resistance elements R4 and R5 (in this case, The voltage division level is adjusted to a value near the reference voltage determined by the voltage division ratio of the variable resistors R6 and R7 of the comparator at the next stage.

In the level detection circuit 5, the divided voltage is applied to the gate electrode (comparative voltage input terminal) of the P-channel MOS transistor P7 of the comparator.

Since the potential of the comparison voltage input terminal drops from the pull-up state to the low level of the divided voltage, the P-channel MOS transistor P7 and the N-channel MO
The current flowing through the S-transistor N5 changes from a decrease to an increase, and the current flowing through the P-channel MOS transistor P8 and the N-channel MOS transistor N6 in a mirror relationship is suppressed to a constant current through the P-channel MOS transistor P6. And P-channel MOS
The gate electrode of the transistor P8 is connected to the variable resistors R6 and R6.
On the other hand, since the reference voltage is fixed to the reference voltage determined by 7, the current starts to decrease from increasing, and the potential of the drain electrode of the N-channel MOS transistor N6 rises from a low level to a high level. This high level is output as a low level to the output terminal OUT12 via the next-stage inverter.

That is, also in the case of this modified example, by inputting a logic signal from the outside and turning on the high withstand voltage switch only for the time required for level detection and connecting the high voltage input signal to the attenuating resistor 1, only the necessary time is obtained. A high voltage is supplied to the attenuator resistor, and the current flowing through this resistor also flows only for a short time, so that the current consumption is reduced.

In particular, in the second embodiment and its modifications, the attenuating resistor 1 is a fixed resistance element without being varied, so that the resistance element can be made smaller and the parasitic capacitance can be kept small.

[0072]

As described above, in the high withstand voltage level detection circuit of the present invention, a high withstand voltage switch is provided in a stage preceding the attenuating resistor, and the high withstand voltage switch is turned on only during the time required for level detection, and a high voltage input is provided. By connecting the signal to the attenuating resistor, it is possible to realize a low power consumption high withstand voltage level detection circuit without sacrificing the delay time.

As a result of the spice simulation, the voltage amplitude of the high-voltage input signal was 500 V and the duty was 5
In the case of the 0% pulse waveform, it was confirmed that the delay time did not change and the power consumption was reduced to で は in comparison with the conventional circuit.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a high withstand voltage level detection circuit according to a first embodiment of the present invention.

FIG. 2 is a waveform chart for explaining a circuit operation of the high withstand voltage level detection circuit of FIG. 1;

FIG. 3 is a circuit diagram of a modification of the first embodiment of the present invention.

FIG. 4 is a circuit diagram of a high withstand voltage level detection circuit according to a second embodiment of the present invention.

FIG. 5 is a circuit diagram of a modification of the second embodiment of the present invention.

FIG. 6 is a circuit diagram of a conventional high withstand voltage level detection circuit.

FIG. 7 is a circuit diagram of another example of a conventional high withstand voltage level detection circuit.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Attenuating resistance 2 High voltage switch 3 Level shift circuit part 4, 5 Level detection circuit part 6 Inverter R1, R2, R6, R7 Variable resistance element R3, R4, R5 Resistance element P1-9 P channel type MOS transistor N1-7N Channel type MOS transistor

Claims (1)

(57) [Claims] 1. A switch means for inputting a high voltage input signal having a predetermined amplitude voltage and a cycle of a predetermined duty ratio, and said high voltage connected in series between an output terminal of said switch means and a ground potential. First for input signal voltage division
And an effective level of the high-voltage input signal divided by these attenuating resistors and a first power supply potential or a second power supply potential higher than the first power supply potential. Level detection means for outputting a logic level to an output terminal; and a first power supply potential in response to a logic signal of the first logic level provided at a timing of a transition process for each rising or falling cycle of the high voltage input signal. Level shift means for outputting a control signal to the switch means at a second logic level higher than the third power supply potential or the first power supply potential, the level shift means having an amplitude voltage equal to the third power supply potential. high voltage input signal, said level with the logic signal is applied to said first and said second attenuating resistors only the first logic level period High-voltage level detection circuit, characterized in that output from the detection means at the first logic level.