JP3225903B2 - Output circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an output buffer circuit of a semiconductor integrated circuit, and more particularly to an output buffer circuit of a semiconductor integrated circuit that drives a capacitive load with a large current.

[0002]

2. Description of the Related Art FIG. 3 shows a conventional output buffer circuit of a semiconductor integrated circuit. The output buffer circuit includes an output control unit 1 that transmits an input signal IN to a next stage at a predetermined timing, a level shift unit 2 that converts a low voltage signal into a high voltage signal, and a first power supply (hereinafter, referred to as VDD2). And a second power supply (hereinafter, referred to as a P-channel MOS transistor P8 having a source connected to the output terminal OUT and a drain connected to the output terminal OUT).
VSS), the source of which is connected to the output terminal OUT, and the drain of which is connected to the N-channel MOS transistor N.
6 and a MOS output section 3 composed of the MOS output section 6. FIG. 4 shows FIG.
3 is a signal timing chart of the output buffer circuit of FIG.
When the input signal IN changes from a low level to a high level, the inverted signal a output from the inverter 1 (INV1) of the output control section 1 and the inverted delay signal c output from the INV6 cause the N-channel of the level shift section 2 to output. M
OS transistor N8, N-channel MOS of output unit 3
The transistors N6 are turned off.

On the other hand, a non-inverted delay signal (hereinafter simply referred to as a delay signal) b output from the INV 3 of the output control unit 1
As a result, the N-channel NOS transistor N7 of the level shift unit 2 is turned on, and the potential of the node d becomes VD
The potential changes from the vicinity of D2 (voltage lower than VDD2 by the threshold value of the P-channel MOS transistor P9) to the VSS potential. Thereby, the P channel MO of the output unit 3
At the same time when the S transistor P1 and the P-channel MOS transistor P10 of the level shift unit 2 are turned on, the potential of the node e changes from VSS to VDD2, and the P-channel MOS transistor P2 of the level shift unit 2
Is turned off.

During the period from when the N-channel MOS transistor N7 of the level shift unit 2 is turned on to when the P-channel MOS transistor P9 of the level shift unit 2 is turned off, the potential of the transistor P9 is changed from VDD2.
Through current I2 flows to VSS via the source and drain of the transistor N7 and the drain and source of the transistor N7. When the P-channel MOS transistor P8 of the output unit 3 is turned on, the load CL is charged, and the output signal OUT changes from the potential VSS to the potential VDD2. During this time, the charging current IOH1 corresponding to the ON-state drive capability of the P-channel MOS transistor P8 of the output unit 3
Flows from the power supply wiring of VDD2.

[0005]

In the conventional output buffer circuit, the M which constitutes the output section 3 corresponding to the load capacitance is set.
The gate width is determined so that the source-drain resistance of the OS transistor is set. At this time, if the driving capability of the output transistor is increased, the output signal OUT
Changes from the VSS level to the VDD2 level, a change in current at the time of switching becomes large, and power supply noise occurs. The power supply noise has a problem that a semiconductor integrated circuit having the output buffer circuit malfunctions or a signal waveform is distorted.

In view of the above, an object of the present invention is to provide a semiconductor integrated circuit which sets the drive current capability of a MOS transistor constituting an output buffer circuit to a desired level and reduces power supply noise generated at the time of switching. To provide an output buffer circuit.

[0007]

In view of the above, an output circuit according to the present invention is, in a first aspect, connected between a first power supply and an output terminal and turned on in response to an input signal. And a second conductive transistor connected in parallel to the first conductive transistor and turned on in response to a first delay signal generated after a lapse of a first predetermined time from an input signal. A first conductivity type transistor, a second conductivity type transistor connected between a second power supply and the output terminal, and turned off in response to a third delay signal generated after a lapse of a predetermined delay time from the input signal; It is characterized by having.

According to a second aspect of the present invention, there is provided an output circuit comprising: a first transistor of a first conductivity type; and a first signal connected in series with the first transistor of the first conductivity type at a first connection node. A first second conductivity type transistor, a second first conductivity type transistor, and a second connection node connected in series with the second first conductivity type transistor. A second signal responsive to a second signal which is an inverted signal of the first signal generated after a delay time of
And a conductive type transistor, wherein the first connection node is connected to the gate of the second first conductive type transistor, and the second connection node is connected to the gate of the first first conductive type transistor, respectively. A first level shift unit and the second level shift unit;
Is connected in series at a third connection node with the third first conductivity type transistor, and a second connection transistor is connected to the third first conductivity type transistor at a third connection node.
And a first output unit having a third second conductivity type transistor responsive to a third signal that is an inverted signal of the second signal generated after a predetermined time has elapsed. A fourth connection transistor connected to the gate of the fourth first conductivity type transistor, and a fourth connection node connected in series with the fourth first conductivity type transistor and a third predetermined time from the second signal. A fourth transistor of a second conductivity type responsive to a fourth signal occurring after a lapse of time.
And a fifth shift transistor including a fifth shift transistor connected to the gate of the fourth connection node and connected in parallel to the third shift transistor of the first conductivity type.
And an output unit.

In one embodiment of the output circuit of the present invention, an output transistor in an output section for charging / discharging a load capacitance of an output line is divided into a plurality of transistors, and a level shift circuit for controlling each gate electrode is provided. A predetermined delay time is provided for an input signal. By turning on only one output transistor during the period when the output signal changes,
The output changes gradually, and the peak value of the current flowing at that time is suppressed. In addition, the output change is assisted by setting a delay time so that other transistors are turned on after the output signal changes gradually or after the output potential reaches a certain potential. And the current drive capability of the output transistor can be set to a desired value. Also, depending on the setting of the delay time, the driving capability of the output transistor after the switching is completed can be secured.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described in more detail based on embodiments of the present invention with reference to the drawings. FIG.
FIG. 2 is a circuit diagram showing an output circuit according to one embodiment of the present invention. The output circuit of the present embodiment is an output buffer circuit for driving a capacitive load CL, and divides an output transistor section into a plurality of P-channel output transistors and first to third output transistors P3, P2, and P1. , Each VD
D2 and the output terminal OUT are connected in parallel.
An N-channel output transistor N1 is connected between the output terminal OUT and VSS. Further, the first to third level shift circuits 6 to 4 and the output control circuit 7 are provided with P-channel output transistors, and the output transistors P3,
P2 and P1 are controlled.

First P-channel output transistor P3
Is a P-channel M of the first level shift unit 6.
Drain of OS transistor P6 and N-channel MOS
The drain of transistor N4 is connected to the gate of P-channel transistor P7. The output signal b of INV3 of the output control unit 7 is provided at the gate of the N-channel transistor N4.
And the gate of the P-channel transistor P6 is
The drain of the P-channel transistor 7 and the drain of the N-channel transistor are connected to a node e which connects them to each other.

The second P-channel output transistor P2
Is the P-channel M of the second level shift unit 5
Connected to the OS transistor P5 and the drain of the N-channel MOS transistor N3. The output signal f of INV7 of the output control unit 7 is input to the gate of the N-channel transistor N3, and the gate of the P-channel transistor P5 is connected to the node e of the first level shift unit 6.

The third P-channel output transistor P1
Is a P-channel M of the third level shift unit 4.
Drain of OS transistor P4 and N-channel MOS
It is connected to the drain of the transistor N2, and the gate of the N-channel transistor N2 is connected to the INV8 of the output control unit 7.
Is input. Further, the gate of the P-channel transistor P4 is connected to the node e of the first level shift unit 5.

The output control unit 7 has a configuration similar to that of the conventional output control unit. The first inverter INV1 receives an input signal IN and outputs an inverted signal a, and outputs a delay signal b to which the input signal IN is input. A pair of cascaded inverters INV2 and INV3 to be output, and a cascaded inverter 3 which receives the input signal IN and outputs its delayed inverted signal c.
It has two inverters INV4, INV5, INV6. The output control unit 7 further includes a delay signal b from INV3.
A delay circuit 8 that further delays the delay signal to a next stage at a predetermined timing, a NAND circuit 1 (NAND1) that receives the output signal h and the delay signal b of the delay circuit 8 as inputs,
INV7 for inverting the output of the delay circuit 8 and outputting an output signal f, a delay circuit 9 for further delaying the output symbol h of the delay circuit 8 and transmitting it to the next stage at a predetermined timing, and an output signal i of the delay circuit 9
NAND2 receiving the input of the delay signal b and the delay signal b;
And INV8 that inverts the output of the above and outputs an output signal g. The inverted inverted signal c from the output control unit 7 is input to the gate of the N-channel output transistor N1.

The operation of the above embodiment will be described with reference to FIG. When the input signal IN changes from the low level to the high level, the first output, which is the output of the output control unit 7,
The inverted signal a forming the third signal and the inverted delayed signal c forming the third signal change from the high level to the low level. Therefore, the N-channel MOS transistor N5 of the first level shift unit 6 and the N-channel output MOS transistor N1 of the output unit are turned off. On the other hand, the delay signal b constituting the second signal of the output control unit 7 changes from a low level to a high level after a predetermined time. For this reason, first
The N-channel MOS transistor N4 of the level shift unit 6 is turned on, and the potential of the node d of the level shift unit 6 decreases, whereby the P-channel MOS transistor P7 and the first output transistor P3 of the level shift unit 6 Is turned on. Therefore, the potential of the node e of the level shift unit 6 starts to rise, and the P-channel MOS transistors P4, P4 of the level shift units 4, 5, 6
5, P6 are simultaneously turned off. At this time, a through current I flows through these transistors during a period from the time when the N-channel transistor N4 of the first level shift unit 6 is turned on to the time when the P-channel transistor P6 is turned off. At the same time, the first P-channel output transistor P3 is also turned on, so that the output terminal OUT
Also changes from a low level to a high level. Here, the first
The current driving capability of the output transistor P3 is suppressed to a predetermined value which is optimal for charging the capacitor CL connected to the output output terminal OUT without generating power supply noise.
The charging current IOH according to the current driving capability of the first output transistor P3 flows. As a result, the peak current value at the time of a signal change is kept low, and the output terminal OUT starts to change relatively slowly.

The signal f, which forms the fourth output signal of the INV7 of the output control unit 7, is a predetermined delay time t from the delay signal b.
After elapse of d1, the level changes from the low level to the high level . In response to this change, the N-channel MOS transistor N3 of the second level shift unit 5 is turned on, and the second output P-channel transistor P2 is turned on. At this time, since the transistor P5 has already been turned off, the through current does not flow in the second level shift unit 5 as described above. Here, the potential V1 immediately before the potential of the output terminal OUT reaches the high level VDD2 is equal to the second potential V1.
The delay time td1 is set so that the output transistor P2 is turned on, so that the potential of the output terminal OUT does not gradually change to the potential VDD2, but changes quickly to the potential VDD2. Can be done. Similarly, the signal g constituting the fifth output signal of the INV 8 of the output control unit 7 changes from the low level to the high level after a lapse of a predetermined delay time td2 from the change of the output signal h of the delay circuit 8, and N-channel MOS of 1 level shift unit 4
The transistor N2 is turned on, and the third output P-channel transistor P1 is turned on. Also here, since the transistor P4 is turned off first, no through current flows between the transistor P4 and the transistor N2. Since the delay time td2 is set to be equal to or longer than the time when the output terminal changes to the high level, the current driving capability of the output transistor after switching can be secured.

In the above embodiment, the current drive capability between the source and the drain of the first P-channel output transistor is suppressed to a predetermined value, so that the current value at the initial stage of the potential change is reduced. By setting the total current driving capability of the transistor and the second P-channel output transistor to a desired current driving capability,
A desired signal change is obtained. Further, the third P-channel output transistor can prevent malfunction of the output circuit due to noise after a signal change.

As described above, the present invention has been described based on the preferred embodiment. However, the output circuit of the present invention is not limited to the configuration of the above-described embodiment, and is not limited to the configuration of the above-described embodiment. The output circuit with various modifications and changes is also
It is within the scope of the present invention.

[0019]

As described above, according to the output circuit of the present invention, the influence on other circuits can be reduced by suppressing the power supply noise generated by suppressing the initial current change at the time of signal change. By reducing and reducing the current drive capability after the initial signal change or after the signal change, a desired signal transmission speed or a desired noise resistance characteristic can be obtained.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of an output circuit according to an embodiment of the present invention.

FIG. 2 is a timing chart of signals of the output circuit of FIG. 1;

FIG. 3 is a circuit diagram of a conventional output circuit.

FIG. 4 is a signal timing chart of the output circuit of FIG. 3;

[Explanation of symbols]

1, 7 output control unit 2, 4 to 6 level shift circuit unit 3 output unit 8, 9 delay circuit unit P1, P2, P3, P4, P5, P6, P7, P8, P
9, P10 P-channel MOS transistors N1, N2, N3, N4, N5, N6, N7, N8 N
Channel MOS transistor CL Load capacitance IN input terminal, input signal OUT output terminal, output signal VDD2, VSS power supply terminal INV1-8 Inverter circuit NAND1, NAND2 NAND gate

Claims (4)

(57) [Claims] (1)Connected between the first power supply and the output terminal
And a first first conductivity type transistor that is turned on in response to an input signal.
In parallel with the transistor and the first first conductivity type transistor.
Connected and occurs after a first predetermined time has elapsed from the input signal.
A second first conductivity that turns on in response to a first delay signal
Type transistor, between the second power supply and the output terminal
Connected after a predetermined delay time from the input signal.
A second conductivity type transistor that is turned off in response to the third delay signal generated.
With a transistor, The first first conductivity type transistor responds to the input signal.
When turned off, the second first conductivity type transistor is turned off.
The star is faster than responding to the first delayed signal and
It turns off later than responding to the input signal
Output circuit. (2)A first first conductivity type transistor;
In series with one first conductivity type transistor and a first connection node
Connected to the first second conductivity type transistor responsive to the first signal.
A transistor, a second first conductivity type transistor, and the second
In series with the first conductivity type transistor and the second connection node
Occurs after a first delay time has passed since the first signal
A second signal responsive to a second signal forming an inverted signal of the first signal.
And a second connection type transistor, wherein the first connection
A node is a gate of the second first conductivity type transistor;
And a second connection node is connected to the first first conductivity type transistor.
First level shift units respectively connected to the gates of the transistors
When, A third first conductivity, wherein the second node is connected to a gate
Transistor and the third first conductivity type transistor
And a third connection node connected in series with the second signal
Of the second signal generated after a lapse of a second predetermined time from
A third second conductivity type responsive to a third signal forming an inverted signal
And a first output having a transistor.
On the road, A fourth first node in which the first connection node is connected to a gate
A conductive type transistor and the fourth first conductive type transistor
And the second signal connected in series at the fourth connection node
To a fourth signal generated after a third predetermined time has passed since
A second transistor having a fourth second conductivity type transistor
A bell shift section, The fourth connection node is connected to a gate, and the third connection node is connected to the gate;
First conductivity type transistor Fifth first connected in parallel with the
A second output section comprising a transistor of a conductivity type.
And an output circuit characterized by: (3)The first connection node is connected to a gate;
A sixth transistor of the first conductivity type,
Connected in series at the fifth connection node
A fourth signal generated after a lapse of a fourth predetermined time from the fourth signal.
And a fifth second conductivity type transistor responsive to the signal
A third level shift unit having The fifth connection node is connected to a gate, and the third connection node is connected to a gate.
A seventh first transistor connected in parallel with the first conductivity type transistor
A third output unit comprising a transistor of a conductivity type.
The output circuit according to claim 4, wherein (4)A first first conductivity type transistor;
In series with one first conductivity type transistor and a first connection node
Connected to the first second conductivity type transistor responsive to the first signal.
A transistor, a second first conductivity type transistor, and the second
In series with the first conductivity type transistor and the second connection node
Occurs after a first delay time has passed since the first signal
A second signal responsive to a second signal forming an inverted signal of the first signal.
And a second connection type transistor, wherein the first connection
A node is a gate of the second first conductivity type transistor;
And a second connection node is connected to the first first conductivity type transistor.
First level shift units respectively connected to the gates of the transistors
When, A third first conductivity, wherein the second node is connected to a gate
Transistor and the third first conductivity type transistor
And a third connection node connected in series with the second signal
Of the second signal generated after a lapse of a second predetermined time from
A third second conductivity type responsive to a third signal forming an inverted signal
And a first output having a transistor.
On the road, A fourth first node in which the first connection node is connected to a gate
A conductive type transistor and the fourth first conductive type transistor
And the second signal connected in series at the fourth connection node
A fourth signal generated after a lapse of a third predetermined time from
Fourth second conductivity responsive to a signal of a logical product with the second signal
A second level shift unit having a type transistor; The fourth connection node is connected to a gate, and the third connection node is connected to the gate;
A fifth first transistor connected in parallel to the first conductivity type transistor
A second output comprising a conductive type transistor; Be prepared
And an output circuit characterized by: