KR100318267B1 - CMOS output buffer for controlling drive current - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a CMOS output buffer circuit for controlling driving current by weakly turning on a CMOS transistor at an output stage in a CMOS output buffer circuit of a semiconductor device. The CMOS output buffer circuit according to the present invention has a first output unit including a first pull-up driver for supplying a power voltage to an output terminal, a first pull-down driver for supplying a ground voltage to the output terminal, and a power supply to the output terminal. A second output including a second pull-up driver for supplying a voltage and a second pull-down driver for supplying a ground voltage to the output terminal, and a first input for receiving a data signal and an enable signal to control the first pull-up driver An input unit for generating a signal and a second input signal for controlling the first pull-down driver, receiving the first input signal and transmitting the signal as a signal for controlling the second pull-up driver according to a control signal, and transmitting the second input signal. And a control unit for receiving a signal and transmitting the signal as a signal for controlling the second pull-down driver by the control signal. It features.

Description

CMOS output buffer circuit for controlling drive current

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an output buffer circuit of a semiconductor device, and more particularly to a complementary metal oxide semiconductor (CMOS) output buffer circuit for controlling driving current by weakly turning on a CMOS transistor at an output stage.

In general, in the CMOS output buffer circuit, a plurality of CMOS transistors including a P-channel metal oxide semiconductor transistor (PMOS transistor) and an N-channel metal oxide semiconductor transistor (NMOS transistor) are connected in parallel. In such a CMOS output buffer circuit, in a low voltage condition where the power supply voltage is low, each CMOS transistor of the output stage is turned on at the same time to transmit an output signal.However, in a high voltage condition where the power supply voltage is high, each CMOS transistor of the output stage simultaneously outputs. In the case of transmission, the driving current becomes large, and the circuit may malfunction due to the peak value of the instantaneous current.

In order to eliminate the malfunction that may occur due to the increase of the driving current in the high voltage condition in which the power supply voltage is high, conventionally, only a part of the plurality of CMOS transistors constituting the output stage is turned on while the high voltage condition is partially turned off. By controlling the magnitude of the drive current.

As another method of eliminating circuit malfunction due to an increase in driving current under high voltage conditions, a method for controlling the driving current by turning the CMOS transistor at the output stage initially weakly on and then strongly turning on is used.

FIG. 1 illustrates a conventional CMOS output buffer circuit for controlling a driving current by turning on only some CMOS transistors among a plurality of CMOS transistors constituting an output stage when the power supply voltage is at a high voltage condition. Referring to FIG. 1, a conventional CMOS output buffer circuit is enabled through a NAND gate NA1 receiving an enable signal En and a data signal Data, and a data signal Data and an inverter IN1. PMOS transistor P1 and NMOS transistor N1 driven by an NOR gate NOR1 receiving a signal En as an input, and output signals of the NAND gate NA1 and NOR gate NOR1 to output an output signal. A PMOS transistor P2 and an NMOS transistor connected in parallel with the first CMOS transistor and driven by an output signal of the NAND gate NA1 and the NOR gate NOR1 to emit an output signal; A second CMOS transistor composed of N2), first and second transmission gates T1 and T2 and transistors P3 and N3 for controlling on / off of the second CMOS transistor in accordance with a sense signal sizecut. It is composed of

As described above, the conventional CMOS output buffer circuit uses an output signal of a power supply voltage detector (Vcc Level Detector) that detects the magnitude of the power supply voltage. When the power supply voltage is low, the power supply voltage detector (Vcc Level) is used. A detection signal sizecut, which is an output signal of a detector, is input in a low state, and the detection signal sizecut is input in a high state when the power supply voltage is high.

In the case where the enable signal En is applied in a high state, the NAND gate NA1 and the NOR gate NOR1 transfer the data signal Data to an output configured of a CMOS transistor.

At this time, when the power supply voltage is a low voltage condition, since the transfer gates T1 and T2 are turned on by the sense signal of the low state, the same signal is applied to all the CMOS transistors constituting the output terminal. The plurality of CMOS transistors are driven simultaneously. However, when the power supply voltage is high in a high voltage condition (sizecut = High), the transfer gates T1 and T2 are turned off by the sense signal in the high state, and the PMOS transistor receives the inverted sense signal sizecutb as an input. As the NMOS transistor N3, which receives P3 and the sense signal sizecut, is turned on, the CMOS transistors P2 and N2 of the output terminal connected to the drains of the turned-on transistors P3 and N3 are eventually turned on. It is turned off.

As described above, when the power supply voltage is a high voltage condition, only some CMOS transistors P1 and N1 are turned on among the plurality of CMOS transistors at the output stage, and some CMOS transistors P2 and N2 are turned off to drive current. Will be controlled.

Figure 2 shows a conventional CMOS output buffer circuit for controlling the drive current by gradually turning on the CMOS transistor at the output stage. Referring to FIG. 2, the enable signal En is received through the NAND gate NA1 receiving the enable signal En and the data signal Data, and the data signal Data and the inverter IN1. A first CMOS transistor composed of a PMOS transistor P1 and an NMOS transistor N1 driven by an NOR gate NOR1, an output signal of the NAND gate NA1 and the NOR gate NOR1, and outputting an output signal; A second CMOS transistor which is connected in parallel with the first CMOS transistor and is driven by an output signal of the NAND gate NA1 and a NOR gate NOR1 and composed of a PMOS transistor P2 and an NMOS transistor N2 for outputting an output signal; And a plurality of inverters IN2, IN3, IN4 and second NAND gates NA2 for delaying the output signal of the NAND gate NA1 to the second PMOS transistor P2, and the NOR gate NOR1. Delay the output signal It is composed of a plurality of inverters IN5, IN6, IN7 and a second NOR gate NOR2 for transferring to the 2 NMOS transistor N2.

When the enable signal En is applied in a high state, the first NAND gate NA1 and the first NOR gate NOR1 transfer the data signal Data to the first CMOS transistor. In this case, the output signals of the first NAND gate NA1 and the first NOR gate NOR1 may include the plurality of inverters IN2,..., IN7, the second NAND gate NA2, and the second NOR gate NOR2. Is transferred to the second PMOS transistor P2 and the second NMOS transistor N2 through a delay circuit composed of Therefore, after a certain time passes after the first PMOS transistor P1 or the first NMOS transistor N1 is turned on, the second PMOS transistor P2 or the second NMOS transistor N2 is turned on.

Such a CMOS output buffer circuit that gradually turns on the CMOS transistor at the output stage is necessary to reduce the output noise due to the peak value of the drive current at the beginning of the output transition.

However, a conventional CMOS output buffer circuit that turns on only some CMOS transistors and turns off some CMOS transistors among the plurality of CMOS transistors at the output stage as described above is required due to the difference in driving capability of the CMOS transistors at the output stage. There is a case where the magnitude of the driving current cannot be satisfied. For example, when the drive current must satisfy 2 mA, the range of the drive current of the PMOS transistor P1 in the previous stage is 1.3 mA to 1.6 mA, and the range of the drive current of the PMOS transistor P2 in the rear stage. Is 1.0 mA to 1.3 mA, if the power supply voltage is turned off under high voltage conditions, the PMOS transistor P2 in the rear stage may not be able to satisfy the required driving current of 2 mA. This may also be caused by various factors of the semiconductor circuit, such as temperature or electrostatic discharge (ESD).

In addition, if the unit width of the CMOS transistors in the output stage is too large, some CMOS transistors are turned on and some CMOS transistors are turned off, and the difference in driving capability is different compared to turning on all CMOS transistors. It becomes large, and precise control of a drive current is impossible.

In addition, as shown in FIG. 2, the output transistors may be reduced by the maximum value of the driving current at the initial stage of the output transition by gradually turning off the CMOS transistors at the output stage, but after the delay time has elapsed. All of the CMOS transistors are turned on so that the driving current is large.

SUMMARY OF THE INVENTION The present invention solves the problems of the prior art, and provides a CMOS output buffer circuit for controlling the driving current by weakly turning on the CMOS transistor of the output stage when the power supply voltage is a high voltage condition. There is a purpose.

In addition to the above, it is an object of the present invention to provide a progressively turn-on CMOS output buffer circuit which is useful for eliminating output noise by using a weakly turned-on CMOS transistor at the output stage.

1 is a CMOS output buffer circuit diagram for controlling a conventional driving current;

2 is a conventional CMOS output buffer circuit diagram for controlling drive current by gradually turning on a CMOS transistor at an output stage;

3 is a CMOS output buffer circuit diagram for controlling driving current by weakly turning on a CMOS transistor at an output stage according to an embodiment of the present invention;

4 is another CMOS output buffer circuit diagram for controlling driving current by weakly turning on a CMOS transistor of an output stage according to an embodiment of the present invention;

5 is a CMOS output buffer circuit diagram for controlling driving current by gradually turning on a CMOS transistor at an output stage using weak turn-on according to an embodiment of the present invention;

6A and 6B illustrate simulation results according to input signals in a CMOS output buffer circuit for controlling a conventional driving current.

7A and 7B show simulation results according to input signals in a CMOS output buffer circuit for controlling driving current by weakly turning on a CMOS transistor of an output stage of the present invention;

8A and 8B illustrate simulation results according to input signals in a CMOS output buffer circuit for controlling driving current by gradually turning on a CMOS transistor at an output stage using a weak turn-on of the present invention. .

(Name of the code for the main part of the drawing)

100: control unit 200: gradual turn-on means

10: input unit 20: PMOS transistor control unit

30: NMOS transistor control unit 40, 70: output unit

50: first gradual turn-on means 60: second gradual turn-on means

21, 31, 52, 54: NMOS transistor

22, 32, 51, 53: PMOS transistors 41, 42: CMOS transistors

P1, P3, P3: PMOS transistors N1, N2, N3: NMOS transistors

T1, T2: transfer gate NA1, NA2: NAND gate

NOR1, NOR2: NOR gate IN1, ..., IN7: Inverter

The CMOS output buffer circuit of the present invention for achieving the above object comprises: a first output unit comprising a first pull-up driver for supplying a power supply voltage to an output terminal and a first pull-down driver for supplying a ground voltage to the output terminal; A second output including a second pull-up driver for supplying a power voltage to the output terminal and a second pull-down driver for supplying a ground voltage to the output terminal, and receiving a data signal and an enable signal to receive the first pull-up driver. An input unit for generating a first input signal for controlling and a second input signal for controlling the first pull-down driver, receiving the first input signal, and transmitting the first input signal as a signal for controlling the second pull-up driver by a control signal, A control for receiving the second input signal and transmitting the second input signal as a signal for controlling the second pull-down driver by the control signal; And a NAND gate for receiving the inverted signal of the enable signal and the data signal to generate the first input signal, and the inverted signal of the data signal and the enable signal. And a NOR gate configured to receive and generate the second input signal. The pull-up drivers of the first and second output units are PMOS transistors, respectively, and the first and second output units are PMOS transistors. Each of the pull-down drivers may be an NMOS transistor. A first switching device configured to output the first input signal received from the input unit by the control signal as a signal for controlling a pull-up driver of the second output unit. And controlling the pull-down driver of the second output unit to receive the second input signal received from the input unit by the control signal. And a second switching element for outputting a signal. The first and second switching elements are respectively composed of PMOS and NMOS transistors. Another CMOS output buffer of the present invention for achieving the above object is characterized by the above-mentioned. The circuit includes an output configured by a pull-up driver for supplying a power supply voltage to an output terminal, a pull-down driver for supplying a ground voltage to the output terminal, and a first input signal for receiving a data signal and an enable signal to control the pull-up driver. And an input unit for generating a second input signal for controlling the pull-down driver, receiving the first input signal and transmitting the signal as a signal for controlling the pull-up driver by a control signal, and receiving and controlling the second input signal. And a control unit for transmitting the pull-down driver as a signal by a signal. The input unit receives the inverted signal of the enable signal and the data signal to generate the first input signal, and the inverted signal of the data signal and the enable signal to receive the first signal. The pull-up driver of the output unit is a PMOS transistor, and the pull-down driver of the output unit is an NMOS transistor. A first switching element configured to output the first input signal received from the input unit as a signal for controlling the pull-up driver of the output unit, and the second input signal received from the input unit by the control signal to the pull-down driver of the output unit. Comprising a second switching element for outputting as a controlling signal Is characterized in. The first and second switching elements is characterized in that it consists of respectively PMOS and NMOS transistors. The control signal may be a signal on the output terminal.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

3 illustrates a CMOS output buffer circuit for controlling drive current by weakly turning on a CMOS transistor at an output stage according to an embodiment of the present invention. Referring to FIG. 3, the present invention includes an input unit 10 which receives a data signal Data and an enable signal En and transmits an output signal to an output unit 40; A control unit (100) for receiving the output signal of the input unit (10) and weakly turning on the CMOS transistor in accordance with a sense signal (sizecut); And an output unit 40 in which a plurality of CMOS transistors 41, 42, ... are connected in parallel.

The input unit 10 is a NOR that receives an enable signal En through an NAND gate NA1 that receives an enable signal En and a data signal Data, a data signal Data, and an inverter IN1. The gate NOR1 is formed.

The controller 100 may weakly turn on the PMOS transistor of the output unit 40 according to the inverted sense signal sizecutb and the output unit 40 of the output unit 40 according to the sense signal sizecut. NMOS transistor controller 30 for weakly turning on the NMOS transistor.

The PMOS transistor control unit 20 includes a PMOS transistor 22 which is always turned on because the ground power is connected to the gate, and an NMOS transistor 21 in which an inverted signal of the sense signal sizecut is applied to the gate. The first transfer gate T1 is connected in parallel, and the output signal of the NAND gate NA1 of the input unit 10 is connected to the second PMOS transistor P2 of the output unit 40 through the first transfer gate T1. Is applied to the gate.

The NMOS transistor controller 30 is formed by connecting a NMOS transistor 31 which is always turned on because a power supply voltage Vcc is connected to a gate, and a PMOS transistor 32 in which a sense signal (sizecut) is applied to the gate in parallel. And a second transfer gate T2, through which the output signal of the NOR gate NOR1 of the input unit 10 passes through the second transfer gate T2 to the gate of the second NMOS transistor N2 of the output unit 40. Is approved.

The output unit 40 is connected to a plurality of CMOS transistors (41, 42, ...) consisting of PMOS transistors (P1, P2, ...) and NMOS transistors (N1, N2, ...) in parallel. .

In the plurality of CMOS transistors 41, 42,..., The first PMOS transistor P1 receives the output signal of the NAND gate NA1 of the input unit 10 as a gate, and the first NMOS transistor N1 The output signal of the NOR gate NOR1 of the input unit 10 is input to the gate. The second PMOS transistor P2 receives the output signal of the NAND gate NA1 of the input unit 10 through the first transfer gate T1, and the second NMOS transistor N2 of the input unit 10 receives the output signal. The output signal of the NOR gate NOR1 is input through the second transfer gate T2.

The operation of the CMOS output buffer circuit according to the embodiment of the present invention as described above is as follows.

When the enable signal En is in a low state, the output signal of the input unit 10 turns off the PMOS transistor P1 and the NMOS transistor N1 of the output unit 40, so that the normal output from the CMOS output buffer circuit is performed. No signal is generated.

When the enable signal En is in a high state, it is a case for outputting the data signal Data. The NAND gate NA1 and the NOR gate NOR1 of the input unit 10 invert the data signal Data, respectively. The output signal will be sent out.

In the output unit 40, the first CMOS transistor 41 including the first PMOS transistor P1 and the first NMOS transistor N1 inverts the output signal of the input unit 10 and the second PMOS transistor P2. The second CMOS transistor 42 including the second NMOS transistor N2 inverts the output signal of the first CMOS transistor 41.

In the PMOS transistor controller 20, the first transfer gate T1 transfers the output signal of the NAND gate NA1 of the input unit 10 to the gate of the second PMOS transistor P2 of the output unit 40. In this low low voltage condition, the inverted sense signal sizecutb is input in a high state so that the NMOS transistor 21 is turned on so that both the PMOS transistor 22 and the NMOS transistor 21 of the first transfer gate T1 are turned on. Is turned on. In this case, the signal is completely transferred to the second PMOS transistor P2 of the output unit 40 regardless of whether the signal input to the first transfer gate T1 is high or low.

However, in a high voltage condition where the power supply voltage is high, since the sense signal sizecut is high, the inverted sense signal sizecutb becomes low, and the NMOS transistor 21 is turned off.

As described above, when only the PMOS transistor 22 is turned on, when the signal input to the first transfer gate T1 is in a high state, the output unit is turned on by the PMOS transistor 22 that is turned on. Completely transferred to 40 turns off the second PMOS transistor P2 completely. This is because the PMOS transistor 22 as a pull-up transistor is always turned on to completely transmit a high state signal.

However, when the input signal of the first transfer gate T1 is in the low state, the turned-on PMOS transistor 22 does not completely transmit the low-state signal and has a threshold voltage (Vtp). The raised signal of is applied to the second PMOS transistor P2 of the output unit 40. Therefore, the second PMOS transistor P2 is weakly turned on, thereby reducing the magnitude of the driving current than when the second PMOS transistor P2 is completely turned on.

In the NMOS transistor controller 30, the second transfer gate T2 transfers the output signal of the NOR gate NOR1 of the input unit 10 to the gate of the second NMOS transistor N2 of the output unit 40. In this low low voltage condition, a sense signal (sizecut) is applied in a low state to turn on the PMOS transistor 32 so that both the PMOS transistor 32 and the NMOS transistor 31 of the second transfer gate T2 are turned on. do. At this time, the signal is completely transmitted to the second NMOS transistor N2 of the output unit 40 regardless of whether the signal input to the second transfer gate T2 is high or low.

On the other hand, in a high voltage condition where the power supply voltage is high, a sense signal (sizecut) is applied in a high state, and the PMOS transistor 32 is turned off. When only the NMOS transistor 31 is turned on as described above, the PMOS transistor 32 is turned off. The signal input to the second transfer gate T2 is completely transmitted to the output unit to turn off the second NMOS transistor N2. This is because the NMOS transistor 31 as a pull-down transistor is always turned on to completely transmit a low state signal.

However, when the input signal of the second transfer gate T2 is in the high state, the turned-on NMOS transistor 31 does not completely transmit the signal in the high state and is lowered by the threshold voltage Vtn. The signal is applied to the second NMOS transistor N2 of the output unit 40. Therefore, the second NMOS transistor N2 is weakly turned on, thereby reducing the magnitude of the driving current than when the second NMOS transistor N2 is completely turned on.

Simulation result of the output waveform according to the data enable signal En of the conventional CMOS output buffer circuit for controlling the driving current by turning on only some CMOS transistors among the plurality of CMOS transistors at the output stage Is shown in FIG. 6. In the CMOS output buffer circuit of the present invention for controlling the driving current by weakly turning on the CMOS transistor at the output terminal, a simulation result of the output waveform according to the data signal and the enable signal En is shown in FIG. 7. Shown.

FIG. 6A shows the voltage waveform over time of the CMOS output buffer circuit for controlling the conventional drive current when the sense signal (sizecut) is high, and FIG. 6B shows the waveform of the output current over time. will be. Referring to FIG. 6A, in the case of a CMOS output buffer circuit for controlling a conventional driving current, the second PMOS transistor P2 and the second NMOS transistor N2 of the output unit are turned off under a high voltage condition with a high power supply voltage. Shows that Referring to FIG. 6B, when the data signal Data is in a low state, the first NMOS transistor N1 is turned on so that a current 61 flows through a ground power supply, and the data signal Data is in a high state. In this case, the first PMOS transistor P1 is turned on so that the current 62 flows through the power supply voltage Vcc.

FIG. 7A shows the waveform of the output voltage over time of the CMOS output buffer circuit of the present invention for controlling the drive current by weakly turning on the CMOS transistor at the output stage in a high voltage condition with a high supply voltage, and FIG. The waveform of the output current over time is shown. Referring to FIG. 7A, when the sensing signal sizecut is high and the data signal Data is low, the signal of the high state is output from the input unit 10 and is input from the first transfer gate T1. The signal is completely transmitted to the output unit 40, but the signal 71 reduced by the threshold voltage Vtn of the NMOS transistor 31 in the second transfer gate T2 is the second NMOS transistor of the output unit 40. By passing to N2, the second NMOS transistor N2 is weakly turned on as a result.

When the sensing signal sizecut and the data signal Data are in a high state, a signal in a low state is output from the input unit 10, and an input signal is completely output from the second transfer gate T2. ), But a signal 72 increased by the threshold voltage Vtp of the PMOS transistor 22 is transmitted to the second PMOS transistor P2 of the output unit 40 in the first transfer gate T1. The second PMOS transistor P2 is weakly turned on.

Referring to FIG. 7B, in the CMOS output buffer circuit according to the present invention, the current flowing through the ground power supply when the second PMOS transistor P2 or the second NMOS transistor N2 of the output CMOS transistor is weakly turned on. It can be seen that the current 74 flowing through the 73 and the power supply voltage Vcc increases with a gentler slope than in the case of turning off some CMOS transistors in the conventional CMOS output buffer circuit.

As described above, it is possible to control the driving current more precisely than the output current by the output unit width of the CMOS transistor by weakly turning on the CMOS transistor at the output stage.

In the present invention, since the control of the driving current uses a weak turn-on of the CMOS transistor, the driving current can be controlled even if the first CMOS transistor 41 constituting the output unit 40 is removed in FIG. . 4 illustrates a CMOS output buffer circuit for controlling a driving current according to an embodiment of the present invention, in which the first CMOS transistor 41 of the output unit 40 is removed.

In addition, the present invention provides a circuit for eliminating output noise that may appear early in the output transition by weakly turning on the CMOS transistor at the beginning of the output transition and strongly turning on the CMOS transistor after a delay time. By using the method for controlling the driving current by weakly turning on the CMOS transistor of the output stage by the device, the number of elements constituting the circuit can be reduced and the output noise can be also reduced.

5 illustrates a CMOS output buffer circuit for controlling drive current by progressively turning on a CMOS transistor at an output stage using weak turn-on, in accordance with an embodiment of the present invention. Referring to FIG. 5, the present invention includes an input unit 10 which receives a data signal Data and an enable signal En and transmits an output signal to an output unit; Progressive turn-on means (200) for transferring the output signal of the input unit (10) to the CMOS transistor of the output unit; And an output unit 70 receiving the signal transmitted through the gradual turn-on means 200 and generating an output signal.

The input unit 10 is a NOR that receives an enable signal En through an NAND gate NA1 that receives an enable signal En and a data signal Data, a data signal Data, and an inverter IN1. The gate NOR1 is formed.

The gradual turn-on means 200 is a first gradual turn-on means 50 for gradually turning on the PMOS transistor P1 of the output part 70 and the NMOS transistor N1 of the output part 70. ) Is the second gradual turn-on means 60 for gradually turning on.

The first gradual turn-on means 50 has a PMOS transistor 51 and an NMOS transistor 52 connected in parallel to output an output signal of the NAND gate NA1 of the input unit 10 to the PMOS transistor of the output unit 70. It consists of a transfer gate T3 which transfers to the gate of P1. The gate of the PMOS transistor 51 is connected to a ground power source and is always turned on.

In the second gradual turn-on means, the PMOS transistor 53 and the NMOS transistor 54 are connected in parallel to output an output signal of the NOR gate NOR1 of the input unit 10 to the NMOS transistor N1 of the output unit 70. It consists of a transfer gate T4 which transfers to the gate of which the gate of the NMOS transistor 54 is connected to the power supply voltage and is always turned on.

In addition, the NMOS transistor 52 of the first gradual turn-on means 50 and the PMOS transistor 53 of the second gradual turn-on means 60 have gates connected to each other so that the CMOS transistor of the output unit 70 can be connected. It is connected to the output terminal. In the above configuration, the sensing signal sizecut and the inverted sensing signal sizecutb applied to the PMOS transistor controller 20 and the NMOS transistor controller 30 shown in FIG. 3 are replaced with the output signal D_out of the output unit. Form.

The output unit 70 includes a CMOS transistor in which a PMOS transistor P1 and an NMOS transistor N1 are connected in series. The third transfer is performed to a gate of the PMOS transistor P1 having a power supply voltage Vcc connected to a source. The signal transmitted through the gate T3 is applied, and the signal transmitted through the fourth transfer gate T4 is applied to the gate of the NMOS transistor N1 having a ground power source connected to the source.

In order to examine the operation of the CMOS output buffer circuit for controlling the driving current by gradually turning on the CMOS transistor of the output stage using the weak turn-on as described above, the NMOS transistor N1 of the output unit 70 is A case in which the output signal D_out of the output unit 70 transitions from a high state to a low state by being turned on will be described.

In order for the output signal D_out of the output unit 70 to transition from the high state to the low state, the enable signal En should be applied in the high state and the data signal Data should be applied in the low state. At this time, a high state signal is output from the NOR gate NOR1 and the NAND gate NA1 of the input unit 10 and applied to the progressive turn-on means 200.

First, referring to the operation of the second gradual turn-on means 60, since the PMOS transistor 53 of the fourth transfer gate T4 is initially turned off by the output signal D_out which is initially in a high state, The high state signal input to the fourth transfer gate T4 is reduced by the threshold voltage Vtn of the NMOS transistor 54 and transferred to the gate of the NMOS transistor N1 of the output unit 70. The NMOS transistor N1 is weakly turned on by the signal.

Accordingly, the output signal D_out of the output unit 70 starts to fall, and the output signal D_out turns on the PMOS transistor 53 of the fourth transfer gate T4 connected to the output signal D_out. When the voltage is lowered to a state capable of being turned on, the PMOS transistor 53 is turned on. As a result, when both the PMOS transistor 53 and the NMOS transistor 54 of the fourth transfer gate T4 are turned on, a signal increased in a high state is applied to the NMOS transistor N1 of the output unit 70 so that the NMOS Transistor N1 is completely turned on.

As described above, when the NMOS transistor N1 of the output unit 70 is gradually turned on, the NMOS transistor 52 of the third transfer gate T3 is initially in the high state output signal D_out. Since the PMOS transistor 51 and the NMOS transistor 52 of the third transfer gate T3 are turned on, the high-state signal input to the third transfer gate T3 is turned on. Since it is completely delivered to the PMOS transistor P1 of the output unit 70, the PMOS transistor P1 remains turned off.

In order to transition the output signal D_out from the low state to the high state, the enable signal En and the data signal Data are both applied in the high state as opposed to the above case. At this time, a low state signal is output from the NOR gate NOR1 and the NAND gate NA1 of the input unit 10 and applied to the gradual turn-on means 200. Since the NMOS transistor 52 of the third transfer gate T3 is initially turned off by the output signal D_out in the low state, the low state signal input to the third transfer gate T3 is turned off. The threshold voltage Vtp of the turned-on PMOS transistor 51 is increased to be transferred to the PMOS transistor P1 of the output unit 70 and the PMOS transistor P1 is weakly turned on.

Therefore, when the output signal D_out of the output unit 70 starts to rise, the output signal D_out rises to a state capable of turning on the NMOS transistor 52 of the third transfer gate T3. The NMOS transistor 52 is turned on and the low-state signal input to the third transfer gate T3 is completely transferred to the PMOS transistor P1 of the output unit 70 so that the PMOS transistor P1 is provided. Is turned on completely.

As described above, when the PMOS transistor P1 of the output unit 70 is gradually turned on, the PMOS transistor 53 of the fourth transfer gate T4 is initially in the low state output signal D_out. Since the signal is turned on, the low state signal input to the fourth transfer gate T4 is completely transmitted to the NMOS transistor N1 of the output unit 70, and the NMOS transistor is transmitted by the transmitted signal. N1 remains turned off.

8 is an output according to a data signal and an enable signal En of a CMOS output buffer circuit for controlling driving current by gradually turning on a CMOS transistor at an output stage using a weak turn-on of the present invention. The simulation result of the waveform is shown.

FIG. 8A shows the output voltage of each node according to the change of the data signal Data, and FIG. 8B shows the current 83 flowing through the ground power supply and the current 84 flowing through the power supply voltage Vcc in this case. ) Is shown.

Referring to FIG. 8A, when the PMOS transistor 53 of the fourth transfer gate T4 is turned off by the output signal D_out in the high state, the enable signal En is applied to the high state. When the data signal Data is applied in the low state, a high state signal is applied to the fourth transfer gate T4, and the high state signal is reduced by the threshold voltage Vtn of the NMOS transistor 54. Since the NMOS transistor N1 is transferred to the NMOS transistor N1 of the output unit 70, it can be seen that the NMOS transistor N1 is weakly turned on 82. In this case, it can be seen that the drive current 83 flowing through the ground power supply does not initially exhibit the highest value, but the drive current decreases 85 while the NMOS transistor N1 is weakly turned on.

When the output signal D_out is initially in the low state and the NMOS transistor 52 of the third transfer gate T3 is turned off, the enable signal En and the data signal Data are in a high state. When applied, a signal having a low state is applied to the third transfer gate T3. The low state signal is increased by the threshold voltage Vtp of the PMOS transistor 51, so that the PMOS transistor P1 of the output unit 70 is applied. The PMOS transistor P1 is weakly turned on 81 because it is transferred to. In this case, it can be seen that the driving current 84 flowing through the power supply does not initially exhibit the highest value, but the driving current decreases 86 while the PMOS transistor P1 is weakly turned on.

As described in detail above, according to the CMOS output buffer circuit for controlling the driving current of the present invention, in the case of a high voltage condition in which the power supply voltage is high, the driving current is weakly turned on without turning off the CMOS transistor of the output stage. Can be precisely controlled.

Further, according to the CMOS output buffer circuit of the present invention for controlling the drive current by gradually turning on the CMOS transistor of the output stage, the CMOS transistor of the output portion is weakly turned on and completely turned on after a certain time. By not outputting the initial value of the drive current to the maximum value, output noise can be eliminated, and the circuit configuration can be further simplified.

Hereinafter, this invention can be implemented in various changes in the range which does not deviate from the summary.

Claims (11)

In the CMOS output buffer circuit, A first output unit comprising a first pull-up driver for supplying a power voltage to an output terminal and a first pull-down driver for supplying a ground voltage to the output terminal; A second output unit including a second pull-up driver for supplying a power voltage to the output terminal and a second pull-down driver for supplying a ground voltage to the output terminal; An input unit receiving a data signal and an enable signal to generate a first input signal for controlling the first pull-up driver and a second input signal for controlling the first pull-down driver; Receiving the first input signal and transmitting the signal as a signal for controlling the second pull-up driver by a control signal, and receiving the second input signal as a signal for controlling the second pull-down driver by the control signal CMOS output buffer circuit comprising a control unit. The method of claim 1, wherein the input unit A NAND gate receiving the inverted signal of the enable signal and the data signal to generate the first input signal; And a NOR gate configured to receive the inverted signal of the data signal and the enable signal to generate the second input signal. The method of claim 1, Pull-up drivers of the first and second output units are PMOS transistors, respectively. And the pull down drivers of the first and second output units are NMOS transistors, respectively. The method of claim 1, A first switching element configured to output the first input signal received from the input unit by the control signal as a signal for controlling a pull-up driver of the second output unit; And a second switching element configured to output the second input signal received from the input unit by the control signal as a signal for controlling a pull-down driver of the second output unit. The method of claim 4, wherein And the first and second switching elements are transfer gates each consisting of a PMOS and an NMOS transistor. In the CMOS output buffer circuit, An output unit comprising a pull-up driver for supplying a power voltage to an output terminal and a pull-down driver for supplying a ground voltage to the output terminal; An input unit receiving a data signal and an enable signal to generate a first input signal for controlling the pull-up driver and a second input signal for controlling the pull-down driver; And a control unit for receiving the first input signal and transmitting the signal as a signal for controlling the pull-up driver by a control signal, and receiving the second input signal as a signal for controlling the pull-down driver by the control signal. CMOS output buffer circuit, characterized in that. The method of claim 8, wherein the input unit A NAND gate receiving the inverted signal of the enable signal and the data signal to generate the first input signal; And a NOR gate configured to receive the inverted signal of the data signal and the enable signal to generate the second input signal. The method of claim 8, The pull-up driver of the output unit is a PMOS transistor, And a pull-down driver of the output unit is an NMOS transistor. The method of claim 8, wherein the control unit, A first switching element configured to output the first input signal received from the input unit by the control signal as a signal for controlling a pull-up driver of the output unit; And a second switching element configured to output the second input signal received from the input unit by the control signal as a signal for controlling a pull-down driver of the output unit. The method of claim 11, And the first and second switching elements are transfer gates each consisting of a PMOS and an NMOS transistor. The method of claim 8, And said control signal is a signal of said output terminal.