CN116232311B - Input circuit of single bus communication chip and chip - Google Patents
Input circuit of single bus communication chip and chip Download PDFInfo
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- CN116232311B CN116232311B CN202310508836.1A CN202310508836A CN116232311B CN 116232311 B CN116232311 B CN 116232311B CN 202310508836 A CN202310508836 A CN 202310508836A CN 116232311 B CN116232311 B CN 116232311B
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0175—Coupling arrangements; Interface arrangements
- H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0021—Modifications of threshold
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
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Abstract
The application relates to the technical field of integrated circuits and discloses an input circuit of a single-bus communication chip and a chip thereof; the input circuit includes: a hysteresis comparator; in the hysteresis comparator: the grid electrode of the first transistor is used for inputting a first voltage; the drain electrode of the first transistor is connected with the first end of the selection path; the grid electrode of the second transistor is used for inputting a reference voltage; the drain electrode of the second transistor is connected with the second end of the selection path; the second end of the selection path is connected with a voltage sampling circuit; the voltage sampling circuit is used for outputting a high level when the first voltage is larger than the upper threshold voltage; outputting a low level when the first voltage is less than the lower threshold voltage; the upper threshold voltage and the lower threshold voltage are obtained according to the reference voltage and the width-to-length ratio of the first transistor, the second transistor and the transistor in the selection path; the received high and low levels can be accurately identified, normal communication of the single-bus communication chip is ensured, and the application scene of the single-bus communication chip is widened.
Description
Technical Field
The application relates to the technical field of integrated circuits, in particular to an input circuit of a single-bus communication chip and the chip.
Background
The single bus communication is a half duplex communication mode, and because the single signal line is used for power supply and communication, the single bus communication has the advantages of saving chip Input and Output (IO) resources, along with simple structure, low cost, convenient expansion and maintenance and the like, and is widely applied to communication scenes.
In order to improve the communication speed, the conventional scheme uses the IO pin of a single-bus communication chip exclusively for communication, and the chip needs a separate power supply to supply power to the IO pin. Under this scheme, the master chip and slave chip output high is typically achieved by a resistive pull-up to a pull-up supply voltage.
However, in the application of the scheme, a scene that the power supply voltage of the pull-up power supply voltage is greatly different from the power supply voltage of the slave chip exists; at this time, the minimum value of the input high-level voltage is always higher than the pull-up power supply voltage, so that the slave chip cannot correctly identify the high level sent by the master chip, and single bus communication failure is caused.
Disclosure of Invention
In view of the above, the present application provides an input circuit and a chip of a single-bus communication chip, which can accurately identify a high level and a low level sent from a main chip by a slave chip, and ensure the reliability and stability of single-bus communication.
In order to solve the problems, the technical scheme provided by the application is as follows:
the first aspect of the present application provides an input circuit of a single bus communication chip, comprising: a hysteresis comparator;
the hysteresis comparator includes: a first transistor, a second transistor, a selection path, and a voltage sampling circuit; the selection path includes a plurality of transistors;
the grid electrode of the first transistor is used for inputting a first voltage; the drain electrode of the first transistor is connected with the first end of the selection path;
the grid electrode of the second transistor is used for inputting a reference voltage; the drain electrode of the second transistor is connected with the second end of the selection path;
the source electrode of the first transistor and the source electrode of the second transistor are grounded;
the second end of the selection path is connected with a voltage sampling circuit; the third end of the selection path is used for connecting with a power supply;
the voltage sampling circuit is used for outputting a high level when the first voltage is larger than the upper threshold voltage; outputting a low level when the first voltage is less than the lower threshold voltage;
the upper threshold voltage and the lower threshold voltage are obtained based on the reference voltage and the aspect ratio of the first transistor, the second transistor, and the transistors in the select path.
Preferably, the selection path includes: a third transistor, a fourth transistor, a fifth transistor, and a sixth transistor;
the source electrode of the third transistor is a first end of the selection path; a grid electrode of the third transistor is connected with a grid electrode of the fourth transistor;
the source electrode of the fourth transistor is a second end of the selection path;
a gate of the fifth transistor is connected with a gate of the sixth transistor; a source electrode of the fifth transistor is connected with a source electrode of the third transistor; the source electrode of the sixth transistor is connected with the source electrode of the fourth transistor;
the drains of the third transistor, the fourth transistor, the fifth transistor and the sixth transistor are all connected together and are the third end of the selection path.
Preferably, the voltage sampling circuit includes: a seventh transistor and an inverter;
the drain electrode of the seventh transistor is used for connecting with a power supply; a gate of the seventh transistor is connected with the second end of the selection path; the source of the seventh transistor is connected to the input terminal of the inverter.
Preferably, the voltage sampling circuit further includes: an eighth transistor, a ninth transistor, and a tenth transistor;
the drain electrode of the eighth transistor is connected with the source electrode of the seventh transistor; a gate of the eighth transistor is connected with a gate of the tenth transistor;
a gate of the ninth transistor is connected to the first end of the selection path; a source of the ninth transistor is connected with a drain of the tenth transistor;
the drain electrode of the tenth transistor is connected with the grid electrode of the tenth transistor;
the drain electrode of the ninth transistor is used for connecting a power supply; sources of the eighth transistor and the tenth transistor are grounded.
Preferably, the hysteresis comparator further comprises: a bias current module;
the bias current module includes: an eleventh transistor and a current source;
the input end of the current source is used for connecting with a power supply; the output end of the current source is used for connecting the grid electrode of the eleventh transistor;
the source of the first transistor and the source of the second transistor are grounded through the drain-source of the eleventh transistor.
Preferably, the method further comprises: an electrostatic discharge (ESD) circuit;
the ESD circuit is connected with the input end of the hysteresis comparator; the input end of the hysteresis comparator is the grid electrode of the first transistor.
Preferably, the method further comprises: a pull-up control circuit and a pull-down control circuit;
the pull-up control circuit and the pull-down control circuit are connected between the ESD circuit and the hysteresis comparator.
Preferably, the method further comprises: a first output buffer and a second output buffer;
the first output buffer and the second output buffer are connected to the output end of the hysteresis comparator;
the first output buffer is used for waveform shaping of the output signal of the hysteresis comparator;
the second output buffer is used for converting the output signal to a low-voltage power domain.
Preferably, the method further comprises: schmitt circuit and selector;
the Schmitt circuit is connected with the hysteresis comparator in parallel;
the output end of the Schmitt circuit is connected with the comparator;
a selector for switching an input mode of the input circuit; the input modes include a schmitt input mode and a hysteretic comparator input mode.
Preferably, the first transistor and the second transistor are both NMOS transistors.
Preferably, the third transistor, the fourth transistor, the fifth transistor and the sixth transistor are PMOS transistors.
A second aspect of the present application provides a single-bus communication chip comprising a transmission circuit, a processing circuit and an input circuit of the single-bus communication chip described above;
the first end of the transmitting circuit is used as an input/output pin of the chip; the second end of the transmitting circuit is used for grounding;
the first end of the input circuit is connected with the first end of the transmitting circuit; the second end of the input circuit is connected with the processing circuit.
From this, the application has the following beneficial effects:
the application provides an input circuit of a single bus communication chip, comprising: a hysteresis comparator; the hysteresis comparator includes: a first transistor, a second transistor, a selection path, and a voltage sampling circuit; the selection path includes a plurality of transistors; the grid electrode of the first transistor is used for inputting a first voltage; the drain electrode of the first transistor is connected with the first end of the selection path; the grid electrode of the second transistor is used for inputting a reference voltage; the drain electrode of the second transistor is connected with the second end of the selection path; the source electrode of the first transistor and the source electrode of the second transistor are grounded; the second end of the selection path is connected with a voltage sampling circuit; the third end of the selection path is used for connecting with a power supply; the voltage sampling circuit is used for outputting a high level when the first voltage is larger than the upper threshold voltage; outputting a low level when the first voltage is less than the lower threshold voltage; the upper threshold voltage and the lower threshold voltage are obtained based on the reference voltage and the aspect ratio of the first transistor, the second transistor, and the transistors in the select path. The input circuit of the single-bus communication chip provided by the application converts the upper threshold voltage and the lower threshold voltage into physical quantities irrelevant to a chip power supply, and can accurately identify the received high and low level functions by setting proper reference voltage and selecting a transistor with proper width-to-length ratio, thereby ensuring normal communication of the single-bus communication chip, avoiding the limitation of the voltage of the chip power supply and widening the application scene of the single-bus communication chip.
Drawings
FIG. 1 is a schematic diagram of a single bus communication system;
fig. 2 is a schematic diagram of an input circuit of a single bus communication chip according to an embodiment of the present application;
FIG. 3 is a schematic diagram of a hysteresis comparator according to an embodiment of the present application;
FIG. 4 is a schematic diagram of an input circuit of another single-bus communication chip according to an embodiment of the present application;
fig. 5 is a waveform diagram of signal effect of an input circuit of a single bus communication chip according to an embodiment of the present application;
FIG. 6 is a schematic diagram of an input circuit of a single-bus communication chip according to an embodiment of the present application;
fig. 7 is a schematic diagram of a single bus communication chip according to an embodiment of the present application.
Detailed Description
In order to enable those skilled in the art to better understand and implement the technical solution of the present application, the following describes a specific application scenario of the present application.
Referring to fig. 1, a schematic diagram of a single bus communication system is shown.
The single bus communication system includes: a master chip a and a slave chip B.
The master chip a and the slave chip B communicate through a Single-Wire Interface (SWI).
Vpup is the master chip supply, VCC is the slave chip supply, and the single bus is connected to Vpup through a pull-up resistor Rpup.
For convenience of description, the single bus communication system shown in fig. 1 uses a chip for transmitting signals as a master chip, and a chip for receiving signals as a slave chip.
The master chip a is similar to the slave chip B in specific structure, and includes a transmitting module Tx and a receiving module Rx. The transmitting module Tx and the receiving module Rx of both chips are connected to SWI through IO pins.
It should be understood that the slave chip B should further include a processing circuit of a subsequent stage of the receiving module Rx, which is not shown in fig. 1 for convenience of explanation.
Specifically, the transmitting module Tx includes an NMOS tube, and a source of the NMOS tube is grounded; the NMOS transistors are specifically NMOSA and NMOSB corresponding to the master chip a and the slave chip B. The receiving module Rx includes an input circuit.
When the main chip A sends a low level, NMOSA is conducted; assuming that the on-resistance of NMOSA is Ron, the bus potential is pulled down to Vpup Ron/(ron+rpup), and the input circuit 1000 of the chip B recognizes that the bus is low.
When the main chip a sends a high level, the NMOSA turns off; the bus potential is pulled up to Vpup gradually, at which point the bus is recognized as high from the input circuit of chip B.
Input circuits of the prior art are often implemented using schmitt circuits of six-tube construction. The schmitt circuit shapes the input signal to the IO pin and obtains the appropriate input high level voltage VIH and input low level voltage VIL.
Wherein VIH is defined as a signal higher than the voltage value is recognized as a high level through the input IO, and VIL is defined as a signal lower than the voltage value is recognized as a low level through the input IO.
However, the inventors found that in the case of using the schmitt circuit, the input high-level voltage VIH and the input low-level voltage VIL are 0.7 VCC and 0.3 VCC, respectively, and are closely related to the power supply voltage VCC from the chip B. When the power supply voltage Vpup of the master chip a is smaller than the power supply voltage VCC of the slave chip B, and when the voltage difference is large to a certain extent, the slave chip cannot correctly recognize the high and low levels output by the master chip, thereby causing a single bus communication failure.
For example: the power supply voltage vpup=1.8v of the master chip a, the slave chip B is supplied with power from a lithium battery, and the power supply voltage vcc=4.2V. In this scenario, the input high level vih=0.7vcc=2.94V from chip B. The high level which can be sent by the main chip A is only 1.8V and is always lower than the input high level VIH; slave chip B will recognize a low level. The slave chip B cannot correctly identify the high level sent by the master chip A, so that single bus communication fails, and various applications of the chip are limited.
The embodiments of the present application will be described in detail below with reference to the accompanying drawings and detailed description.
Referring to fig. 2, a schematic diagram of an input circuit of a single bus communication chip according to an embodiment of the present application is shown.
The input circuit of the single bus communication chip provided by the embodiment of the application comprises: hysteresis comparator.
The hysteresis comparator includes: the first transistor TR1, the second transistor TR2, the selection path 100, and the voltage sampling circuit 200.
Wherein the selection path 100 includes a plurality of transistors.
The gate of the first transistor TR1 is used for inputting a first voltage vin+; the drain of the first transistor TR1 is connected to the first end of the selection path 100.
The gate of the second transistor TR2 is used to input a reference voltage VREF; the drain of the second transistor TR2 is connected to the second terminal of the selection path 100.
The application does not limit the value and implementation of the reference voltage VREF. The value of the reference voltage VREF can be specifically set by those skilled in the art according to the chip communication requirements. The reference voltage VREF may be obtained by dividing a voltage by a resistor by the power supply VCC.
The source of the first transistor TR1 and the source of the second transistor TR2 are both grounded GND.
A second end of the selection path 100 is connected with the voltage sampling circuit 200; a third terminal of the selection path 100 is used for connecting to the power supply VCC.
A voltage sampling circuit 100 for outputting a high level when the first voltage vin+ is greater than the upper threshold voltage vt+; when the first voltage is smaller than the lower threshold voltage Vt-, a low level is output.
The upper threshold voltage vt+ and the lower threshold voltage Vt-are obtained based on the reference voltage VREF and the width-to-length ratios of the first transistor TR1, the second transistor TR2, and the transistors in the selection path 100.
Since the upper threshold voltage Vt+ and the lower threshold voltage Vt-are obtained based on the reference voltage VREF and the aspect ratio of the transistors; therefore, the upper threshold voltage and the lower threshold voltage are irrelevant to the power supply voltage VCC of the single-bus communication chip, and the situation that the power supply voltage of the master chip and the power supply voltage of the slave chip are too different to each other is avoided, so that the slave chip cannot accurately recognize the high level sent by the master chip; the single-bus communication chip can accurately identify the high and low levels of the input signals, and the application scene of the single-bus communication chip is expanded.
The input circuit of the single bus communication chip provided by the embodiment of the application comprises: a hysteresis comparator; the hysteresis comparator includes: a first transistor, a second transistor, a selection path, and a voltage sampling circuit; the selection path includes a plurality of transistors; the grid electrode of the first transistor is used for inputting a first voltage; the drain electrode of the first transistor is connected with the first end of the selection path; the grid electrode of the second transistor is used for inputting a reference voltage; the drain electrode of the second transistor is connected with the second end of the selection path; the source electrode of the first transistor and the source electrode of the second transistor are grounded; the second end of the selection path is connected with a voltage sampling circuit; the third end of the selection path is used for connecting with a power supply; the voltage sampling circuit is used for outputting a high level when the first voltage is larger than the upper threshold voltage; outputting a low level when the first voltage is less than the lower threshold voltage; the upper threshold voltage and the lower threshold voltage are obtained based on the reference voltage and the aspect ratio of the first transistor, the second transistor, and the transistors in the select path. The input circuit of the single-bus communication chip provided by the embodiment of the application converts the upper threshold voltage and the lower threshold voltage into physical quantities irrelevant to a chip power supply, and can realize the function of accurately identifying the received high and low levels by setting the proper reference voltage and selecting the transistor with proper width-to-length ratio, thereby ensuring the normal communication of the single-bus communication chip and widening the application scene of the single-bus communication chip.
One possible alternative path and specific implementation of the voltage sampling circuit is described below in conjunction with the accompanying drawings.
Referring to fig. 3, a schematic diagram of a hysteresis comparator according to an embodiment of the present application is shown.
As in the above embodiment, the hysteresis comparator 1000 provided in this embodiment also includes: the first transistor TR1, the second transistor TR2, the selection path 100, and the voltage sampling circuit 200. The connection mode can be seen in the above embodiments.
In this embodiment, the first transistor TR1 and the second transistor TR2 are NMOS transistors.
Specifically, the selection path 100 includes: the third transistor TR3, the fourth transistor TR4, the fifth transistor TR5, and the sixth transistor TR6.
In this embodiment, the transistors in the selection path 100 are PMOS transistors. It should be appreciated that in other possible implementations, the third transistor, the fourth transistor, the fifth transistor and the sixth transistor may also be other types of transistors, for example: insulated gate bipolar transistors.
The source of the third transistor TR3 is the first end of the selection path 100, and the gate of the third transistor TR3 is connected to the gate of the fourth transistor TR 4.
The source of the fourth transistor TR4 is the second terminal of the selection path 100.
A gate of the fifth transistor TR5 is connected to a gate of the sixth transistor TR 6; the source of the fifth transistor TR5 is connected to the source of the third transistor TR 3; the source of the sixth transistor TR6 is connected to the source of the fourth transistor TR 4.
The drains of the third transistor TR3, the fourth transistor TR4, the fifth transistor TR5 and the sixth transistor TR6 are all connected together as a third terminal of the selection path 100 for connection to the power supply VCC.
Specifically, the voltage sampling circuit 200 includes: the seventh transistor TR7, the eighth transistor TR8, the ninth transistor TR9, the tenth transistor TR10, and the inverter INV.
The drain of the seventh transistor TR7 is for connection to a power supply VCC; the gate of the seventh transistor TR7 is connected to the second terminal of the selection path 100; the source of the seventh transistor TR7 is connected to the input terminal of the inverter INV.
It should be appreciated that the voltage sampling circuit 200 includes only the seventh transistor TR7 and the inverter INV, and thus the sampling and outputting of the second terminal of the selection path 100 can be completed.
In this embodiment, the eighth transistor TR8 is to avoid the direct grounding when the seventh transistor TR7 is turned on, and damage the seventh transistor. The ninth transistor TR9 and the tenth transistor TR10 can control the turn-on condition of the eighth transistor TR8, and the ninth transistor TR9 and the tenth transistor TR10 and the seventh transistor TR7 and the eighth transistor TR8 are symmetrically designed.
The drain of the eighth transistor TR8 is connected to the source of the seventh transistor TR 7; the gate of the eighth transistor TR8 is connected to the gate of the tenth transistor TR 10.
A gate of the ninth transistor TR9 is connected to the first end of the selection path 100; the source of the ninth transistor TR9 is connected to the drain of the tenth transistor TR 10.
The drain of the tenth transistor TR10 is connected to the gate of the tenth transistor TR 10.
The drain of the ninth transistor TR9 is for connection to a power supply VCC; the sources of the eighth transistor TR8 and the tenth transistor TR10 are grounded GND.
In addition to the above, the hysteresis comparator provided in this embodiment further includes: a bias current module; the bias current module includes: the eleventh transistor TR11, the twelfth transistor TR12, and the current source IBIAS.
The input end of the current source IBIAS is used for connecting the power VCC; an output terminal of the current source IBIAS is connected to a gate of the eleventh transistor TR 11.
The source of the first transistor TR1 and the source of the second transistor TR2 are grounded through the drain-source of the eleventh transistor TR 11.
The drain of the twelfth transistor TR12 is connected to the output of the current source IBIAS; the drain of the twelfth transistor TR12 is also connected to the gate of the twelfth transistor TR 12; the source of the twelfth transistor TR12 is grounded GND.
The bias current module is used for enabling the hysteresis comparator to work stably and maintaining the upper threshold voltage and the lower threshold voltage of the hysteresis comparator. The bias current module can also eliminate noise and improve dynamic range and stability.
In this embodiment, the first transistor TR1, the second transistor TR2, the eighth transistor TR8, the tenth transistor TR10, the eleventh transistor TR11, and the twelfth transistor TR12 each employ an NMOS transistor; other transistors are PMOS transistors; has the advantage of smaller power consumption.
Under the above-mentioned composition and connection modes of the selection path, the voltage sampling circuit and the bias current module, the relationship between the first voltage vin+ input by the hysteresis comparator and the output signal is as follows:
when the input first voltage vin+ is 0V, the first transistor TR1 is turned off; the second transistor TR2 is turned on due to the input of VREF; at this time, the fifth transistor TR5 and the sixth transistor TR6 will be turned on, and the third transistor TR3 and the fourth transistor TR4 will be turned off. The current i flowing through the eleventh transistor TR11 is all contributed by the sixth transistor TR6 and the second transistor TR 2. At this time, the drain of the second transistor TR2 is at a high level, so the seventh transistor TR7 is turned on, and the input terminal of the inverter INV is at a high level; then a low level is output after being processed by the inverter INV. Obviously, the first voltage vin+ is now smaller than the upper threshold voltage vt+.
When the first voltage vin+ is continuously increased to the upper threshold voltage vt+, the first transistor TR1 is gradually turned on, and a part of the current i flowing through the eleventh transistor TR11 starts to flow from the first transistor TR1, this phenomenon continues until the current flowing through the first transistor TR1 is equal to the current flowing through the fifth transistor TR5, and at this time, the first voltage vin+ reaches the upper threshold voltage vt+. In this process, the drain of the second transistor TR2 is still at a high level, and the seventh transistor TR7 is turned on, so the voltage sampling circuit 200 still outputs a low level.
When the first voltage vin+ increases to be greater than the upper threshold voltage vt+, the hysteresis comparator changes state, and thus the third transistor TR3 and the fourth transistor TR4 are turned on, and most of the current will flow through the first transistor TR1 and the third transistor TR3. The fifth transistor TR5, the sixth transistor TR6, and the second transistor TR2 are turned off. Therefore, the drain of the second transistor TR2 is low, the seventh transistor TR7 is turned off, and the input terminal of the inverter INV is low; the high level is outputted after the processing by the inverter INV.
The following equations can be listed by the procedure described above:
the upper threshold voltage Vt+ can be derived from the above formula:
wherein, the liquid crystal display device comprises a liquid crystal display device,a gate-source voltage of the transistor; />Is the off-voltage of the transistor; />Is the transconductance parameter of the transistor; />Is the aspect ratio of the transistor.
The falling condition of the first voltage vin+ is similar to the above process, and as the first voltage vin+ is reduced to the lower threshold voltage Vt-, the on/off condition of each transistor in the selection path 100 is changed, so that the input signal sampled by the voltage sampling circuit is changed in high/low level, and the output signal is different.
The same applies to the lower threshold voltage Vt-:
with the structure of the hysteresis comparator, the input circuit of the single-bus communication chip can accurately identify the high level and the low level of the input signal through the upper threshold voltage and the lower threshold voltage. The upper threshold voltage and the lower threshold voltage are determined by the width-to-length ratio of the reference voltage value and the transistor; the reference voltage value is independently input and is independent of the voltage required by an application scene and the like; the width-to-length ratio of the transistor is determined by the characteristics of the transistor and is irrelevant to different scenes; therefore, the input circuit of the single-bus communication chip provided by the embodiment can accurately identify the received high and low levels, ensures normal communication of the single-bus communication chip, is not limited by the power supply voltage of the chip, and widens the application scene of the single-bus communication chip.
Referring to fig. 4, a schematic diagram of an input circuit of another single bus communication chip according to an embodiment of the present application is shown.
The input circuit of the single-bus communication chip provided in the embodiment of the present application includes, in addition to the hysteresis comparator 1000 described in the above embodiment: an Electro-Static Discharge (ESD) circuit 2000, a pull-up control circuit 3000, a pull-down control circuit 4000, a first output buffer 5000, and a second output buffer 6000.
The ESD circuit 2000 is connected to the input of the hysteresis comparator 1000; the input of the hysteresis comparator 1000 is the gate of the first transistor TR1 in the above embodiment.
The ESD circuit 2000 can provide a discharging path for the ESD current when the ESD phenomenon occurs in the input circuit, so as to prevent the ESD current from entering the input circuit and the processing circuit at the subsequent stage to cause device damage.
The pull-up control circuit 3000 and the pull-down control circuit 4000 are connected between the ESD circuit 2000 and the hysteresis comparator 1000.
The pull-up control circuit 3000 and the pull-down control circuit 4000 can reduce malfunction caused when signals are unstable, for example, when power is on; and can improve the driving capability of the pins.
The input signal is input to the hysteresis comparator 1000 through vin+; the reference voltage VREF passes through Vin-input hysteresis comparator 1000.
The first output buffer 5000 and the second output buffer 6000 are connected to the output terminal of the hysteresis comparator 1000.
The first output buffer 5000 is used for waveform shaping the output signal of the hysteresis comparator.
The second output buffer 6000 is used to convert the output signal to a low voltage power domain.
Referring to fig. 5, the signal effect waveform diagram of the input circuit of the single bus communication chip according to the embodiment of the application is shown.
The power supply voltage VCC=4.2V of the chip, the power supply voltage Vup=1.8V of the main chip, the reference voltage VREF=1V of the hysteresis comparator in the input circuit, when the input signal voltage Vdwi rises from 0V to 1.8V, the input signal voltage Vdwi returns to 0V, and the output voltage C of the input circuit can accurately identify the high level and the low level of the signal.
Referring to fig. 6, a schematic diagram of an input circuit of another single bus communication chip according to an embodiment of the present application is shown.
Similar to the embodiment described in fig. 4, this embodiment also includes: a hysteresis comparator 1000, an ESD circuit 2000, a pull-up control circuit 3000, a pull-down control circuit 4000, a first output buffer 5000, and a second output buffer 6000.
In addition, the present embodiment further includes: schmitt circuit 7000 and selector 8000.
Schmitt circuit 7000 is connected in parallel with hysteresis comparator 1000; the output of schmitt circuit 7000 is connected to selector 8000.
A selector 8000 for switching an input mode of the input circuit.
The input modes comprise a Schmidt input mode and a hysteresis comparator input mode.
It should be appreciated that the selector 8000 includes a selection signal generating circuit.
By generating the selection signal, the switching of the Schmidt input mode and the hysteresis comparator input mode can be realized, the input circuit of the same IO pin is configured into different input modes, the multiplexing capability of the IO pin is enhanced, and the IO input circuit has better compatibility.
For example: when the SWI is applied, the SWI is configured into an input mode of the hysteresis comparator, so that the requirement of single bus communication electrical characteristics can be met, and the working scene that Vup is far lower than VCC is supported. When used as General-Purpose Input/Output (GPIO) or integrated circuit Input/Output (I2C IO), the Input mode of the schmitt circuit is configured to be the Input mode of the schmitt circuit, and the minimum value of VIH is 0.7 vcc and the maximum value of vil is 0.3 vcc, which meet the requirements of IO specifications.
Based on the input circuit of the single-bus communication chip provided in the above embodiment, the embodiment of the present application further provides a single-bus communication chip, which is described in detail below with reference to the accompanying drawings.
Referring to fig. 7, a schematic diagram of a single bus communication chip according to an embodiment of the present application is shown.
The single-bus communication chip provided by the embodiment of the application comprises a transmitting circuit 7A, a processing circuit 7B and an input circuit 7C of the single-bus communication chip described in the embodiment above.
The first end of the transmitting circuit 7A is used as an IO pin of the chip; a second terminal of the transmission circuit 7A is for the ground GND.
The IO pin of the chip is used for receiving an input signal or sending an output signal.
A first end of the input circuit 7C is connected to a first end of the transmission circuit 7A; a second terminal of the input circuit 7C is connected to the processing circuit 7B.
Specifically, the specific structure and function of the input circuit 7C can be seen in the above embodiments, and will not be described herein.
In the single-bus communication chip provided by the embodiment, when the input circuit identifies the signals received by the IO pins, the upper threshold voltage and the lower threshold voltage used are related to the width-to-length ratio of the set reference voltage and the transistors adopted by the input circuit, and are irrelevant to the chip power supply, so that the single-bus communication chip can accurately identify the received high and low level functions without being limited by the chip power supply, the normal communication of the single-bus communication chip is ensured, and the application scene of the single-bus communication chip is widened.
It should be noted that, in the present description, each embodiment is described in a progressive manner, and each embodiment is mainly described in a different manner from other embodiments, and identical and similar parts between the embodiments are all enough to refer to each other.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the application. Thus, the present application is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (10)
1. An input circuit of a single bus communication chip, comprising: a hysteresis comparator;
the hysteresis comparator includes: a first transistor, a second transistor, a selection path, and a voltage sampling circuit; the select path includes a plurality of transistors;
the grid electrode of the first transistor is used for inputting a first voltage; the drain electrode of the first transistor is connected with the first end of the selection path;
the grid electrode of the second transistor is used for inputting a reference voltage; the drain electrode of the second transistor is connected with the second end of the selection path;
the source electrode of the first transistor and the source electrode of the second transistor are grounded;
the second end of the selection path is connected with the voltage sampling circuit; the third end of the selection path is used for connecting with a power supply;
the selection path includes: a third transistor, a fourth transistor, a fifth transistor, and a sixth transistor; the source electrode of the third transistor is a first end of the selection path; a gate of the third transistor is connected with a gate of the fourth transistor; the source of the fourth transistor is the second end of the selection path; a gate of the fifth transistor is connected with a gate of the sixth transistor; the source electrode of the fifth transistor is connected with the source electrode of the third transistor; the source electrode of the sixth transistor is connected with the source electrode of the fourth transistor; the drains of the third transistor, the fourth transistor, the fifth transistor and the sixth transistor are all connected together and are the third end of the selection path;
the voltage sampling circuit includes: a seventh transistor and an inverter; the drain electrode of the seventh transistor is used for connecting a power supply; a gate of the seventh transistor is connected to the second end of the selection path; the source electrode of the seventh transistor is connected with the input end of the inverter;
the voltage sampling circuit is used for outputting a high level when the first voltage is larger than an upper threshold voltage; outputting a low level when the first voltage is less than a lower threshold voltage;
the upper threshold voltage and the lower threshold voltage are obtained from the reference voltage and the aspect ratio of the first transistor, the second transistor, and the transistors in the select path.
2. The input circuit of claim 1, wherein the voltage sampling circuit further comprises: an eighth transistor, a ninth transistor, and a tenth transistor;
the drain electrode of the eighth transistor is connected with the source electrode of the seventh transistor; a gate of the eighth transistor is connected with a gate of the tenth transistor;
a gate of the ninth transistor is connected to the first end of the selection path; of the ninth transistor
A source electrode is connected with the drain electrode of the tenth transistor;
the drain electrode of the tenth transistor is connected with the grid electrode of the tenth transistor;
the drain electrode of the ninth transistor is used for connecting the power supply; sources of the eighth transistor and the tenth transistor are grounded.
3. The input circuit of claim 1, wherein the hysteresis comparator further comprises: a bias current module;
the bias current module includes: an eleventh transistor and a current source;
the input end of the current source is used for connecting with the power supply; the output end of the current source is used for connecting the grid electrode of the eleventh transistor;
the source of the first transistor and the source of the second transistor are grounded through the drain-source of the eleventh transistor.
4. An input circuit as claimed in any one of claims 1 to 3, further comprising: an electrostatic discharge (ESD) circuit;
the ESD circuit is connected to the input end of the hysteresis comparator; the input end of the hysteresis comparator is the grid electrode of the first transistor.
5. The input circuit of claim 4, further comprising: a pull-up control circuit and a pull-down control circuit;
the pull-up control circuit and the pull-down control circuit are connected between the ESD circuit and the hysteresis comparator.
6. An input circuit as claimed in any one of claims 1 to 3, further comprising: a first output buffer and a second output buffer;
the first output buffer and the second output buffer are connected to the output end of the hysteresis comparator;
the first output buffer is used for waveform shaping of the output signal of the hysteresis comparator;
the second output buffer is used for converting the output signal to a low-voltage power domain.
7. An input circuit as claimed in any one of claims 1 to 3, further comprising: schmitt circuit and selector;
the Schmitt circuit is connected with the hysteresis comparator in parallel;
the output end of the Schmitt circuit is connected with the comparator;
the selector is used for switching the input mode of the input circuit; the input modes include a schmitt input mode and a hysteretic comparator input mode.
8. An input circuit as claimed in any one of claims 1 to 3, wherein the first transistor and the second transistor are NMOS transistors.
9. The input circuit of claim 1, wherein the third transistor, the fourth transistor, the fifth transistor, and the sixth transistor are PMOS transistors.
10. A single bus communication chip comprising a transmitting circuit, a processing circuit and an input circuit of the single bus communication chip of any one of claims 1-9;
the first end of the transmitting circuit is used as an input/output pin of the chip; the second end of the transmitting circuit is used for being grounded;
the first end of the input circuit is connected with the first end of the transmitting circuit; the second end of the input circuit is connected with the processing circuit.
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| CN202310508836.1A CN116232311B (en) | 2023-05-08 | 2023-05-08 | Input circuit of single bus communication chip and chip |
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