JP2008182418A - Semiconductor integrated circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit capable of eliminating difficulty at matching of status setup and readily performing amplitude adjustment of an output signal. <P>SOLUTION: The semiconductor integrated circuit comprises a signal output circuit 1 for forming an output signal, by a switching operation and a control circuit 2 for supplying a control signal to the signal output circuit 1 to control an output signal amplitude. The control circuit 2 comprises a pseudo-circuit portion 3, which imitates the signal output circuit 1; the pseudo-circuit portion 3 comprises a pair of connecting terminals T21 and T22, to which a resistor R2 is connected; in addition, the control circuit 2 comprises a first signal-level control circuit 4 for comparing a voltage level of the connection terminal T21, where a high potential voltage is obtained, with a high signal level of the signal output circuit 1 for controlling the control circuit 2 so that those levels become the same and a second signal-level control circuit 5 for comparing a voltage level of the connection terminal T22, where a low potential voltage is obtained, with a low signal level of the signal output circuit 1 to control the control circuit 2 so that those levels become the same. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a semiconductor integrated circuit, and more particularly to a semiconductor integrated circuit that outputs a small amplitude differential signal under the control of a control circuit.

  In recent years, in the field of video display equipment, with the development of flat panel displays, semiconductor integrated circuits (LSIs) that display and drive flat panel displays and signal processing semiconductor integrated circuits (LSIs) that process display signals It is often used to transmit a small-amplitude differential signal between various circuits, such as data transmission performed between a personal computer and a data display performed between a personal computer and a graphic display. In such a signal transmission, since a small amplitude differential signal is transmitted, there is an advantage that high-speed signal transmission in which electromagnetic interference noise (EMI) is suppressed can be achieved.

  By the way, when transmitting such a small amplitude differential signal, a circuit that controls the signal level and signal amplitude to be transmitted and transmits a small amplitude signal conforming to a certain standard is required. As a typical circuit, a line driver circuit called LVDS (Low Voltage Differential Signaling) is known.

  Here, FIG. 10 is a circuit configuration diagram showing an example of such a known line driver circuit, which is disclosed in International Publication (WO) 2003-040291.

  As shown in FIG. 10, the line driver circuit 50 includes a driver circuit 51 that performs a switching operation by a differential signal, and a replica circuit 52 that has a circuit configuration similar to the driver circuit 51 and controls the driver circuit 51. ing.

  The driver circuit 51 includes a switching circuit 53 including four switching NMOS transistors QN1 to QN4, a load resistor RT connected between a pair of output nodes 54 and 55 of the switching circuit 53, and a node 56 of the switching circuit 53. And a current source consisting of an NMOS transistor QN5 connected between the lower potential points and a current source consisting of an NMOS transistor QN6 connected between the node 57 of the switching circuit 53 and the high potential point.

  The replica circuit 52 includes two NMOS transistors QN8 and QN9 connected in series between the nodes 58 and 59 via two resistors nRT / 2, and an NMOS transistor connected between the node 58 and a high potential point. A current source composed of QN7, a current source composed of an NMOS transistor QN10 connected between the node 59 and a low potential point, a voltage obtained at a node 69 which is a connection point of two resistors nRT / 2, and a first reference voltage An operational amplifier OP10 that compares Vref1 and supplies the comparison output to the gates of the NMOS transistors QN7 and QN6, and means for supplying the second reference voltage Vref2 to the gates of the NMOS transistors QN10 and QN5. ing.

  In this case, the replica circuit 52 is for supplying a control voltage to the gate of the NMOS transistor QN6 that operates as a source follower, and is 1 / n of the size of each NMOS transistor QN1 to QN6 used in the driver circuit 51. Here, n is a positive number larger than 0), each of the NMOS transistors QN7 to QN10, and two resistors (nRT / N) each having a resistance value (n / 2) times the termination resistance RT of the driver circuit 51. 2). The current source NMOS transistor QN10 of the replica circuit 52 and the current source NMOS transistor QN5 of the driver circuit 51 are current mirror-connected, whereby the NMOS transistor QN5 has a drain current ID flowing therethrough and the NMOS transistor QN10 has a drain thereof. A drain current (ID / n) that is 1 / n times the current ID flows.

  In the replica circuit 52, NMOS transistors QN8 and QN9 connected to both sides of the two resistors nRT / 2 respectively correspond to the NMOS transistors QN1 to QN4 of the driver circuit 51. The difference is that the NMOS transistors QN8 and QN9 of the replica circuit 52 are always in the on state, whereas the QN4 performs the on / off operation in response to the input signal. The NMOS transistor QN7, which is a current source, has a gate voltage controlled by the comparison output of the operational amplifier OP10. The first reference voltage Vref1 is supplied to the non-inverting input (+) of the operational amplifier circuit OP10, and the inverting input (− ) Is fed back the voltage of the node 60. As a result, the voltage of the node 60 is controlled to approach the first reference voltage Vref1. On the other hand, a drain current in accordance with the second reference voltage Vref2 flows through the NMOS transistor QN10, whereby the operating current (ID / n) of the replica circuit 52 is determined.

  Further, in the driver circuit 51, the input signals In1 and In2 supplied to the gates of the NMOS transistors QN1 and QN2 are in a range between a low potential voltage (low level ground voltage) and a high potential voltage (high level power supply voltage VDD). The NMOS transistors QN1 to QN4 are turned on and off with the change, and a switching operation is performed. For example, when the input signal In1 is at a low level and the input signal In2 is at a high level, the two NMOS transistors QN1 and QN4 are turned off and the two NMOS transistors QN2 and QN3 are turned on. As a result, a current ID flows from the upper side to the lower side of the terminal resistor RT, and an output voltage ΔV (= ID × RT) is formed between the nodes 54 and 55.

  At this time, also in the replica circuit 52, a current (ID / n) flows from the upper side to the lower side of the two resistors (nRT / 2), and the voltage ΔVR {= (ID / n) between the nodes 58 and 59. X (nRT / 2 + nRT / 2) = ID * RT} is formed.

  On the other hand, when the input signal In1 is at a high level and the input signal In2 is at a low level, the two NMOS transistors QN1 and QN4 are turned on and the two NMOS transistors QN2 and QN3 are turned off. As a result, a reverse current ID from the lower side to the upper side of the figure flows through the termination resistor RT, and an output voltage ΔV (= ID × RT) is formed between the nodes 54 and 55. Also in this case, in the replica circuit 52, the current (ID / n) flows from the upper side to the lower side of the two resistors (nRT / 2), and the voltage ΔVR {= (ID / n) between the nodes 58 and 59. X (nRT / 2 + nRT / 2) = ID * RT} is formed.

  In this case, in the driver circuit 51, the offset potential VOS of the output signal is expressed by VOS = (V54 + V55) / 2 where the voltages of the nodes 54 and 55 are V54 and V55, respectively, and the value is 2 in the replica circuit 52. This is linked to the potential VOSR {= (V58 + V59) / 2} of the node 60 which is a connection point of two resistors. Therefore, the value of the first reference voltage Vref1 supplied to the non-inverting input of the operational amplifier OP10 is determined so that the offset potential VOS, that is, the potential of the node 60 becomes the target value.

As described above, in the known line driver circuit 50, the output current of the driver circuit 51 is controlled by the current mirror connection of the two NMOS transistors QN5 and QN10 connected to the low potential side, and the termination resistor RT of the driver circuit 51 is controlled. The current source NMOS transistor QN6 and the like of the driver circuit 51 are controlled based on the connection voltage of the two resistors (nRT / 2) of the replica circuit 52 provided as a replica so as to stabilize the amplitude and offset potential of the output signal. I have to.
International Publication No. 2003-040291

  In the known line driver circuit, the accuracy of the common voltage, which is the voltage at the connection node 60 of the two resistors (nRT / 2) of the replica circuit 52, matches the matching state between the driver circuit 51 and the replica circuit 52, and the driver circuit 51. In order to increase the accuracy of the common voltage, these matching states are strictly set because they depend on the matching states of the termination resistor RT externally connected to the two resistors (nRT / 2) of the replica 52 respectively. Although it is necessary, such a setting is difficult in terms of a circuit.

  The present invention has been made in view of such a technical background, and an object of the present invention is to eliminate the difficulty of setting the matching state and to easily adjust the amplitude of the output signal. A circuit is provided.

  In order to achieve the above object, a semiconductor integrated circuit according to the present invention outputs a signal output circuit that performs a switching operation by an input differential signal to form an output signal, and supplies a control signal to a current source of the signal output circuit. A semiconductor integrated circuit comprising a control circuit for controlling the amplitude of a signal, the control circuit having a pseudo circuit section that imitates a signal output circuit, and the pseudo circuit section is a pair of resistance connections to which a pseudo termination resistor is connected The voltage level of the resistor connection terminal from which a high potential is derived in the pair of resistor connection terminals is compared with the high signal level of the signal output circuit, and the control circuit A first signal level control circuit that controls the current source, and compares the voltage level of the resistor connection terminal from which the low potential of the pair of resistor connection terminals is derived with the low signal level of the signal output circuit; Level comprises a first structure means having a second signal level control circuit for controlling the current source of the control circuit to be the same.

  In order to achieve the above object, a semiconductor integrated circuit according to the present invention supplies a control signal to a signal output circuit that performs a switching operation by an input differential signal to form an output signal, and a current source of the signal output circuit. The control circuit has a pseudo circuit unit that imitates the signal output circuit, and the pseudo circuit unit has a pair of pseudo termination resistors connected thereto. Comparing the voltage level of the resistance connection terminal that has a resistance connection terminal and from which the high potential or low potential is derived in the pair of resistance connection terminals with the high signal level or low signal level of the signal output circuit, and their correspondence It has a signal level control circuit that controls the current source of the control circuit so that the level is the same, and controls the output signal amplitude to the current source of the control circuit not connected to the signal level control circuit Comprising a second configuration means formed by connecting the current circuit.

  In the first configuration means and the second configuration means, the semiconductor element constituting the signal output circuit and the semiconductor element constituting the pseudo circuit portion of the control circuit can be constituted by semiconductor elements of the same size.

  In the first configuration means and the second configuration means, the size of the semiconductor element constituting the pseudo circuit portion of the control circuit is a fraction of the size of the semiconductor element constituting the signal output circuit. can do.

  Further, the first configuration means and the second configuration means are configured such that the resistance connected to the pair of resistance connection terminals of the pseudo circuit portion of the control circuit is composed of a variable resistor externally connected to the control circuit. be able to.

  Furthermore, in the first configuration means and the second configuration means, resistors connected to the pair of resistance connection terminals of the pseudo circuit portion of the control circuit can be connected so as to be built in the control circuit.

  In this case, in the second configuration means, the signal level control circuit compares the high potential voltage supplied to one of the pair of resistor connection terminals with the high potential reference voltage, and outputs the comparison output to the high potential of the pseudo circuit section. It can be configured to supply each of the side current source and the high potential side current source of the signal output circuit.

  In the second configuration means, the signal level control circuit compares the low potential voltage supplied to the other of the pair of resistor connection terminals with the low potential reference voltage, and outputs the comparison output to the low potential side of the pseudo circuit section. The current source and the low potential side current source of the signal output circuit can be respectively supplied.

  In the second configuration means, the constant current source can be mirror-connected to the high potential side current source of the pseudo circuit section and the high potential side current source of the signal output circuit.

  In the second configuration means, the constant current source can be mirror-connected to the low potential side current source of the pseudo circuit section and the low potential side current source of the signal output circuit.

  In addition, the first and second constituent means can be configured such that the high potential reference voltage and the low potential reference voltage are derived from a digital-analog converter.

  In the first configuration means and the second means, the control circuit may be provided with a terminal for introducing a reference voltage from the outside.

  As described above in detail, according to the semiconductor integrated circuit of the present invention, a pseudo-simulation of a signal output circuit that performs a switching operation by an input differential signal and a signal output circuit that controls the output signal amplitude of the signal output circuit. Using a control circuit including a circuit part, the semiconductor element constituting the pseudo circuit part and the semiconductor element constituting the signal output circuit are formed with exactly the same size, or the size of the semiconductor element constituting the pseudo circuit part is The signal output circuit is formed by 1 / n of the semiconductor elements constituting the signal output circuit, and the resistance component having the same resistance value as the termination resistor of the signal output circuit or a resistance component having a resistance value n times that of the pseudo circuit By connecting to the signal output section, matching between the signal output circuit and the pseudo circuit section can be achieved, and an output signal whose amplitude is adjusted with high accuracy can be easily obtained. .

  According to the semiconductor integrated circuit of the present invention, the resistance connected to the pseudo circuit portion of the control circuit is a variable resistance, and an output signal whose amplitude is easily adjusted is obtained by adjusting the resistance value of the variable resistance. In addition, the size ratio between the semiconductor elements constituting the pseudo circuit portion and the semiconductor elements constituting the signal output circuit is set to 1 / n, and the resistance value of the resistor used in the pseudo circuit portion is output as a signal. By setting the termination resistance value used for the termination resistance of the circuit to n times, in addition to the above-described effects, there is an effect that current consumption in the pseudo circuit portion of the control circuit can be reduced.

  Furthermore, according to the semiconductor integrated circuit of the present invention, the common signal voltage is set by setting the high signal level and the low signal level using the first signal level control circuit and the second signal level control circuit, respectively, in which feedback control is performed. There is an effect that the level and the signal amplitude can be set simultaneously.

  In addition, according to the semiconductor integrated circuit of the present invention, by generating the high potential reference voltage and the low potential reference voltage used for the first signal level control circuit and the second signal level control circuit from the DA converter, There is an effect that the amplitude of the output signal can be easily set. In this case, by providing a terminal to which the external reference voltage supplied from the DA converter is provided, the output signal is similarly used using the external supply reference voltage. It is possible to easily set the amplitude of the.

  Embodiments of the present invention will be described below with reference to the drawings.

  FIG. 1 is a circuit diagram showing a specific circuit configuration of a semiconductor integrated circuit according to the first embodiment of the present invention.

  As shown in FIG. 1, this semiconductor integrated circuit controls a signal output circuit 1 including a switching stage 6 that performs a switching operation by an input differential signal, and an amplitude of a differential signal that is switched by the signal output circuit 1. The control circuit 2 includes a simulation circuit unit 3 having a circuit configuration simulating the circuit configuration of the signal output circuit 1, and voltage comparison circuit units 4 and 5 incorporating two OP amplifiers. Yes.

  The signal output circuit 1 includes a switching stage 6 including four NMOS transistors MN1 to MN4 whose gates are cross-connected, a termination resistor R1 connected between a pair of output nodes T11 and T12 of the switching stage 6, A current source composed of a PMOS transistor MP1 connected between the node T13 of the switching stage 6 and the high potential voltage point, and a current source composed of an NMOS transistor MN5 connected between the node T14 of the switching stage 6 and the low potential voltage point. I have.

  The control circuit 2 includes a simulation circuit unit 3, a first operational amplifier OP 1 that operates as the first signal level control circuit 4, and a second operational amplifier OP 2 that operates as the second signal level control circuit 5. . The simulation circuit unit 3 includes a resistor R2 externally connected between a pair of output nodes (resistance connection terminals) T21 and T22, a PMOS transistor MP2 connected in series between one output node T21 and a high potential voltage point, and An NMOS transistor MN6 and two NMOS transistors MN7 and MN8 connected in series between the other output node T22 and a low potential voltage point. The PMOS transistor MP2 and the NMOS transistor MN8 operate as current sources. It is. The first signal level control circuit 4 has a first operational amplifier OP1, the high potential side reference voltage VrefU is supplied to its non-inverting input (+), and the high potential voltage of one output node T21 is its inverting input ( The comparison output is supplied to the gate of the PMOS transistor MP2 which is a current source and the gate of the PMOS transistor MP1 which is a current source. The second signal level control circuit 5 has a second operational amplifier OP2, the low potential side reference voltage VrefL is supplied to its non-inverting input (+), and the low potential voltage of the other output node T22 is its inverting input ( The comparison output is supplied to the gate of the NMOS transistor MN8, which is a current source, and the gate of the NMOS transistor MN5, which is a current source. The PMOS transistor MP1 and the PMOS transistor MP2 are current mirror connected, and the NMOS transistor MN5 and the NMOS transistor MN8 are similarly current mirror connected.

  In this case, the NMOS transistor MN1 and the NMOS transistor MN2, the NMOS transistor MN3 and the NMOS transistor MN4, the PMOS transistor MP1 and the PMOS transistor MP2, the NMOS transistor MN5 and the NMOS transistor MN8, and the NMOS transistor MN6 and the NMOS transistor MN7 are transistors of the same size. Composed. The same resistance device is used for the externally connected termination resistor R1 and the externally connected resistor R2 between the pair of output nodes T21 and T22. With this configuration, the simulation circuit unit 3 including the PMOS transistor MP2, the three NMOS transistors MN6, MN7, and MN8 and the externally connected resistor R2 in the control circuit 2 simulates the signal output circuit 1 including the termination resistor R1. ing.

  The operation of the semiconductor integrated circuit configured as described above is as follows.

  The signal output circuit 1 performs substantially the same operation as that of the driver 51 described above. When the input signal Vin1 is low and the input signal Vin2 is high, the two NMOS transistors MN1 and MN4 The two NMOS transistors MN2 and MN3 are turned on, the current ID flows from the upper side to the lower side in FIG. 1 through the termination resistor R1, and the output voltage ΔV (= ID × R1) flows between the termination resistors R1. ) Is formed. On the other hand, when the input signal Vin1 is at a high level and the input signal Vin2 is at a low level, the two NMOS transistors MN1 and MN4 are turned on, the two NMOS transistors MN2 and MN3 are turned off, and the termination resistor R1 is connected to the termination resistor R1. A current ID flows from the lower side to the upper side, and an output voltage ΔV (= ID × R1) is formed between the load resistors R1.

  During this operation, the impedance value of the termination resistor R1 externally connected to the signal output circuit 1 is set to 100Ω, the impedance value of the resistor R2 externally connected to the simulation circuit unit 3 of the control circuit 2 is set to 100Ω, and the control circuit 2 Assuming that the high level voltage of the output signal is set to 1.3V as the supplied first reference voltage VrefU, the high level output voltage 1.3V is input to the non-inverting input (+) of the first operational amplifier OP1. Since the voltage of one output node T21 is fed back to the inverting input (−), the high potential voltage of one output node T21 becomes the high level output voltage 1.3V under the control of the first signal level control circuit 4. The gate voltage of the PMOS transistor MP2 is set to be the same voltage, so that the high potential drive voltage of one output node T21 is also output at a high level. It becomes the same voltage as the force voltage 1.3V.

  Similarly, if the low-level output voltage of the output signal is set to 1.1V as the second reference voltage VrefL, the second operational amplifier OP2 has the low-level output voltage 1.1V at its non-inverting input (+). Since the voltage of the other output node T22 is fed back to the inverting input (−), the voltage of the other output node T22 is changed to the low level output voltage 1.1V by the control of the second signal level control circuit 5. The gate voltage of the NMOS transistor MN8 is set so as to be the same voltage, whereby the voltage of the other output node T22 becomes the same voltage as the low level output voltage 1.1V.

  At this time, the current flowing through the externally connected resistor R2 is (T21−T22) / R2 = (1.3−1.1) / 100 = 2 mA.

  In this case, the PMOS transistor MP2 constituting the current source and the PMOS transistor MP1 constituting the current source are connected in a current mirror, and similarly, the current source is constituted with the NMOS transistor MN8 constituting the current source. The NMOS transistor MN5 that is connected is current mirror connected, the size of these transistors is the same, and the termination resistor R1 and the externally connected resistor R2 are of the same configuration, so that the termination resistor R1 The voltage at both ends and the voltage at both ends of the resistor R2 are both equal to VrefU = 1.3V and VrefL = 1.1V, and the signal amplitude and offset level output from the signal output circuit 1 are simultaneously controlled. . At this time, the circuit size of the simulation circuit unit 3 that simulates the signal output circuit 1 is the same as the circuit size of the signal output circuit 1, and the termination resistors R1 and R2 also use the same resistance device. The matching state between the signal output circuit 1 and the simulation circuit unit 3 is very good.

  If the signal output circuit 1 and the simulation circuit unit 3 simulating the signal output circuit 1 are configured with the same circuit size as in this embodiment, the currents flowing in the signal output circuit 1 and the simulation circuit unit 3 are the same. Therefore, the signal output circuit 1 and the simulation circuit unit 3 consume power by the amount of current flowing.

  That is, in order to reduce the current flowing through the simulation circuit unit 3, the size of each of the PMOS transistor MP2 and the NMOS transistors MN6 to MN8 constituting the simulation circuit unit 3 is set to the PMOS transistor constituting the corresponding signal output circuit 1. MP1 and NMOS transistors MN1 to MN5 are each 1 / n of the size of the transistors (where n is a positive number larger than 1), and the resistor R2 has a resistance value n times that of the termination resistor R1. .

  In this example, for example, if n = 10, the sizes of the PMOS transistor MP2 and NMOS transistors MN6 to MN8 of the simulation circuit unit 3 are the same as the sizes of the PMOS transistor MP1 and NMOS transistors MN1 to MN5 of the corresponding signal output circuit 1, respectively. The size of each transistor is 1/10, and the resistance R2 is 1000Ω, which is 10 times 100. When the high potential voltage and the low potential voltage respectively formed at the pair of output nodes T21 and T22 in the simulation circuit unit 3 are set to 1.3 V and 1.1 V, respectively, as in the case of the previous example, the current flowing through the resistor R2 (1.3V-1.1V) /1000Ω=0.2 mA, which is 1/10 that of the previous example, and the power consumption of the simulation circuit unit 3 can be reduced accordingly. it can. At this time, since the current mirror ratio in the signal output circuit 1 and the simulation circuit unit 3 is 10 times, the current flowing through the termination resistor R1 is 2 mA, and the voltage formed at the pair of output nodes T11 and T12 is a pair of outputs. The voltage is the same as that formed at the nodes T21 and T22.

  In the case of an integrated circuit configuration, formation of a multiplication ratio based on the transistor size of the signal output circuit 1 and the simulation circuit unit 3 can be easily realized by connecting as many transistors of the same size as necessary. Also, regarding the setting of the resistance ratio between the externally connected resistor R2 and the terminating resistor R1, since these are externally connected resistors, it is possible to easily realize a highly accurate resistance value.

  Next, FIG. 2 relates to a second embodiment of the semiconductor integrated circuit according to the present invention, and is a circuit diagram showing a specific circuit configuration thereof. The first embodiment shown in FIG. The same components as those used in the semiconductor integrated circuit are given the same reference numerals.

  The semiconductor integrated circuit according to the second embodiment is a resistor externally connected between the pair of output nodes T21 and T22 of the simulation circuit unit 3 in the semiconductor integrated circuit according to the first embodiment shown in FIG. This is an example in which R2 is replaced with a variable resistor R2 ′, and the configuration of each other part is the same as that of the semiconductor integrated circuit according to the first embodiment. Therefore, the description of the configuration of the semiconductor integrated circuit according to the second embodiment and the description of the operation thereof are substantially the same as the configuration of the semiconductor integrated circuit according to the first embodiment already described and the operation thereof. Therefore, their explanation is omitted here except for the following points.

  In the semiconductor integrated circuit according to the second embodiment, if the corresponding transistor sizes constituting the signal output circuit 1 and the simulation circuit unit 3 are the same as in the previous example, they are connected to the simulation circuit unit 3. When the resistance value of the variable resistor R2 ′ is set equal to the resistance value of the termination resistor R1 connected to the signal output circuit 1, the voltages of the high potential output nodes T11 and T21 are on the high potential side as in the previous example. In addition to being equal to the reference voltage VrefU, the voltages at the low potential output nodes T12 and T22 are equal to the low potential side reference voltage VrefL, and each has a preset amplitude level.

  On the other hand, when the resistance value of the variable resistor R2 ′ is set to be smaller than the resistance value of the termination resistor R1, the control circuit 2 is used unless the high potential side reference voltage VrefU and the low potential side reference voltage VrefL are changed. By the control by the first operational amplifier OP1 and the second operational amplifier OP2, the high potential voltage of one output node T21 of the simulation circuit unit 3 becomes equal to the high potential side reference voltage VrefU, and the low potential voltage of the other output node T22 is low. It becomes equal to the potential side reference voltage VrefL.

  At this time, since the resistance value of the variable resistor R2 'is set to be smaller than the resistance value of the termination resistor R1, the current flowing through the variable resistor R2' increases by the smaller amount. If the current flowing through the simulation circuit unit 3 increases, the current flowing through the signal output circuit 1 due to the current mirror connection, that is, the current flowing through the termination resistor R1, also increases, and the amplitude of the output signal formed at both ends of the termination resistor R1. Increases as the current increases.

  On the other hand, when the resistance value of the variable resistor R2 ′ is set to be larger than the resistance value of the termination resistor R1, as in the previous case, the voltage of one output node T21 of the simulation circuit unit 3 and the other output Although the voltage at the node T22 does not change, the current flowing through the termination resistor R2 ′ decreases. Then, the current flowing through the signal output circuit 1, that is, the current flowing through the termination resistor R 1 also decreases due to the decrease in the current flowing through the simulation circuit unit 3, and the amplitude of the differential output signal formed at both ends of the termination resistor R 1 decreases the current. It will decrease by minutes.

  Also in the semiconductor integrated circuit according to the second embodiment, the size of each of the PMOS transistor MP2 and the NMOS transistors MN6 to MN8 constituting the simulation circuit unit 3 is set to the PMOS constituting the corresponding signal output circuit 1. If the size of each of the transistors MP1 and NMOS transistors MN1 to MN5 is reduced to 1 / n (where n is a positive number larger than 1), the current flowing through the simulation circuit unit 3 decreases accordingly. However, even if the resistance value of the variable resistor R2 ′ having a resistance change range centered on 1 / n of the resistance value of the termination resistor R1 is used at that time, the termination of the signal output circuit 1 as described above. The amplitude of the output signal derived from the resistor R1 can be adjusted by adjusting the resistance value of the variable resistor R2 ′.

  As described above, according to the semiconductor integrated circuit according to the second embodiment, unless the high potential side reference voltage VrefU and the low potential side reference voltage VrefL are changed, the resistor externally connected to the simulation circuit unit 3 is a variable resistor. If the resistance value is appropriately set as R2 ′, the amplitude of the differential output signal can be adjusted. At this time, if the size of each transistor constituting the simulation circuit unit 3 is set to 1 / n of the corresponding transistor size constituting the signal output circuit 1, the amplitude adjustment of the output signal can be increased while reducing power consumption. Can be done with precision.

  Next, FIG. 3 relates to a third embodiment of the semiconductor integrated circuit according to the present invention, and is a circuit diagram showing a specific circuit configuration thereof, and relates to the first embodiment shown in FIG. The same components as those used in the semiconductor integrated circuit are denoted by the same reference numerals.

  The semiconductor integrated circuit according to the third embodiment has resistors connected between the pair of output nodes T21 and T22 of the simulation circuit unit 3 in the semiconductor integrated circuit according to the first embodiment shown in FIG. In this example, the resistor R2 ″ is connected to the inside of the simulation circuit unit 3, and the other components are the same as those of the semiconductor integrated circuit according to the first embodiment. The configuration and operation of the semiconductor integrated circuit according to the embodiment are almost the same as the configuration and operation of the semiconductor integrated circuit according to the first embodiment already described. Omitted except.

  In the semiconductor integrated circuit according to the third embodiment, as in the previous example, when each transistor size constituting the signal output circuit 1 and the corresponding transistor size constituting the simulation circuit unit 3 are the same, the resistor R2 Is selected to be the same as the resistance value of the termination resistor R1. At this time, the operation of the semiconductor integrated circuit according to the third embodiment is the same as that of the semiconductor integrated circuit according to the first embodiment. Thus, an output signal is derived between the pair of output nodes T11 and T12 so that the high potential level matches the high potential side reference voltage VrefU and the low potential level matches the low potential side reference voltage VrefL. In such a configuration, the size of each transistor constituting the signal output circuit 1 and the size of each corresponding transistor constituting the simulation circuit unit 3 are the same. Quenching state has become remarkably suitable conditions.

  Incidentally, since the accuracy of the resistance value of the internally connected resistor R2 ″ depends on the processing accuracy of the integrated circuit manufacturing technique, the externally connected resistor R1 as in the semiconductor integrated circuit according to the first embodiment. Compared with the case where R2 is realized by the same resistance element, it is somewhat difficult to match the accuracy of the resistance value. With such a configuration, it is possible to simultaneously control the amplitude and the common level of the output signal. become.

  On the other hand, as shown in FIG. 4, a plurality of (n) resistors Rm1 to Rmn are connected in parallel between a pair of output nodes T21 and T22, and in order to select each resistor Rm1 to Rmn, they are connected in series. It is possible to adopt a variable resistance configuration in which switch elements S1 to Sn are connected to each other. In this example, since the entire resistance value can be changed by selecting ON / OFF of the switch elements S1 to Sn, the matching state can be improved with the strictness of the processing accuracy reduced. It becomes possible. In addition, the example of such a variable resistance type configuration is merely an example, and does not specify the configuration of the variable resistor to be used.

  Also in the semiconductor integrated circuit according to the third embodiment, if the size of each transistor constituting the simulation circuit unit 3 is set to 1 / n of the corresponding transistor size constituting the signal output circuit 1, so far It becomes possible to realize the functions as described together.

  Next, FIG. 5 relates to a fourth embodiment of the semiconductor integrated circuit according to the present invention, and is a circuit diagram showing a specific circuit configuration thereof. The first embodiment shown in FIG. The same components as those used in the semiconductor integrated circuit are given the same reference numerals.

  The semiconductor integrated circuit according to the fourth embodiment is an example in which the control of the output signal level and the amplitude control of the output signal can be individually controlled, and the constant current circuit CI1 is used instead of the first operational amplifier OP1. Is used. The semiconductor integrated circuit according to the fourth embodiment is the semiconductor according to the first embodiment shown in FIG. 1 except that the constant current circuit CI1 is used instead of the first operational amplifier OP1. The configuration is the same as that of the integrated circuit.

  The constant current circuit CI1 in the semiconductor integrated circuit according to the fourth embodiment includes a PMOS transistor MP3 connected in series between the power supply line VDD and the ground line and a current source IS1 from which the current I1 is derived. Thus, the gate and the source of the PMOS transistor MP3 are directly connected to the gate of the PMOS transistor MP2 of the simulation circuit unit 3, whereby the PMOS transistor MP3, the PMOS transistor MP2, and the PMOS transistor MP1 are in a current mirror connection.

  Here, assuming that the transistor size of the PMOS transistor MP2 is m times the transistor size of the PMOS transistor MP3 (m is a positive number of 1 or more), the PMOS transistor MP2 is changed to the current I1 flowing through the PMOS transistor MP3. Current mI1 flows. At this time, the same current mI1 flows through the resistor R2, and the signal amplitude formed between the pair of output nodes T21 and T22 is mI1 × R2.

  At this time, the low signal level in the output signal of the signal output circuit 1 is such that the low potential voltage of the other output node T22 supplied to the inverting input (−) of the second operational amplifier OP2 is applied to the non-inverting input (+). It is controlled by the supplied low potential side reference voltage VrefL, and each voltage of the corresponding output nodes T22 and T12 is set equal to the low potential side reference voltage VrefL.

  As described above, in this embodiment, the low signal level of the output signal and the amplitude of the output signal are individually controlled, and the output signal amplitude and the common level can be individually controlled.

  FIG. 6 is a circuit diagram showing a specific circuit configuration according to the fifth embodiment of the semiconductor integrated circuit according to the present invention, and is related to the fourth embodiment shown in FIG. The same components as those used in the semiconductor integrated circuit are denoted by the same reference numerals.

  The semiconductor integrated circuit according to the fifth embodiment is such that the semiconductor integrated circuit according to the fourth embodiment shown in FIG. 5 controls the low signal level of the output signal. The high signal level of the output signal is controlled. The difference in configuration between the semiconductor integrated circuit according to the fifth embodiment (this circuit is called the former circuit) and the type semiconductor integrated circuit according to the fourth embodiment (this circuit is called the latter circuit) is as follows. In the latter circuit, the low potential side reference voltage VrefL is supplied to the inverting input (+) of the second operational amplifier OP2, and the low potential voltage of the other output node T22 is supplied to the non-inverting input (−). The former circuit is such that the high potential side reference voltage VrefU is supplied to the inverting input (+) of the second operational amplifier OP2, and the high potential voltage of one output node T21 is supplied to the non-inverting input (−). There is only a difference, and other configurations are not different between the former circuit and the latter circuit.

  As in the semiconductor integrated circuit according to the fifth embodiment, the high potential side reference voltage VrefU is supplied to the inverting input (+) of the second operational amplifier OP2, and the high level of one output node T21 is supplied to the non-inverting input (−). With the configuration in which the potential voltage is supplied, the voltage of the high potential output node T21 of the simulation circuit unit 3 and the voltage of the high potential output node T11 of the signal output circuit 1 are respectively controlled by the second operational amplifier OP2. It is controlled to be equal to the reference voltage VrefU, and the effect obtained thereby is almost the same as the effect obtained in the semiconductor integrated circuit according to the fifth embodiment.

  Next, FIG. 7 relates to a sixth embodiment of the semiconductor integrated circuit according to the present invention, and is a circuit diagram showing a specific circuit configuration thereof. The first embodiment shown in FIG. The same components as those used in the semiconductor integrated circuit are denoted by the same reference numerals.

  The semiconductor integrated circuit according to the sixth embodiment is an example in which the control of the output signal level and the amplitude control of the output signal are individually controlled as in the previous example, and a constant current is used instead of the second operational amplifier OP2. The circuit CI2 is used. The semiconductor integrated circuit according to the sixth embodiment is the semiconductor according to the first embodiment illustrated in FIG. 1 except that the constant current circuit CI2 is used instead of the second operational amplifier OP2. The configuration is the same as that of the integrated circuit.

  The constant current circuit CI2 in the semiconductor integrated circuit according to the sixth embodiment comprises a current source IS2 for deriving a current I2 connected in series between the power supply line VDD and the ground line, and an NMOS transistor MN9. The gate and drain of the transistor MN9 are directly connected to the gate of the NMOS transistor MN8 of the simulation circuit unit 3, whereby the NMOS transistor MN9, the NMOS transistor MP8, and the NMOS transistor MN5 are current-mirror connected.

  In this case, the PMOS transistors MP1 and MP2, the NMOS transistors MN1 to MN5, and the NMOS transistors MN6 to MN8 have the same transistor size, and the same resistance device is used for the termination resistor R1 and the resistor R2. Then, the transistor size of the NMOS transistor MN8 is m times the transistor size of the NMOS transistor MN9 (where m is a positive number of 1 or more) between the NMOS transistor MN9 and the NMOS transistor MN9 that is current-mirror connected to the NMOS transistor MN8. By doing so, a current mI2 that is m times the current I2 flowing through the NMOS transistor MN9 flows through the NMOS transistor MN8, and at the same time, the same current mI2 flows through the resistor R2, and a pair of output nodes T21, T2 Signal amplitude formed between will MI2 × R2.

  Further, since the voltage of one output node T21 is supplied to the inverting input (−) of the first operational amplifier OP1, and the high potential side reference voltage VrefU is supplied to the non-inverting input (+), the high signal level of the output signal. Is controlled by the potential side reference voltage VrefU, and is controlled so that the voltage at one output node T21 of the simulation circuit unit 3 and the voltage at one output node T11 of the signal output circuit 1 are equal to the high potential side reference voltage VrefU, respectively. Is done.

  As described above, according to the semiconductor integrated circuit of the sixth embodiment, the differential signal amplitude and the common level can be controlled by individually controlling the high potential level and the output signal amplitude of the output signal. Thus, similar to the above-described example, the matching state of the transistor size and the matching state of the resistance value with the externally connected resistors R1 and R2 can be controlled with good accuracy.

  Next, FIG. 8 relates to a seventh embodiment of the semiconductor integrated circuit according to the present invention, and is a circuit diagram showing a specific circuit configuration thereof, and relates to the sixth embodiment shown in FIG. The same components as those used in the semiconductor integrated circuit are denoted by the same reference numerals.

  The semiconductor integrated circuit according to the seventh embodiment is such that the semiconductor integrated circuit according to the sixth embodiment shown in FIG. 7 controls the high signal level of the output signal. The low signal level of the output signal is controlled. The semiconductor integrated circuit according to the seventh embodiment (herein, this circuit is again referred to as the former circuit) and the semiconductor integrated circuit according to the sixth embodiment (herein, this circuit is again referred to as the latter circuit). The latter circuit is configured such that the high potential side reference voltage VrefU is supplied to the inverting input (+) of the first operational amplifier OP1, and the high potential voltage of one output node T21 is supplied to the non-inverting input (−). Is supplied to the inverting input (+) of the first operational amplifier OP1, and the low potential side reference voltage VrefL is supplied to the non-inverting input (−) of the other output node T22. There is no difference between the former circuit and the latter circuit except for the difference that the potential voltage is supplied.

  As in the semiconductor integrated circuit according to the seventh embodiment, the low potential side reference voltage VrefL is supplied to the inverting input (+) of the first operational amplifier OP1, and the low level of the other output node T22 is supplied to the non-inverting input (−). With the configuration in which the potential voltage is supplied, in the first operational amplifier OP1, the low signal level of each voltage and output signal of the other output node T22 of the simulation circuit unit 3 and the other output node T12 of the signal output circuit 1 is low. Control is performed to be equal to the potential-side reference voltage VrefL, and the effect obtained thereby is almost the same as the effect obtained in the semiconductor integrated circuit according to the sixth embodiment.

  Next, FIG. 9 relates to an eighth embodiment of the semiconductor integrated circuit according to the present invention, and is a circuit diagram showing a specific circuit configuration thereof. The first embodiment shown in FIG. The same components as those used in the semiconductor integrated circuit are given the same reference numerals.

  The semiconductor integrated circuit according to the eighth embodiment includes a high potential side reference voltage VrefU and a second operational amplifier OP2 that are supplied to the first operational amplifier OP1 of the semiconductor integrated circuit according to the first embodiment shown in FIG. The low-potential-side reference voltage VrefL supplied to is supplied from the digital-analog converters DA1 and DA2, respectively, and the other configuration is the same as that of the semiconductor integrated circuit according to the first embodiment. is there.

  The configuration and operation of the semiconductor integrated circuit according to the eighth embodiment are the same except that the high potential side reference voltage VrefU and the low potential side reference voltage VrefL are supplied from the digital-analog converters DA1 and DA2, respectively. The configuration and operation of the semiconductor drive circuit according to the first embodiment shown in FIG. 1 are almost the same. During the operation of the semiconductor integrated circuit according to the eighth embodiment, the first operational amplifier OP1 takes in the output high potential side reference voltage VrefU of the digital-analog converter DA1 that generates the high potential side reference voltage VrefU, and the low potential side The second operational amplifier OP2 takes in the output low potential side reference voltage VrefL of the digital-analog converter DA2 that generates the reference voltage VrefL. By adjusting the digital-analog converters DA1 and DA2, the high potential side reference voltage VrefU and the low potential are adjusted. The side reference voltage VrefL is easily controlled, so that the amplitude and common level of the output signal can be easily set to arbitrary values.

  In each of the semiconductor integrated circuits according to the fourth to eighth embodiments, the transistor size of the signal output circuit 1 and the transistor size of the simulation circuit unit 3 are changed to different sizes instead of the same size. Even when the resistor R2 is built in or formed with a variable resistor, the same function as described above can be achieved.

  Further, in each of the semiconductor integrated circuits according to the first to eighth embodiments, the control circuit 2 is not supplied with the high potential side reference voltage VrefU or the low potential side reference voltage VrefL as an internal signal, but with an external supply. It is also possible to provide a connection terminal for supplying an external signal, and by using such a connection terminal, it is possible to supply the reference voltage after setting the reference voltage to an arbitrary value, It becomes possible to easily set the common level to an arbitrary value.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a circuit diagram showing a specific circuit configuration according to a first embodiment of a semiconductor integrated circuit according to the present invention. FIG. 6 is a circuit diagram showing a specific circuit configuration according to a second embodiment of the semiconductor integrated circuit according to the present invention. FIG. 10 is a circuit diagram showing a specific circuit configuration of a semiconductor integrated circuit according to a third embodiment of the present invention. It is a circuit diagram which shows an example which implement | achieves load resistance R2 of the semiconductor integrated circuit which concerns on 3rd Embodiment in the form of variable resistance. FIG. 10 is a circuit diagram showing a specific circuit configuration of a semiconductor integrated circuit according to a fourth embodiment of the present invention. FIG. 10 is a circuit diagram showing a specific circuit configuration of a semiconductor integrated circuit according to a fifth embodiment of the present invention. FIG. 10 is a circuit diagram showing a specific circuit configuration of a semiconductor integrated circuit according to a sixth embodiment of the present invention. FIG. 20 is a circuit diagram showing a specific circuit configuration according to a seventh embodiment of the semiconductor integrated circuit according to the present invention. FIG. 20 is a circuit diagram showing a specific circuit configuration according to an eighth embodiment of the semiconductor integrated circuit of the present invention. It is a circuit block diagram which shows an example of a known line driver circuit.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Signal output circuit 2 Control circuit 3 Simulated circuit part 4 1st voltage comparison circuit part 5 2nd voltage comparison circuit part 6 Switching stage OP1 1st operational amplifier OP2 2nd operational amplifier MN1-MN9 NMOS transistor MP1-MP3 PMOS transistor T11, T12, T21, T22 Output node R1 Termination resistor R2, R2 ′, R2 ″ Resistance VrefU High potential side reference voltage VrefL Low potential side reference voltage Rm1 to Rmn Resistive elements S1 to Sn Switch elements CI1, CI2 Constant current circuits IS1, IS2 Current source DA1 , DA2 analog-to-digital converter

Claims (15)

In a semiconductor integrated circuit comprising a signal output circuit that forms an output signal by performing a switching operation by an input differential signal, and a control circuit that supplies a control signal to a current source of the signal output circuit to control the amplitude of the output signal The control circuit includes a pseudo circuit unit that imitates the signal output circuit, and the pseudo circuit unit includes a pair of resistance connection terminals to which a pseudo termination resistor is connected. A first signal level control circuit for comparing a voltage level of a resistance connection terminal from which a potential is derived and a high level signal level of the signal output circuit and controlling a current source of the control circuit so that the levels are the same; And comparing the voltage level of the resistor connection terminal from which the low potential of the pair of resistor connection terminals is derived with the low level signal level of the signal output circuit so that the levels are the same. The semiconductor integrated circuit and having a second signal level control circuit for controlling the current source of the serial control circuit. 2. The semiconductor integrated circuit according to claim 1, wherein the transistors constituting the pseudo circuit section and the transistors constituting the signal output circuit are of equal size. 2. The semiconductor integrated circuit according to claim 1, wherein the transistor constituting the pseudo circuit section is configured to be a fraction of the size of the transistor constituting the signal output circuit. . 4. The semiconductor integrated circuit according to claim 1, wherein the resistor externally connected to the pair of resistance connection terminals of the pseudo circuit unit is a variable resistor. 5. The semiconductor integrated circuit according to claim 1, wherein a resistance connected to a pair of resistance connection terminals of the pseudo circuit portion is built in the control circuit. 6. Integrated circuit. A signal output circuit that forms an output differential signal by performing a switching operation by an input differential signal, and a control circuit that controls the amplitude of the output differential signal by supplying a control signal to a current source of the signal output circuit. In the semiconductor integrated circuit, the control circuit includes a pseudo circuit unit that imitates the signal output circuit, the pseudo circuit unit includes a pair of resistance connection terminals to which a pseudo termination resistor is connected, and the pair of resistance connection terminals The voltage level of the resistor connection terminal from which the high potential or low potential is derived is compared with the high level signal level or low level signal level of the signal output circuit, and the corresponding level of the control circuit is set to be the same. A signal level control circuit for controlling the current source is provided, and a constant current circuit for controlling the output signal amplitude is connected to the current source of the control circuit to which the signal level control circuit is not connected. The semiconductor integrated circuit according to claim. 7. The semiconductor integrated circuit according to claim 6, wherein the current source controlled by the signal level control circuit is a low potential side current source, and the current source controlled by the constant current circuit is a high potential side current source. A semiconductor integrated circuit. 7. The semiconductor integrated circuit according to claim 6, wherein the current source controlled by the signal level control circuit is a high potential side current source, and the current source controlled by the constant current circuit is a low potential side current source. A semiconductor integrated circuit. 9. The semiconductor integrated circuit according to claim 6, wherein the transistors constituting the pseudo circuit section and the transistors constituting the signal output circuit are configured to have the same size. 10. A semiconductor integrated circuit. 9. The semiconductor integrated circuit according to claim 6, wherein the transistor constituting the pseudo circuit section is configured to be a fraction of the size of the transistor constituting the signal output circuit. A semiconductor integrated circuit. 11. The semiconductor integrated circuit according to claim 6, wherein the resistor externally connected to the pair of resistance connection terminals of the pseudo circuit unit is a variable resistor. 6. The semiconductor integrated circuit according to claim 1, wherein the reference voltage for determining the signal amplitude level supplied to the signal level control circuit is an analog voltage output from a DA converter. A semiconductor integrated circuit. 11. The semiconductor integrated circuit according to claim 6, wherein a reference voltage for determining a signal amplitude level supplied to each of the first signal level control circuit and the second signal level control circuit is DA. A semiconductor integrated circuit, which is an analog voltage output from a converter. 12. The semiconductor integrated circuit according to claim 11, wherein a reference voltage for determining a signal amplitude level supplied to the signal level control circuit is an analog voltage output from a DA converter. 15. The semiconductor integrated circuit according to claim 1, further comprising an external terminal to which a reference voltage is supplied.

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