WO2012117456A1

WO2012117456A1 - Differential driver circuit

Info

Publication number: WO2012117456A1
Application number: PCT/JP2011/003817
Authority: WO
Inventors: 義英小松; 剛志江渕
Original assignee: パナソニック株式会社
Priority date: 2011-03-03
Filing date: 2011-07-04
Publication date: 2012-09-07

Abstract

In this current mode differential driver circuit, replica transistors (M5 to M8) having high on-resistance values with respect to output switch transistors (M1 to M4) that configure driver main units (11 and 12) are connected in parallel so that, by causing low current to flow at the replica transistors (M5 to M8) to replica termination transistors (R9 and R10) which have resistance values which are larger than the actual termination resistors, virtual potentials of the plus side and the minus side are acquired at replica circuits (13 and 14) so as to feed-back the virtual potentials to current source transistors (M9 and M10). As a result, variation in resistors and variation in transistors are compensated for in order to achieve a differential driver circuit which performs well for long-distance transmission at a low power supply voltage.

Description

Differential driver circuit

The present invention relates to a differential driver circuit, and more particularly to a differential serial data transmission technique.

In recent years, various transmission methods have been used as a data transmission method between devices and a data transmission method between a host device and a memory card. Among them, a differential method is adopted as one means for increasing the transmission speed. If a differential driver circuit that generates a differential signal is used, communication with a low amplitude is possible, and signal transmission can be realized at high speed (see Patent Document 1).

Generally, the differential driver circuit is often configured by a current mode differential driver system in which the direction of current is changed by an output switch using a constant current circuit. This method is widely used in the LVDS (Low Voltage Differential Driver) transmission method. As a feature, a constant current of about 2 mA flows through the terminating resistor 100Ω on the receiving side, so that the amplitude on the receiving side is guaranteed, so that long distance transmission from several tens of centimeters to several meters is possible, parasitic wiring Advantages that are not easily affected by resistance are listed.

A current mode differential driver circuit having a configuration for correcting an output current in accordance with a change in common mode potential is also known (see Patent Document 2).

US Pat. No. 6,118,438 JP 2004-253859 A

However, in the conventional current mode differential driver circuit, it is generally difficult to reduce the voltage. The reason is that at least four stages of transistors are required to be stacked vertically between the power source and the ground, and further, it is necessary to secure a potential difference corresponding to the amplitude of the termination resistor. Therefore, if the constant current source is designed to be saturated, For example, a power supply voltage of 1.8 V or more is required. In this case, for example, a differential driver circuit that operates with a power supply voltage of 1.2 V cannot be realized.

In addition, in order to suppress variations in the constant current source, when a current source having a cascode configuration is used, a six-stage transistor is required, and the power supply voltage cannot be lowered more and more. Since the variation in the constant current source directly affects the differential output voltage, if the cascode configuration cannot be achieved, the value of the current change tends to increase and the variation in the differential voltage amplitude increases.

There is also a problem of reflection. Generally, the output impedance of a differential driver circuit that outputs a signal to a transmission line having a differential impedance of 100Ω is preferably 50Ω. However, since the output switch transistor of the differential driver circuit is completely turned on / off as a digital transistor, the output impedance is lowered. For this reason, reflection tends to occur at the output end of the differential driver circuit.

Therefore, the present invention compensates for resistance variations and transistor variations by mounting a circuit that guarantees the required output voltage amplitude in a current mode differential driver circuit, and is a differential that is strong for long-distance transmission with a low power supply voltage. An object is to realize a driver circuit.

In order to achieve the above object, the present invention provides a differential driver circuit for driving a transmission line pair so that a current flows through a termination resistor connected between the transmission line pair. A configuration including a circuit and a feedback circuit is employed. That is, the driver body is connected between the first current source transistor on the power source side, the second current source transistor on the ground side, and the first current source transistor and the second current source transistor, respectively, via the transmission line pair. And a plurality of output switch transistors for controlling the current flowing through the terminating resistor. The replica circuit includes a replica termination resistor having a resistance value greater than the resistance value of the termination resistor, an on-resistance value greater than each of the plurality of output switch transistors, and a first current source transistor and a second current source transistor. And a plurality of replica transistors that are connected between the current source transistors and generate a plus-side virtual potential and a minus-side virtual potential by flowing a current through the replica termination resistor. The feedback circuit controls the first current source transistor according to the plus-side virtual potential so that the plus-side potential and the minus-side potential of the transmission line pair become predetermined potentials, and according to the minus-side virtual potential. The second current source transistor is controlled.

According to the present invention, the plus-side virtual potential and the minus-side virtual potential generated by the replica circuit are fed back, so that the plus-side potential and the minus-side potential of the transmission line pair are guaranteed even with a low power supply voltage. be able to. That is, it is possible to eliminate the influence of resistance variation and current variation from the differential voltage amplitude generated in the termination resistor.

1 is a circuit diagram showing a configuration of a differential driver circuit according to an embodiment of the present invention. It is a block diagram which shows the use condition of the differential driver circuit of FIG. It is a figure which shows the frequency characteristic of the output impedance of the differential driver circuit of FIG. It is a figure which shows the output characteristic of the differential driver circuit of FIG. It is a figure which shows the output characteristic of the differential driver circuit which concerns on a comparative example.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 shows the configuration of the differential driver circuit 10 according to the present embodiment, and FIG. 2 shows the usage state of the differential driver circuit 10.

As shown in FIG. 1, a differential driver circuit 10 according to the present embodiment is a circuit for generating a differential signal for data communication between devices, for example, and outputs constituting the

driver bodies

11 and 12. The switch transistors M1 to M4 and the protective resistors R1 to R4, the positive output terminal DATA_P of the differential driver circuit 10, the negative output terminal DATA_N of the differential driver circuit 10, and the replica transistor M5 constituting the

replica circuits

13 and 14 M8, replica protection resistors R5 to R8 and replica termination resistors R9 and R10, a current source transistor M9 on the power supply VDD side, a current source transistor M10 on the ground VSS side, a serial data input signal SER, and an enable signal ENA To control the on / off of the output switch transistors M1 to M4. 15 and 16, resistors R11 and R12 inserted in series in the feedback loop, resistor R13 and capacitor C1 constituting the first filter, resistor R14 and capacitor C2 constituting the second filter, and a positive virtual potential A differential amplifier circuit 21 that controls the current source transistor M9 so that is equal to the reference potential 0.3V, and a differential amplifier that controls the current source transistor M10 so that the negative virtual potential is equal to the reference potential 0.1V A circuit 22, a potential generating circuit 30 for generating a reference potential of 0.3 V and 0.1 V from a power supply VDD of 1.2 V, for example, and a current source transistor M9 and output switch transistors M1 and M3 so as to constitute a first AC impedance circuit Between the resistor R15 and the capacitor C3 inserted between the connection point between the resistor R15 and the power supply VDD or the ground VSS. A resistor R16 and a capacitor C4 inserted in series between the connection point of the current source transistor M10 and the output switch transistors M2 and M4 and the power supply VDD or the ground VSS so as to constitute a column circuit and a second AC impedance circuit. Circuit.

As shown in FIG. 2, the plus side output terminal DATA_P and the minus side output terminal DATA_N of the differential driver circuit 10 according to the present embodiment are each a receiving device via a transmission line pair L1, L2 having a characteristic impedance of 50Ω, for example. 40 and further connected to the terminating resistor circuit 41. The termination resistor circuit 41 includes termination resistors R17 and R18 each having a resistance value of 50Ω, for example, and switches S1 and S2 that are closed during communication. The connection point of both termination resistors R17 and R18 is connected to the power supply VDD via the capacitor C5. In a state where both switches S1 and S2 are closed, the differential driver circuit 10 drives the transmission line pair L1 and L2 so that a current flows through the series circuit of the terminating resistors R17 and R18. As a result, the differential plus side potential Vp from one transmission line L1 and the differential minus side potential Vn from the other transmission line L2 are applied to the series circuit of the termination resistors R17 and R18, respectively. As a result, the termination resistors R17 and R18. A differential voltage amplitude Vdiff is obtained at both ends of the series circuit. This differential voltage amplitude Vdiff is
Vdiff = | Vp−Vn |
It is represented by

Now, the circuit configuration of the

driver bodies

11 and 12 including the output switch transistors M1 to M4 and the protection resistors R1 to R4 in FIG. 1 is n-parallel with the same configuration (n is a value larger than 1, especially an integer value, for example, 15). It is said. Thus, the replica transistors M5 to M8 have an on-resistance value that is n times the on-resistance value of the output switch transistors M1 to M4, and the replica protection resistors R5 to R8 have a resistance that is n times the resistance value of the protection resistors R1 to R4. Each of the replica termination resistors R9 and R10 is set to have a resistance value that is n times the sum of the resistance values of the termination resistors R17 and R18. In the case of R17 + R18 = 100Ω and n = 15, R9 = R10 = 1.5 kΩ.

The four replica transistors M5 to M8 are connected between the current source transistor M9 on the power supply VDD side and the current source transistor M10 on the ground VSS side, and are turned on simultaneously in response to the enable signal ENA. A positive virtual potential and a negative virtual potential are generated by flowing a current 1 / n of the current flowing through the output switch transistors M1 to M4 through R10. Then, the differential amplifier circuit 21 causes the current source transistor M9 to respond to the plus-side virtual potential so that the differential plus-side potential Vp and the differential minus-side potential Vn of the transmission line pair L1, L2 are respectively predetermined potentials. The differential amplifier circuit 22 feedback-controls the current source transistor M10 in accordance with the negative virtual potential.

1 makes it possible to control the output potentials of the

driver bodies

11 and 12 without affecting the output switch transistors M1 to M4 of the

driver bodies

11 and 12. In addition, since the output potential is guaranteed by the

replica circuits

13 and 14, it is possible to eliminate the influence of variations in the current source transistors M9 and M10, variations in the output switch transistors M1 to M4, variations in parasitic resistance, and the like. Specifically, by supplying an accurate reference potential (0.3 V and 0.1 V) from the potential generation circuit 30, the influence of variations on the differential voltage amplitude Vdiff can be suppressed. Comparing voltage variation and current variation in general fine processes from the 150 nm generation to the 32 nm generation in recent years, the voltage variation value can be set to 4 to 6 times smaller. As the miniaturization progresses, the difference tends to increase. Therefore, in such a differential driver circuit 10, a circuit configuration that is guaranteed by voltage is desirable.

In addition, since the protection resistors R1 to R4 are inserted in the current paths of the output switch transistors M1 to M4 in the

driver bodies

11 and 12, it is possible to increase the ESD (Electro-Static Discharge) resistance of the differential driver circuit 10. Further, since the protection resistors R1 to R4 as well as the output switch transistors M1 to M4 have an n-parallel configuration, their resistance components can be made small enough to be ignored in total.

Further, if the constant ratio n between the

driver bodies

11 and 12 and the

replica circuits

13 and 14 is increased, the

replica circuits

13 and 14 can be operated with a slight auxiliary current. The power consumption of the entire circuit 10 can be suppressed.

FIG. 3 shows the frequency characteristics of the output impedance Zout of the differential driver circuit 10 as seen from the transmission line side. The output impedance Zout is obtained by adding the protective resistance R2 and the on-resistance RM2 of the output switch transistor M2 to the parallel impedance of the on-resistance RM10 of the current source transistor M10 and the series impedance of the resistor R16 and the capacitor C4. Thus, it has a component of angular frequency ω (= 2πf), that is, a component of frequency f. Accordingly, the output impedance Zout can be set to 50Ω in a specific frequency region by appropriately selecting the resistor R16 and the capacitor C4. The series impedance of the resistor R15 and the capacitor C3 works in the same way.

Therefore, the reflection generated at the driver output ends of the transmission line pair L1 and L2 can be reduced by the AC impedance circuits R15 and C3; R16 and C4.

4 shows the output characteristics of the differential driver circuit 10 of FIG. 1, and FIG. 5 shows the output characteristics of the differential driver circuit according to the comparative example. In the comparative example, the

replica circuits

13 and 14 in FIG. 1 are not provided, the current source transistors M9 and M10 are replaced with constant current sources of about 2 mA, respectively, and a power supply voltage of 1.8 V or more is given. . Compared with the output waveform of FIG. 5, the output waveform of FIG. 4 has less blurring of the waveform mainly in the voltage direction. This indicates that there is little variation due to fluctuations in power supply voltage and temperature, that is, resistance to variations in characteristics of transistors and resistors. In other words, the differential driver circuit 10 of FIG. 1 shows that the sensitivity of the characteristic variation is low with respect to the characteristic variations of the transistors and resistors.

The differential driver circuit according to the present invention can be designed with a digital transistor having a low threshold, can realize a circuit configuration capable of greatly reducing power consumption, and can realize data transmission with guaranteed output potential. Therefore, it is useful for an interface for communication in a mobile device such as a mobile phone.

DESCRIPTION OF SYMBOLS 10

Differential driver circuit

11 and 12 Driver

main body

13 and 14

Replica circuit

15 and 16

Logic circuit

21 and 22 Differential amplifier circuit 30 Potential generation circuit 40 Receiving device 41 Termination resistor circuit C1-C5 Capacity | capacitance DATA_N Negative side of differential driver circuit Output terminal DATA_P Positive side output terminal ENA of differential driver circuit ENA enable signal L1, L2 Transmission line pair M1-M4 Output switch transistor M5-M8 Replica transistor M9, M10 Current source transistors R1-R4 Protection resistance R5-R8 Replica protection resistance R9 , R10 Replica termination resistors R11 to R16 Resistors R17, R18 Termination resistors S1, S2 Switch SER Serial data input signal VDD Power supply Vdiff Differential voltage amplitude Vn Differential minus side potential Vp Differential plus side potential VSS Ground Zout The output impedance of the dynamic driver circuit

Claims

A differential driver circuit that drives the transmission line pair so as to pass a current through a termination resistor connected between the transmission line pair,
A first current source transistor on the power supply side, a second current source transistor on the ground side, and connected between the first current source transistor and the second current source transistor, respectively, and the termination via the transmission line pair A driver body having a plurality of output switch transistors for controlling a current flowing through the resistor;
A replica termination resistor having a resistance value greater than the resistance value of the termination resistor, an on-resistance value greater than each on-resistance value of each of the plurality of output switch transistors, and the first current source transistor and the first A replica circuit having a plurality of replica transistors that are connected between two current source transistors and generate a plus-side virtual potential and a minus-side virtual potential by passing a current through the replica termination resistor;
The first current source transistor is controlled according to the plus-side virtual potential so that the plus-side potential and the minus-side potential of the transmission line pair become predetermined potentials, respectively, and according to the minus-side virtual potential A differential driver circuit comprising a feedback circuit for controlling the second current source transistor.
The differential driver circuit according to claim 1.
The replica termination resistor has a resistance value n times (n> 1) the resistance value of the termination resistor, and each of the plurality of replica transistors is n times the on-resistance value of each of the plurality of output switch transistors. A differential driver circuit characterized by having an on-resistance value.
The differential driver circuit according to claim 1.
The feedback circuit includes:
A first differential amplifier circuit that controls the first current source transistor so that the plus-side virtual potential is equal to a first reference potential;
A differential driver circuit comprising: a second differential amplifier circuit that controls the second current source transistor so that the negative virtual potential is equal to a second reference potential.
The differential driver circuit according to claim 1.
The driver body further includes a plurality of protective resistors connected in series to the plurality of output switch transistors,
The replica circuit further includes a plurality of replica protection resistors connected in series to the plurality of replica transistors,
The replica termination resistor has a resistance value that is n times (n> 1) the resistance value of the termination resistor, and each of the plurality of replica protection resistors has a resistance value that is n times the resistance value of each of the plurality of protection resistors. And each of the plurality of replica transistors has an on-resistance value that is n times the on-resistance value of each of the plurality of output switch transistors.
The differential driver circuit according to claim 1.
A first AC impedance circuit formed by connecting a resistor and a capacitor in series, inserted between a connection point between the first current source transistor and any of the plurality of output switch transistors, and a power supply or a ground;
A second AC impedance circuit formed by connecting a resistor and a capacitor connected in series between a connection point between the second current source transistor and one of the plurality of output switch transistors and a power supply or a ground; A differential driver circuit further comprising the differential driver circuit.