CN116488596A - LVDS receiving circuit with wide input common mode range and chip - Google Patents
LVDS receiving circuit with wide input common mode range and chip Download PDFInfo
- Publication number
- CN116488596A CN116488596A CN202310060754.5A CN202310060754A CN116488596A CN 116488596 A CN116488596 A CN 116488596A CN 202310060754 A CN202310060754 A CN 202310060754A CN 116488596 A CN116488596 A CN 116488596A
- Authority
- CN
- China
- Prior art keywords
- transistor
- input
- transistors
- common mode
- drain
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000008859 change Effects 0.000 claims abstract description 20
- 230000011664 signaling Effects 0.000 claims abstract description 5
- 238000000034 method Methods 0.000 claims description 10
- 230000001105 regulatory effect Effects 0.000 claims description 7
- 230000003321 amplification Effects 0.000 claims description 6
- 230000001276 controlling effect Effects 0.000 claims description 6
- 238000003199 nucleic acid amplification method Methods 0.000 claims description 6
- 238000007493 shaping process Methods 0.000 claims description 5
- 229910044991 metal oxide Inorganic materials 0.000 claims description 4
- 150000004706 metal oxides Chemical class 0.000 claims description 4
- 239000004065 semiconductor Substances 0.000 claims description 4
- 238000012545 processing Methods 0.000 abstract description 2
- 238000010586 diagram Methods 0.000 description 5
- 238000005259 measurement Methods 0.000 description 4
- 230000005540 biological transmission Effects 0.000 description 3
- 230000008569 process Effects 0.000 description 2
- 230000004075 alteration Effects 0.000 description 1
- 238000013459 approach Methods 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005670 electromagnetic radiation Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000036039 immunity Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000008092 positive effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/45—Differential amplifiers
- H03F3/45071—Differential amplifiers with semiconductor devices only
- H03F3/45479—Differential amplifiers with semiconductor devices only characterised by the way of common mode signal rejection
- H03F3/45632—Differential amplifiers with semiconductor devices only characterised by the way of common mode signal rejection in differential amplifiers with FET transistors as the active amplifying circuit
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/30—Modifications of amplifiers to reduce influence of variations of temperature or supply voltage or other physical parameters
- H03F1/301—Modifications of amplifiers to reduce influence of variations of temperature or supply voltage or other physical parameters in MOSFET amplifiers
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
- H04B1/06—Receivers
- H04B1/16—Circuits
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Logic Circuits (AREA)
Abstract
The invention discloses a Low Voltage Differential Signaling (LVDS) receiving circuit and a chip with wide input common mode range, and relates to the technical field of data processing circuits. The input stage of the LVDS receiving circuit comprises a first-stage input end and a second-stage input end, two groups of PMOS tube input differential pairs, a level shift module, a PMOS transistor PM5 serving as a switch, a reference voltage module and a bias circuit module; the bias circuit module is used for providing bias current I0 and control configuration thereof, and is used for reducing output bias current I0 when the input common mode level is at the middle level or near the reference voltage so as to compensate the increase of circuit transconductance Gm when the two groups of PMOS tube input differential pairs work simultaneously. The invention not only can realize the input common mode range from the rail to the rail under the low power supply voltage, but also has smaller change along with the common mode of the circuit transconductance Gm, thereby obviously reducing the influence of the change of the input common mode on the speed, the gain, the hysteresis and the like of the circuit.
Description
Technical Field
The present invention relates to the field of data processing circuits, and in particular, to an LVDS receiving circuit and chip with a wide input common mode range.
Background
Low-voltage differential signaling (LVDS) transmission technology was proposed in the 1990 s, which can achieve higher transmission speed, lower electromagnetic radiation interference, better noise immunity and greatly reduced power consumption by adopting differential small-swing signaling to transmit data, and thus is widely used in various communication systems.
The LDVS data transmission system includes an LDVS transmitting circuit and an LDVS receiving circuit, and according to the standard of the current LVDS protocol, the input common mode range of the LVDS receiving circuit needs to be wide enough (must be significantly larger than the common mode range of the LDVS transmitting circuit) for robust operation, and especially when the power supply voltage of the receiving end is low, it is desirable that the input common mode range of the LVDS receiving circuit can reach a voltage range close to a rail-to-rail voltage range, taking into consideration the ground voltage difference between the transmitting end and the receiving end, direct coupling interference, transmitting end interference, and the like. By way of example, fig. 1 illustrates a prior art LVDS receiver circuit, where PMOS transistors PM1 and PM2 form a differential input pair, and according to the positive and negative magnitudes of the differential input (VP-VN) which represents a positive signal, VN represents a negative signal, the differential input signal is equal to VP-VN), the magnitude of the constant source current IBIAS flowing to the drains of PM1 and PM2 is adjusted, and NMOS transistors NM1, NM2, NM3, NM4 form a diode load with positive feedback in combination to achieve signal amplification and required hysteresis, and further signal amplification and differential to single-ended output VOUT are achieved through the output stage formed by NM5, NM6 and PM3, PM 4. However, this structure cannot realize a wide input common mode range, assuming that the absolute values of the gate-source voltages of PM1 and PM2 are |v GS The overdrive voltage required for a constant source current IBIAS is V DSAT,IBIAS Then input common mode level V CM,IN = (vp+vn)/2 should be smaller than VDD-V DSAT , IBIAS -|V GS When the power supply voltage VDD is low, it is difficult to satisfy the standard range required by the LVDS protocol.
To achieve a near rail-to-rail input common mode range, typical LVDS receive circuit input stages today typically use a combination of PMOS (Positive channel Metal Oxide Semiconductor) and NMOS (Negative channel Metal Oxide Semiconductor) differential pairs: when the input common mode level is lower, the PMOS tube differential pair works; when the input common mode level is higher, the NMOS tube differential pair works; when the input common mode level is at the intermediate level, the PMOS tube differential pair and the NMOS tube differential pair work simultaneously. Referring to fig. 2, a conventional LVDS receiver circuit for implementing a common-mode range of a rail-to-rail input is illustrated, and the scheme uses PMOS differential input pairs PM1 and PM2 and NMOS differential input pairs NM1 and NM2 in a mixed manner to form a folded operational amplifier, so as to expand the input common-mode range. When the input common mode level is low, the PMOS differential input pair PM1 and PM2 works; when the input common mode level is higher, the NMOS differential input pair NM1 and NM2 works; when the input common mode level is at the intermediate level, the PMOS input differential pair PM1, PM2 and the NMOS input differential pair NM1, NM2 operate simultaneously. However, this working mode may cause significant changes of the total transconductance Gm, bias current, etc. of the circuit along with the input common mode, resulting in larger circuit delay and smaller gain in some cases, and because the gain of the input stage varies greatly along with the process, temperature, and supply voltage, it is difficult to implement stable hysteresis voltage.
Accordingly, the prior art also provides schemes for extending the input common mode range by adding level shifting, such as the input stage for LVDS receiver circuits disclosed in chinese patent application CN 201880065454.3: the power supply circuit comprises at least one power supply voltage connection end, a first-stage input end and a second-stage input end, wherein the first-stage input end and the second-stage input end are used for applying differential input signal pairs; the input stage further comprises a first differential stage and a second differential stage, wherein the stage input ends are respectively and directly connected with the input ends of the first differential stage, and respectively and indirectly connected with the input ends of the second differential stage through level shifting circuits; the input stage further comprises two stage outputs, each of which has a connection consisting of one output of each of the first differential stage and the second differential stage; the first differential stage and the second differential stage are each connected to a supply voltage connection via a transistor of the third differential stage, wherein the control input of one of the transistors is connected to a measurement path which connects the stage inputs to one another and the control input of the other transistor is connected to a supply voltage. The core of the scheme is that: expansion of common mode input range is achieved by using two sets of input differential pairs and a level shifting circuit that reduces the input common mode level, while setting a third set of differential pairs, a first set of differential pairs and a second set of differential pairs The transistors of the third differential pair are connected to the supply voltage connection, respectively, the control input of one transistor of the third differential pair is connected to the reference voltage, the control input of the other transistor of the third differential pair is connected to the measurement path (which may be a series circuit of two identical resistors, see measurement path 20 of resistors 32, 33 in fig. 3) which connects the two stage inputs to each other, the reference voltage being V REF Connecting the input VP (positive signal) and VN (negative signal) via two identical resistors of the measurement path, wherein the potential at the junction of the two resistors is the input common mode level V CM,IN = (vp+vn)/2, the other transistor in the third differential pair is connected to the junction of R1, R2; by comparing the reference voltages V REF Common mode level V with the input CM,IN To adjust how much constant source current flows to the drains of the two transistors in the third differential pair; the input stage has the advantages of maximizing the allowable common mode range, simultaneously having fixed bias current (i.e. not changing along with the change of the input common mode), being easy to integrate hysteresis function, eliminating the correlation between current consumption and the common mode, and reducing the correlation between circuit parameters such as hysteresis, delay time and the like and the common mode. However, the above solution still has the disadvantage that the total transconductance Gm of the circuit varies greatly with the common mode (especially when the two transistors of the first differential pair and the two transistors of the second differential pair operate simultaneously, the total transconductance Gm of the circuit increases relatively significantly), resulting in significant variations in speed, gain, hysteresis, etc. of the circuit with the common mode.
In summary, how to provide an LVDS receiving circuit capable of realizing an input common mode range close to rail-to-rail at a low power supply voltage and having a small circuit transconductance Gm with a small common mode variation is a technical problem to be solved currently.
Disclosure of Invention
The invention aims at: overcomes the defects of the prior art and provides an LVDS receiving circuit and a chip with wide input common mode range. The LVDS receiving circuit with the wide input common mode range provided by the invention not only can realize the input common mode range close to the rail-to-rail under the low power supply voltage, but also has smaller circuit transconductance Gm along with the common mode change, so that the speed, gain, hysteresis and the like of the circuit along with the common mode change are smaller, and the influence of the input common mode change on the speed, gain, hysteresis and the like of the circuit is obviously reduced.
In order to achieve the above object, the present invention provides the following technical solutions:
the Low Voltage Differential Signaling (LVDS) receiving circuit with a wide input common mode range comprises an input stage, wherein the input stage comprises a first stage input end, a second stage input end, a first group of PMOS (P-channel metal oxide semiconductor) tube input differential pairs, a second group of PMOS tube input differential pairs and a level shifting module; the first-stage input end and the second-stage input end are used for applying differential input signal pairs VP and VN, and the differential input signal pairs VP and VN are respectively and directly connected with the grid electrodes of two transistors of the second group of PMOS tube input differential pairs and are used for controlling leakage currents of the two transistors; the differential input signal pair VP and VN are also indirectly connected with the grid electrodes of the two transistors of the first group of PMOS tube input differential pair through a level shifting module respectively and used for controlling leakage currents of the two transistors; the level shift module is used for reducing the input common mode level;
The input stage further comprises a PMOS transistor PM5 serving as a switch, a reference voltage module, and a bias circuit module;
the drain electrode of the transistor PM5 is connected with the source electrodes of the two transistors of the first group of PMOS transistor input differential pairs to a first node, the source electrodes of the transistor PM5 and the source electrodes of the two transistors of the second group of PMOS transistor input differential pairs are connected to a second node, and the grid electrode of the transistor PM5 is connected with a reference voltage module;
the reference voltage module provides a reference voltage V REF To the transistors PM5, V REF As the gate voltage of the transistor PM 5;
the bias circuit module is used for providing bias current I0 of the input stage and performing control configuration of the bias current; wherein the bias circuit module is configured to: in the case of determining that the input common mode level is at the intermediate level or that the input common mode level is at the reference voltage V REF When the difference value of the output voltage is within the preset range, the bias power of the output is regulated downFlow I0 such that the bias current I0 flowing to the aforementioned first and second nodes decreases.
Further, the bias current I0 output by the bias circuit module and the input common mode level V CM,IN In relation, the input common mode level V CM,IN = (vp+vn)/2, VP represents the positive side signal, VN represents the negative side signal;
The bias current I0 and the input common mode level V CM,IN The relation expression of (a) is I0=I Fixing +f(V CM,IN ) Wherein I is Fixing And input common mode level V CM,IN Irrespective of f (V) CM,IN ) Representing and inputting common mode level V CM,IN A related function;
configuration f (V) CM,IN ) The weight duty ratio of the relation expression is expressed in the aforesaid way to reduce the input common mode level V CM,IN Influence on bias current I0; wherein, in configuration f (V CM,IN ) When a function is inputted a common mode level V CM,IN When the difference between the power supply voltage and the ground voltage is within the preset range, let f (V CM,IN ) =0; when the power voltage is equal to the reference voltage V REF When the difference of (2) is within the preset range, let f (V CM,IN ) Is a preset negative value.
Further, the bias circuit module comprises a comparison unit and a bias current I0 control unit;
the comparing unit is configured to: comparing the input common mode level with the reference voltage V REF The power supply voltage and the ground voltage, and sends the comparison result to a bias current I0 control unit;
the bias current I0 control unit is configured to: acquiring the comparison result, when the difference value between the input common mode level and the ground voltage is within a preset range, judging that the input common mode level is close to the ground voltage, and the transistor PM5 is in an off state, wherein bias current I0 completely flows to the second node, and at the moment, the two transistors PM3 and PM4 of the second group of PMOS tube input differential pairs work; the method comprises the steps of,
When the difference value between the input common mode level and the power supply voltage is within a preset range, the input common mode level is judged to be close to the power supply voltage, two transistors of the second group of PMOS tube input differential pairs are turned off, bias current I0 mainly flows to the source electrode of the transistor PM5, at the moment, the two transistors PM1 and PM2 of the first group of PMOS tube input differential pairs work, and the direct current level of the differential input signal pairs VP and VN is reduced through a level shifting module; the method comprises the steps of,
when the common mode level and the reference voltage V are input REF When the difference value of (2) is within the preset range, determining that the common mode level is at the reference voltage V REF Near, bias current I0 flows to the first node and the second node at the same time, and at the moment, two transistors of the first group of PMOS tube input differential pairs and two transistors of the second group of PMOS tube input differential pairs work at the same time; and regulating the output bias current I0 down so that the bias current I0 flowing to the input differential pair of the two groups of PMOS tubes is reduced.
Further, the bias circuit module includes PMOS transistors PM0, PM8, PM9, PM10, and PM11, NMOS transistors NM1, NM2, and NM3, and two resistors R3 and R4 having equal resistance values;
the drain electrode of the transistor PM0 is connected with the source electrodes of the transistors PM3 and PM4 of the second group of PMOS tube input differential pairs, and bias current I0 is provided for the input stage; the source of the transistor PM0 is connected with the power supply voltage VDD; the gate of the transistor PM0 is connected to the gate and the drain of the transistor PM8, while being connected to the drain of the transistor NM1, and while being connected to the drain of the transistor PM 9; transistors PM0 and PM8 constitute a current mirror; the sources of the transistors PM8 and PM9 are connected with a power supply voltage VDD;
The gate of the transistor NM1 is connected with a bias voltage V BIAS Source electrode ground voltage VSS, is used for forming the current source;
the grid electrode of the transistor PM9 is connected with the grid electrode and the drain electrode of the transistor PM10, and the transistors PM9 and PM10 form a current mirror; the source of the transistor PM10 is connected with the power supply voltage VDD, the drain of the transistor PM10 is also connected with the source of the transistor PM11, the drain of the transistor PM11 is connected with the drain of the transistor NM2, the source of the transistor NM2 is simultaneously connected with the drain and the gate of the transistor NM3, and the source of the transistor NM3 is grounded at the voltage VSS; the gates of the transistor PM11 and the transistor NM2 are connected with the connection part of the resistors R3 and R4, the other end of the resistor R3 is connected with the input positive end signal VP of the receiving circuit, the other end of the resistor R4 is connected with the input negative end signal VN of the receiving circuit, and the potential of the connection part of the resistors R3 and R4 isInput common mode level V CM,IN 。
Further, let the ratio of the width to length ratio of the transistor PM0 to the transistor PM8 be m, and the ratio of the width to length ratio of the transistor PM9 to the transistor PM10 be 1, the bias current i0=mχi provided by the transistor PM0 NM1 -m*I PM10 Wherein I NM1 Represents the current, m.times.I, of the transistor NM1 NM1 Is a fixed part and does not follow the input common mode level V CM,IN A change; i PM10 Represents the current, m.times.I, of the transistor PM10 PM10 As a variable part, with input common mode level V CM,IN A change by change;
when the input common mode level is higher than or lower than the preset threshold, the transistor PM11 or NM2 is turned off, at which time I PM10 Bias current i0=m×i NM1 The method comprises the steps of carrying out a first treatment on the surface of the When the input common mode level is at the intermediate level or at the reference voltage V REF In the vicinity, the bias circuit module turns on the transistors PM11 and NM2 by adjusting the size of the transistors PM11, NM2, and NM3 so that I PM10 >And 0 to reduce the bias voltage I0, so as to compensate the increase of the total transconductance Gm of the circuit caused by the simultaneous operation of the first group of PMOS tube input differential pairs PM1 and PM2 and the second group of PMOS tube input differential pairs PM3 and PM 4.
Further, the input stage further comprises a load module;
the drain electrode of one transistor in the first PMOS tube input differential pair and the drain electrode of one transistor in the second PMOS tube input differential pair are connected to the negative end output VON1 of the input stage, and the drain electrode of the other transistor in the first PMOS tube input differential pair and the drain electrode of the other transistor in the second PMOS tube input differential pair are connected to the positive end output VOP1 of the input stage; the load module is connected with the VOP1 and the VON1 and used for primary amplification of signals and generating an input common mode level of a rear-stage circuit;
the load module comprises two grounding resistors R1 and R2 with equal resistance values, one end of the resistor R1 is grounded, the other end of the resistor R2 is grounded, and the other end of the resistor R is grounded.
Further, the output signal VOD comprises a comparator module positioned behind the input stage, the VOP1 and the VON1 are respectively connected to the positive end input and the negative end input of the comparator module, and the VOP1 and the VON1 signals are amplified and/or shaped through the comparator module to obtain the output signal VOUT.
Further, the comparator module includes PMOS transistors PM12, PM13, and PM14, NMOS transistors NM6, NM7, NM8, and NM9, and an output stage;
transistors PM13 and PM14 as an input differential pair, the gates of which are connected to VOP1 and VON1 signals, respectively, the sources of transistors PM13 and PM14 being connected, and simultaneously, to the drain of transistor PM 12; the gate of the transistor PM12 is connected to the second bias voltage V BIAS2 The source electrode is connected with a power supply V DDCORE Providing bias current for transistors PM13 and PM 14;
the drain of the transistor PM13 is connected to the drain and gate of the transistor NM8, simultaneously to the drain of the transistor NM6, simultaneously to the gate of the transistor NM7, simultaneously to the negative input terminal of the output stage; the drain of the transistor PM14 is connected to the drain and gate of the transistor NM9, and simultaneously to the drain of the transistor NM7, and simultaneously to the gate of the transistor NM6, and simultaneously to the input positive terminal of the output stage;
transistors NM6, NM7, NM8 and NM9 form a diode load with positive feedback for realizing hysteresis;
The output stage is used for amplifying, differentiating, converting to single end and/or shaping the signal and outputting the signal VOUT.
Further, the level shift module includes NMOS transistors NM4 and NM5, and NMOS transistors NM16 and NM17; the gates of the transistors NM16 and NM17 are respectively connected to the differential input signal pair VP and VN, the sources of the transistors NM16 and NM17 are respectively connected to the gates of the transistors PM1 and PM2, and are respectively connected to the drains of the transistors NM4 and NM5, and the drains of the transistors NM16 and NM17 are both connected to the power supply voltage VDD; the gates of the transistors NM4 and NM5 are connected to a first bias voltage V BIAS1 The sources of the transistors NM4 and NM5 are both connected to the ground voltage VSS, and the transistors NM4 and NM5 are used for the role of current sources;
and/or the reference voltage module comprises a PMOS transistor PM15 and an NMOS transistor NM10, wherein the source electrode of the transistor NM10 is grounded to the voltage VSS, and the grid electrode of the transistor NM10 is connected to the first bias voltage V BIAS1 The transistor NM10 is used for the role of a current source; meanwhile, the drain of the transistor NM10 is connected to the gate and drain of the transistor PM15, the source of the transistor PM15 is connected to the power supply voltage VDD, and the drain output of the transistor NM10 provides the gate voltage V for the transistor PM5 REF 。
The invention also provides a chip, and a receiver capable of converting LVDS signals is integrated on the chip, and comprises the LVDS receiving circuit.
Compared with the prior art, the invention has the following advantages and positive effects by taking the technical scheme as an example: the LVDS receiving circuit with a wide input common mode range not only can realize the input common mode range close to the rail-to-rail under low power supply voltage, but also has smaller circuit transconductance Gm along with the common mode change, so that the speed, gain, hysteresis and the like of the circuit along with the common mode change are smaller, and the influence of the input common mode change on the speed, gain, hysteresis and the like of the circuit is obviously reduced.
Drawings
Fig. 1 is a schematic diagram of a LVDS receiver circuit in the prior art.
Fig. 2 is a schematic diagram of a structure of an LVDS receiver circuit for implementing a common mode range of a rail-to-rail input according to the prior art.
Fig. 3 is an input stage block diagram of another LVDS receiver circuit implementing a near rail-to-rail input common mode range provided in the prior art.
Fig. 4 is a schematic structural diagram of an LVDS receiving circuit with a wide input common mode range according to the present invention.
Fig. 5 is a schematic circuit diagram of each module of the LVDS receiving circuit provided by the present invention.
Reference numerals illustrate:
a level shift module 10;
a reference voltage module 20;
a bias circuit module 30;
A load module 40;
a comparator module 50.
Detailed Description
The wide input common mode range LVDS receiving circuit and the chip disclosed in the present invention are further described in detail below with reference to the accompanying drawings and specific embodiments. It should be noted that the technical features or combinations of technical features described in the following embodiments should not be regarded as being isolated, and they may be combined with each other to achieve a better technical effect. In the drawings of the embodiments described below, like reference numerals appearing in the various drawings represent like features or components and are applicable to the various embodiments. Thus, once an item is defined in one drawing, no further discussion thereof is required in subsequent drawings.
It should be noted that the structures, proportions, sizes, etc. shown in the drawings are merely used in conjunction with the disclosure of the present specification, and are not intended to limit the applicable scope of the present invention, but rather to limit the scope of the present invention. The scope of the preferred embodiments of the present invention includes additional implementations in which functions may be performed out of the order described or discussed, including in a substantially simultaneous manner or in an order that is reverse, depending on the function involved, as would be understood by those of skill in the art to which embodiments of the present invention pertain.
Techniques, methods, and apparatus known to one of ordinary skill in the relevant art may not be discussed in detail, but are intended to be part of the specification where appropriate. In all examples shown and discussed herein, any specific values should be construed as merely illustrative, and not a limitation. Thus, other examples of the exemplary embodiments may have different values.
Examples
Referring to fig. 4, an LVDS receiving circuit with a wide input common mode range is provided in this embodiment.
The LVDS receiving circuit comprises an input stage and a comparator module positioned behind the input stage.
The input stage includes: the circuit comprises a first-stage input end and a second-stage input end, a first group of PMOS tube input differential pairs PM1 and PM2 and a second group of PMOS tube input differential pairs PM3 and PM4, a level shift circuit module, a PMOS transistor PM5 used as a switch, a reference voltage module for providing grid voltage for the transistor PM5, a bias circuit module and a load module.
The first stage input and the second stage input are used to apply differential input signal pairs VP (positive side signal) and VN (negative side signal).
The differential input signal pair VP and VN are respectively and directly connected to the gates of the two transistors PM3 and PM4 of the second PMOS transistor input differential pair, so as to control the leakage currents of the two transistors PM3 and PM 4. Meanwhile, the differential input signal pair VP and VN are also indirectly connected to the gates of the two transistors PM1 and PM2 of the first group of PMOS transistor input differential pair through the level shift circuit module, respectively, for leakage currents of the two transistors PM1 and PM 2.
The level shifting module is used for reducing the input common mode level.
The drain of the transistor PM5 is connected to the first node with the sources of the two transistors PM1 and PM2 of the first PMOS transistor input differential pair, see point a in fig. 4; meanwhile, the source electrode of the transistor PM5 and the source electrodes of the two transistors PM3 and PM4 of the second group of PMOS transistor input differential pairs are connected to a second node, see point B in fig. 4; and, the gate of the transistor PM5 is connected with a reference voltage module.
The reference voltage module provides a reference voltage V REF To the transistors PM5, V REF As the gate voltage of the transistor PM 5.
The bias circuit module is used for providing bias current I0 of the input stage and performing control configuration of the bias current, and is used for realizing the bias current and control thereof in FIG. 4. Specifically, the bias circuit module is configured to: in the case of determining that the input common mode level is at the intermediate level or that the input common mode level is at the reference voltage V REF When the difference value of the first and second nodes is within the preset range, the output bias current I0 is regulated down, so that the bias current I0 flowing to the first and second nodes is reduced.
The load module is connected with the positive end output VOP1 and the negative end output VON1 of the input stage and is used for primary amplification of signals and generation of input common mode level of a later-stage circuit. Specifically, the drain electrode of one transistor in the first group of PMOS transistor input differential pair and the drain electrode of one transistor in the second group of PMOS transistor input differential pair are connected to the negative end output VON1 of the input stage, and the drain electrode of the other transistor in the first group of PMOS transistor input differential pair and the drain electrode of the other transistor in the second group of PMOS transistor input differential pair are connected to the positive end output VOP1 of the input stage; the load module is connected with the VOP1 and the VON1 for primary amplification of signals and generating input common mode level of a subsequent circuit.
The comparator module is connected with the positive end output VOP1 and the negative end output VON1 of the input stage and is used for amplifying and/or shaping signals so as to obtain an output signal VOUT.
In this embodiment, the bias current I0 output by the bias circuit module and the input common mode level V CM,IN In relation, the input common mode level V CM,IN = (vp+vn)/2, VP represents the positive side signal, VN represents the negative side signal. That is, the value of the bias current I0 is subjected to the input common mode level V CM,IN Influence of = (vp+vn)/2.
Specifically, the output bias current I0 is the input common mode level V CM,IN Is expressed as i0=i Fixing +f(V CM,IN ) Wherein I is Fixing And input common mode level V CM,IN Irrespective of f (V) CM,IN ) Representing and inputting common mode level V CM,IN A function of the correlation. In connection with the example of FIG. 4, the I Fixing =I B I.e. the fixed part of the bias current I0 is equal to the B-point current value I B 。
Configuration f (V) CM,IN ) In the above relation formula i0=i Fixing +f(V CM,IN ) To reduce the input common mode level V CM,IN Influence on the bias current I0. Thus, f (V) CM,IN ) The weight in the configuration current is relatively small, thereby reducing the degree to which the bias current varies with the input common mode level.
Wherein, in the configuration of f%V CM,IN ) When a function is inputted a common mode level V CM,IN When the difference between the input common mode level and the power supply voltage or the ground voltage is within a preset range, namely when the input common mode level is close to the power supply voltage and the ground voltage, f (V CM,IN ) =0; when the power voltage is equal to the reference voltage V REF When the difference of (2) is within the preset range, i.e. when the supply voltage is close to V REF When in the vicinity, let f (V CM,IN ) Is a preset negative value, thereby reducing the bias current I0.
In this embodiment, the bias circuit module may specifically include a comparing unit and a bias current I0 control unit.
The comparing unit is configured to: comparing the input common mode level with the reference voltage V REF The power supply voltage and the ground voltage, and sends the comparison result to the bias current I0 control unit.
The bias current I0 control unit is configured to: acquiring the comparison result, when the difference value between the input common mode level and the ground voltage is within a preset range, judging that the input common mode level is close to the ground voltage, and the transistor PM5 is in an off state, wherein bias current I0 completely flows to the second node, and at the moment, the two transistors PM3 and PM4 of the second group of PMOS tube input differential pairs work; when the difference value between the input common mode level and the power supply voltage is within a preset range, the input common mode level is judged to be close to the power supply voltage, two transistors of the input differential pair of the second group of PMOS tubes are turned off, bias current I0 mainly flows to the source electrode of the transistor PM5, at the moment, the two transistors PM1 and PM2 of the input differential pair of the first group of PMOS tubes work, and the direct current level of the differential input signal pairs VP and VN is reduced through a level shifting module; and when the common mode level and the reference voltage V are input REF When the difference value of (2) is within the preset range, determining that the common mode level is at the reference voltage V REF Near, bias current I0 flows to the first node and the second node at the same time, and at the moment, two transistors of the first group of PMOS tube input differential pairs and two transistors of the second group of PMOS tube input differential pairs work at the same time; and regulating the output bias current I0 down so that the bias current I0 flowing to the input differential pair of the two groups of PMOS tubes is reduced.
LVDS reception as shown in connection with FIG. 4The device circuit is used for understanding: when the input common mode level is close to the ground voltage, the voltage at the point B is lower, the transistor PM5 is in an off state, the bias current I0 output by the bias circuit module completely flows to the point B, at the moment, the two transistors PM3 and PM4 of the second group of PMOS tube input differential pairs work, and the input signals are amplified and shaped through a load and a comparator circuit at a later stage to obtain an output signal VOUT. When the input common mode level approaches to the power supply voltage, the two transistors PM3 and PM4 of the second group of PMOS input differential pair are turned off, the voltage at the point B is higher, the bias current I0 mainly flows to the source of the transistor PM5, at this time, the level shift circuit will reduce the dc level of the differential input signal pair VP and VN, the two transistors PM1 and PM2 of the first group of PMOS input differential pair work, and the input signal is amplified and shaped by the load and the comparator circuit at the later stage to obtain the output signal VOUT. When the input common mode level is at the reference voltage V REF When the bias current I0 flows to the point A and the point B simultaneously, the two transistors PM1 and PM2 of the first group of PMOS tube input differential pairs and the two transistors PM3 and PM4 of the second group of PMOS tube input differential pairs work simultaneously, at the moment, the bias circuit module can reduce the output bias current I0, and then the input signals are amplified through the load module and the comparator circuit of the later stage, and the output VOUT is obtained through shaping. The bias current I0 output by the circuit is regulated down, so that the increase of the total transconductance Gm of the circuit caused by the simultaneous operation of the two groups of PMOS tube input differential pairs PM1, PM2, PM3 and PM4 can be compensated, the change of the transconductance Gm of the circuit along with the common mode is smaller, the change of the speed, gain, hysteresis and the like of the circuit along with the common mode is also smaller, and the working stability of the circuit is improved.
As a typical preferred mode, referring to fig. 5, the bias circuit module may specifically include PMOS transistors PM0, PM8, PM9, PM10, and PM11, NMOS transistors NM1, NM2, and NM3, and two resistors R3 and R4 having equal resistance values.
The drain electrode of the transistor PM0 is connected with the source electrodes of the transistors PM3 and PM4 of the second group of PMOS tube input differential pairs, and bias current I0 is provided for the input stage; the source of the transistor PM0 is connected with the power supply voltage VDD; the gate of the transistor PM0 is connected to the gate and the drain of the transistor PM8, while being connected to the drain of the transistor NM1, and while being connected to the drain of the transistor PM 9; transistors PM0 and PM8 constitute a current mirror; the sources of the transistors PM8 and PM9 are connected to the power supply voltage VDD.
The gate of the transistor NM1 is connected with a bias voltage V BIAS The source ground voltage VSS is used to construct a current source.
The gate of the transistor PM9 is connected to the gate and drain of the transistor PM10, and the transistors PM9 and PM10 constitute a current mirror. The source of the transistor PM10 is connected to the power supply voltage VDD, the drain of the transistor PM10 is also connected to the source of the transistor PM11, the drain of the transistor PM11 is connected to the drain of the transistor NM2, the source of the transistor NM2 is simultaneously connected to the drain and the gate of the transistor NM3, and the source of the transistor NM3 is grounded to the voltage VSS.
The gates of the transistor PM11 and the transistor NM2 are connected with the connection part of the resistors R3 and R4, the other end of the resistor R3 is connected with the input positive end signal VP of the receiving circuit, the other end of the resistor R4 is connected with the input negative end signal VN of the receiving circuit, and the potential of the connection part of the resistors R3 and R4 is the input common mode level V CM,IN 。
The adjusting and controlling process of the bias circuit module is as follows: let the ratio of the width to length ratio of the transistor PM0 to the transistor PM8 be m, and the ratio of the width to length ratio of the transistor PM9 to the transistor PM10 be 1.
Bias current i0=i provided by transistor PM0 PM0 =m*I PM8 =m*(I NM1 -I PM9 )=m*I NM1 -m*I PM9 = m*I NM1 -m*I PM10 Wherein I PM0 Representing the current of transistor PM0, I PM8 Representing the current of transistor PM8, I PM9 Representing the current of transistor PM9, I PM10 Representing the current of transistor PM10, I NM1 A current representing the transistor NM 1; m is I NM1 Is a fixed part and does not follow the input common mode level V CM,IN A change; m is I PM10 As a variable part, with input common mode level V CM,IN And changes from variation to variation.
When the input common mode level is higher than or lower than the preset threshold, i.e. when the input common mode level is higher or lower, the transistor PM11 or the transistor NM2 is turned off, at which time I PM10 Bias current i0=m×i NM1 Is thatA fixed value; when the input common mode level is at the intermediate level or at the reference voltage V REF In the vicinity, the bias circuit module can adjust the sizes of the transistors PM11, NM2 and NM3 to make the transistors PM11 and NM2 conductive, at the moment I PM10 >0, can obtain i0=mi NM1 -m*I NM10 Less than m.times.I NM1 Namely, the bias voltage I0 is reduced, so as to compensate the increase of the total transconductance Gm of the circuit caused by the simultaneous operation of the first group of PMOS input differential pairs PM1 and PM2 and the second group of PMOS input differential pairs PM3 and PM 4.
With continued reference to fig. 5, for the preferred embodiment of each module in the LVDS receiving circuit provided by the present invention, the circuit composition of the level shifting module 10, the reference voltage module 20, and the load module 40 and the comparator module 50 is also illustrated.
The level shift module 10 may specifically include NMOS transistors NM4, NM5 and NMOS transistors NM16, NM17. The gates of the transistors NM16 and NM17 are respectively connected to the differential input signal pair VP and VN, the sources of the transistors NM16 and NM17 are respectively connected to the gates of the transistors PM1 and PM2, and are also respectively connected to the drains of the transistors NM4 and NM5, and the drains of the transistors NM16 and NM17 are both connected to the power supply voltage VDD; the gates of the transistors NM4 and NM5 are connected to a first bias voltage V BIAS1 The sources of the transistors NM4 and NM5 are both connected to the ground voltage VSS, and the transistors NM4 and NM5 are used for the role of a current source.
The reference voltage module 20 may specifically include a PMOS transistor PM15 and an NMOS transistor NM10. The source electrode of the transistor NM10 is grounded to the voltage VSS, and the gate electrode is connected to the first bias voltage V BIAS1 The transistor NM10 is used for the role of a current source; meanwhile, the drain of the transistor NM10 is connected to the gate and drain of the transistor PM15, the source of the transistor PM15 is connected to the power supply voltage VDD, and the drain output of the transistor NM10 provides the gate voltage V for the transistor PM5 REF 。
The load module 40 may specifically include two resistors R1 and R2 with equal resistance values; one end of the resistor R1 is grounded, and the other end of the resistor R1 is connected with VON1; resistor R2 has one end connected to ground and the other end connected to VOP1.
The latter comparator block 50 has a hysteresis function and may include PMOS transistors PM12, PM13, PM14, NMOS transistors NM6, NM7, NM8, NM9, and an output stage.
Transistors PM13 and PM14 as an input differential pair, the gates of which are connected to VOP1 and VON1 signals, respectively, the sources of transistors PM13 and PM14 being connected, and simultaneously, to the drain of transistor PM 12; the gate of the transistor PM12 is connected to the second bias voltage V BIAS2 The source electrode is connected with a power supply V DDCORE Bias current is provided to transistors PM13 and PM 14.
The drain of the transistor PM13 is connected to the drain and gate of the transistor NM8, simultaneously to the drain of the transistor NM6, simultaneously to the gate of the transistor NM7, simultaneously to the negative input terminal of the output stage; the drain of the transistor PM14 is connected to the drain and gate of the transistor NM9, and simultaneously to the drain of the transistor NM7, and simultaneously to the gate of the transistor NM6, and simultaneously to the input positive of the output stage.
Transistors NM6, NM7, NM8 and NM9 constitute a diode load with positive feedback for implementing hysteresis.
The output stage is used for amplifying, differentiating, converting to single end and/or shaping the signal and outputting the signal VOUT.
According to the LVDS receiving circuit with the input common mode range, on one hand, the input differential pair, the level shifting module, the PMOS transistor serving as a switching function and the reference voltage module can be used for realizing the range from the input common mode level of the circuit to the rail through the two groups of PMOS transistors under the low power supply voltage; on the other hand, the bias circuit module is used for adjusting and controlling bias current to compensate the increase of the total transconductance Gm of the circuit caused by the simultaneous operation of the transistor pairs of the input difference of the two groups of PMOS tubes, so that the change of the transconductance Gm of the circuit along with the common mode is smaller, the influence of the change of the input common mode on the speed, the gain, the hysteresis and the like of the circuit is reduced, and the working stability of the circuit is improved.
In another embodiment of the present invention, a chip is further provided, and a receiver capable of converting LVDS signals is integrated on the chip, where the receiver includes the LVDS receiving circuit.
Other technical features are described in the previous embodiments and are not described in detail here.
In the above description, the disclosure of the present invention is not intended to limit itself to these aspects. Rather, the components may be selectively and operatively combined in any number within the scope of the present disclosure. In addition, terms like "comprising," "including," and "having" should be construed by default as inclusive or open-ended, rather than exclusive or closed-ended, unless expressly defined to the contrary. All technical, scientific, or other terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. Common terms found in dictionaries should not be too idealized or too unrealistically interpreted in the context of the relevant technical document unless the present disclosure explicitly defines them as such. Any alterations and modifications of the present invention, which are made by those of ordinary skill in the art based on the above disclosure, are intended to be within the scope of the appended claims.
Claims (10)
1. The Low Voltage Differential Signaling (LVDS) receiving circuit with a wide input common mode range comprises an input stage, wherein the input stage comprises a first stage input end, a second stage input end, a first group of PMOS (P-channel metal oxide semiconductor) tube input differential pairs, a second group of PMOS tube input differential pairs and a level shifting module; the first-stage input end and the second-stage input end are used for applying differential input signal pairs VP and VN, and the differential input signal pairs VP and VN are respectively and directly connected with the grid electrodes of two transistors of the second group of PMOS tube input differential pairs and are used for controlling leakage currents of the two transistors; the differential input signal pair VP and VN are also indirectly connected with the grid electrodes of the two transistors of the first group of PMOS tube input differential pair through a level shifting module respectively and used for controlling leakage currents of the two transistors; the level shift module is used for reducing the input common mode level, and is characterized in that:
the input stage further comprises a PMOS transistor PM5 serving as a switch, a reference voltage module, and a bias circuit module;
the drain electrode of the transistor PM5 is connected with the source electrodes of the two transistors of the first group of PMOS transistor input differential pairs to a first node, the source electrodes of the transistor PM5 and the source electrodes of the two transistors of the second group of PMOS transistor input differential pairs are connected to a second node, and the grid electrode of the transistor PM5 is connected with a reference voltage module;
The reference voltage module provides a reference voltage V REF To the transistors PM5, V REF As the gate voltage of the transistor PM 5;
the bias circuit module is used for providing bias current I0 of the input stage and performing control configuration of the bias current; wherein the bias circuit module is configured to: in the case of determining that the input common mode level is at the intermediate level or that the input common mode level is at the reference voltage V REF When the difference value of the first and second nodes is within the preset range, the output bias current I0 is regulated down, so that the bias current I0 flowing to the first and second nodes is reduced.
2. The LVDS receiving circuit of claim 1, wherein: the bias current I0 output by the bias circuit module and the input common mode level V CM,IN In relation, the input common mode level V CM,IN = (vp+vn)/2, VP represents the positive side signal, VN represents the negative side signal;
the bias current I0 and the input common mode level V CM,IN The relation expression of (a) is I0=I Fixing +f(V CM,IN ) Wherein I is Fixing And input common mode level V CM,IN Irrespective of f (V) CM,IN ) Representing and inputting common mode level V CM,IN A related function;
configuration f (V) CM,IN ) The weight duty ratio of the relation expression is expressed in the aforesaid way to reduce the input common mode level V CM,IN Influence on bias current I0; wherein, in configuration f (V CM,IN ) When a function is inputted a common mode level V CM,IN When the difference between the power supply voltage and the ground voltage is within the preset range, let f (V CM,IN ) =0; when the power voltage is equal to the reference voltage V REF When the difference of (2) is within the preset range, let f (V CM,IN ) Is a preset negative value.
3. The LVDS receiving circuit according to claim 1 or 2, wherein: the bias circuit module comprises a comparison unit and a bias current I0 control unit;
the comparing unit is configured to: comparing the input common mode level with the reference voltage V REF The power supply voltage and the ground voltage, and sends the comparison result to a bias current I0 control unit;
the bias current I0 control unit is configured to: acquiring the comparison result, when the difference value between the input common mode level and the ground voltage is within a preset range, judging that the input common mode level is close to the ground voltage, and the transistor PM5 is in an off state, wherein bias current I0 completely flows to the second node, and at the moment, the two transistors PM3 and PM4 of the second group of PMOS tube input differential pairs work; the method comprises the steps of,
when the difference value between the input common mode level and the power supply voltage is within a preset range, the input common mode level is judged to be close to the power supply voltage, two transistors of the second group of PMOS tube input differential pairs are turned off, bias current I0 mainly flows to the source electrode of the transistor PM5, at the moment, the two transistors PM1 and PM2 of the first group of PMOS tube input differential pairs work, and the direct current level of the differential input signal pairs VP and VN is reduced through a level shifting module; the method comprises the steps of,
When the common mode level and the reference voltage V are input REF When the difference value of (2) is within the preset range, determining that the common mode level is at the reference voltage V REF Near, bias current I0 flows to the first node and the second node at the same time, and at the moment, two transistors of the first group of PMOS tube input differential pairs and two transistors of the second group of PMOS tube input differential pairs work at the same time; and regulating the output bias current I0 down so that the bias current I0 flowing to the input differential pair of the two groups of PMOS tubes is reduced.
4. The LVDS receive circuit of claim 3, wherein: the bias circuit module comprises PMOS transistors PM0, PM8, PM9, PM10 and PM11, NMOS transistors NM1, NM2 and NM3 and two resistors R3 and R4 with equal resistance values;
the drain electrode of the transistor PM0 is connected with the source electrodes of the transistors PM3 and PM4 of the second group of PMOS tube input differential pairs, and bias current I0 is provided for the input stage; the source of the transistor PM0 is connected with the power supply voltage VDD; the gate of the transistor PM0 is connected to the gate and the drain of the transistor PM8, while being connected to the drain of the transistor NM1, and while being connected to the drain of the transistor PM 9; transistors PM0 and PM8 constitute a current mirror; the sources of the transistors PM8 and PM9 are connected with a power supply voltage VDD;
the gate of the transistor NM1 is connected with a bias voltage V BIAS Source electrode ground voltage VSS, is used for forming the current source;
the grid electrode of the transistor PM9 is connected with the grid electrode and the drain electrode of the transistor PM10, and the transistors PM9 and PM10 form a current mirror; the source of the transistor PM10 is connected with the power supply voltage VDD, the drain of the transistor PM10 is also connected with the source of the transistor PM11, the drain of the transistor PM11 is connected with the drain of the transistor NM2, the source of the transistor NM2 is simultaneously connected with the drain and the gate of the transistor NM3, and the source of the transistor NM3 is grounded at the voltage VSS; the gates of the transistor PM11 and the transistor NM2 are connected with the connection part of the resistors R3 and R4, the other end of the resistor R3 is connected with the input positive end signal VP of the receiving circuit, the other end of the resistor R4 is connected with the input negative end signal VN of the receiving circuit, and the potential of the connection part of the resistors R3 and R4 is the input common mode level V CM,IN 。
5. The LVDS receive circuit of claim 4, wherein: let the ratio of the width to length ratio of the transistor PM0 to the transistor PM8 be m and the ratio of the width to length ratio of the transistor PM9 to the transistor PM10 be 1, the bias current i0=mχi provided by the transistor PM0 NM1 -m*I PM10 Wherein I NM1 Represents the current, m.times.I, of the transistor NM1 NM1 Is a fixed part and does not follow the input common mode level V CM,IN A change; i PM10 Represents the current, m.times.I, of the transistor PM10 PM10 As a variable part, with input common mode level V CM,IN A change by change;
when the input common mode level is higher than or lower than the preset threshold, the transistor PM11 or NM2 is turned off, at which time I PM10 Bias current i0=m×i NM1 The method comprises the steps of carrying out a first treatment on the surface of the When the input common mode level is at the intermediate level or at the reference voltage V REF Nearby, the bias circuit module turns on transistors PM11 and NM2 by adjusting the size of transistors PM11, NM2 and NM3,so that I PM10 >And 0 to reduce the bias voltage I0, so as to compensate the increase of the total transconductance Gm of the circuit caused by the simultaneous operation of the first group of PMOS tube input differential pairs PM1 and PM2 and the second group of PMOS tube input differential pairs PM3 and PM 4.
6. The LVDS receiving circuit of claim 1, wherein: the input stage further comprises a load module;
the drain electrode of one transistor in the first PMOS tube input differential pair and the drain electrode of one transistor in the second PMOS tube input differential pair are connected to the negative end output VON1 of the input stage, and the drain electrode of the other transistor in the first PMOS tube input differential pair and the drain electrode of the other transistor in the second PMOS tube input differential pair are connected to the positive end output VOP1 of the input stage; the load module is connected with the VOP1 and the VON1 and used for primary amplification of signals and generating an input common mode level of a rear-stage circuit;
The load module comprises two grounding resistors R1 and R2 with equal resistance values, one end of the resistor R1 is grounded, the other end of the resistor R2 is grounded, and the other end of the resistor R is grounded.
7. The LVDS receiving circuit of claim 1, wherein: the circuit also comprises a comparator module positioned behind the input stage, wherein the VOP1 and the VON1 are respectively connected to the positive end input and the negative end input of the comparator module, and the VOP1 and the VON1 signals are amplified and/or shaped by the comparator module to obtain an output signal VOUT.
8. The LVDS receive circuit of claim 7, wherein: the comparator module comprises PMOS transistors PM12, PM13 and PM14, NMOS transistors NM6, NM7, NM8 and NM9, and an output stage;
transistors PM13 and PM14 as an input differential pair, the gates of which are connected to VOP1 and VON1 signals, respectively, the sources of transistors PM13 and PM14 being connected, and simultaneously, to the drain of transistor PM 12; the gate of the transistor PM12 is connected to the second bias voltage V BIAS2 The source electrode is connected with a power supply V DDCORE To transistors PM13 and PM14Supplying bias current;
the drain of the transistor PM13 is connected to the drain and gate of the transistor NM8, simultaneously to the drain of the transistor NM6, simultaneously to the gate of the transistor NM7, simultaneously to the negative input terminal of the output stage; the drain of the transistor PM14 is connected to the drain and gate of the transistor NM9, and simultaneously to the drain of the transistor NM7, and simultaneously to the gate of the transistor NM6, and simultaneously to the input positive terminal of the output stage;
Transistors NM6, NM7, NM8 and NM9 form a diode load with positive feedback for realizing hysteresis;
the output stage is used for amplifying, differentiating, converting to single end and/or shaping the signal and outputting the signal VOUT.
9. The LVDS receiving circuit of claim 1, wherein: the level shift module includes NMOS transistors NM4 and NM5, and NMOS transistors NM16 and NM17; the gates of the transistors NM16 and NM17 are respectively connected to the differential input signal pair VP and VN, the sources of the transistors NM16 and NM17 are respectively connected to the gates of the transistors PM1 and PM2, and are respectively connected to the drains of the transistors NM4 and NM5, and the drains of the transistors NM16 and NM17 are both connected to the power supply voltage VDD; the gates of the transistors NM4 and NM5 are connected to a first bias voltage V BIAS1 The sources of the transistors NM4 and NM5 are both connected to the ground voltage VSS, and the transistors NM4 and NM5 are used for the role of current sources;
and/or the reference voltage module comprises a PMOS transistor PM15 and an NMOS transistor NM10, wherein the source electrode of the transistor NM10 is grounded to the voltage VSS, and the grid electrode of the transistor NM10 is connected to the first bias voltage V BIAS1 The transistor NM10 is used for the role of a current source; meanwhile, the drain of the transistor NM10 is connected to the gate and drain of the transistor PM15, the source of the transistor PM15 is connected to the power supply voltage VDD, and the drain output of the transistor NM10 provides the gate voltage V for the transistor PM5 REF 。
10. A chip on which a receiver capable of converting LVDS signals is integrated, characterized in that: the receiver comprising the LVDS receiving circuit of any one of claims 1-9.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310060754.5A CN116488596A (en) | 2023-01-19 | 2023-01-19 | LVDS receiving circuit with wide input common mode range and chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310060754.5A CN116488596A (en) | 2023-01-19 | 2023-01-19 | LVDS receiving circuit with wide input common mode range and chip |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN116488596A true CN116488596A (en) | 2023-07-25 |
Family
ID=87220209
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202310060754.5A Pending CN116488596A (en) | 2023-01-19 | 2023-01-19 | LVDS receiving circuit with wide input common mode range and chip |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN116488596A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117149689A (en) * | 2023-11-01 | 2023-12-01 | 江苏帝奥微电子股份有限公司 | Low-power consumption detection circuit and detection method thereof |
| CN117713768A (en) * | 2024-02-05 | 2024-03-15 | 安徽大学 | Complementary input comparator circuit and module |
| CN117997295A (en) * | 2024-03-29 | 2024-05-07 | 瓴科微(上海)集成电路有限责任公司 | LVDS receiving circuit |
| CN118113100A (en) * | 2024-04-25 | 2024-05-31 | 瓴科微(上海)集成电路有限责任公司 | LVDS circuit with wide input range |
-
2023
- 2023-01-19 CN CN202310060754.5A patent/CN116488596A/en active Pending
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117149689A (en) * | 2023-11-01 | 2023-12-01 | 江苏帝奥微电子股份有限公司 | Low-power consumption detection circuit and detection method thereof |
| CN117149689B (en) * | 2023-11-01 | 2023-12-29 | 江苏帝奥微电子股份有限公司 | Low-power consumption detection circuit and detection method thereof |
| CN117713768A (en) * | 2024-02-05 | 2024-03-15 | 安徽大学 | Complementary input comparator circuit and module |
| CN117713768B (en) * | 2024-02-05 | 2024-04-26 | 安徽大学 | Complementary input comparator circuit and module |
| CN117997295A (en) * | 2024-03-29 | 2024-05-07 | 瓴科微(上海)集成电路有限责任公司 | LVDS receiving circuit |
| CN117997295B (en) * | 2024-03-29 | 2024-06-18 | 瓴科微(上海)集成电路有限责任公司 | LVDS receiving circuit |
| CN118113100A (en) * | 2024-04-25 | 2024-05-31 | 瓴科微(上海)集成电路有限责任公司 | LVDS circuit with wide input range |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN116488596A (en) | LVDS receiving circuit with wide input common mode range and chip | |
| US5594383A (en) | Analog filter circuit and semiconductor integrated circuit device using the same | |
| EP2498398B1 (en) | Amplifier circuit and method | |
| US20080246511A1 (en) | Differential Drive Circuit and Electronic Apparatus Incorporating the Same | |
| US7733181B2 (en) | Amplifier circuit having dynamically biased configuration | |
| EP2652872B1 (en) | Current mirror and high-compliance single-stage amplifier | |
| CN103907285A (en) | Differential amplifier | |
| CN110729995B (en) | Level conversion circuit and level conversion method | |
| CN109546975B (en) | operational transconductance amplifier | |
| CN110932714A (en) | SUBLVDS-based transmission interface circuit | |
| US6133764A (en) | Comparator circuit and method | |
| CN113507270B (en) | Variable gain amplifier | |
| US6538513B2 (en) | Common mode output current control circuit and method | |
| CN101995900B (en) | Gradient voltage generator used for continuous variable gain amplifier | |
| KR20180071988A (en) | Fully balanced differential rail-to-rail second generation current conveyor | |
| KR100499859B1 (en) | Variable gain amplifier | |
| CN209930214U (en) | Novel common mode level shift circuit for operational amplifier | |
| CN114584082B (en) | Bandwidth adjusting circuit and bandwidth adjusting method of operational amplifier | |
| KR100499856B1 (en) | Variable gain amplifier | |
| US6686794B1 (en) | Differential charge pump | |
| US10720890B1 (en) | High-speed high-accuracy amplifier and method thereof | |
| CN117997295B (en) | LVDS receiving circuit | |
| CN114094948B (en) | Rail-to-Rail Amplifier Common Mode Sensing Control Constant Transconductance Input Method | |
| CN219740326U (en) | Amplifier | |
| CN111756358B (en) | Hysteresis voltage configurable comparator and hysteresis voltage control method |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |