CN110932714A

CN110932714A - SUBLVDS-based transmission interface circuit

Info

Publication number: CN110932714A
Application number: CN201911306254.5A
Authority: CN
Inventors: 殷景志; 石梦涵; 常玉春; 蒋佳奇
Original assignee: Jilin University
Current assignee: Jilin University
Priority date: 2019-12-18
Filing date: 2019-12-18
Publication date: 2020-03-27
Anticipated expiration: 2039-12-18
Also published as: CN110932714B

Abstract

The invention provides a high-speed transmission interface circuit based on a SUBLVDS technology, and belongs to the technical field of integrated circuits. The circuit mainly comprises three parts: the device comprises a single-end-to-differential module, an input buffer module and a common-mode feedback output driving module. The high-speed output device is used for converting a single-ended signal inside a chip into a pair of low-voltage differential signals meeting the SUBLVDS protocol standard and outputting the signals to the outside of the chip at a high speed. The invention can work under 1.2V low voltage, has 150mV of output swing and high transmission speed, and can be used for high-frequency signal transmission. Meanwhile, the driver circuit with a swing rate compensation structure is adopted, and an adjustable internal terminal resistor is added, so that the impedance matching performance of the circuit is greatly improved, the overshoot and ringing phenomena of a transmission signal are greatly reduced, and the transmission quality is improved. A common mode feedback loop is formed in the circuit, so that the output common mode is stable, and the output signal can be stably received.

Description

SUBLVDS-based transmission interface circuit

Technical Field

The invention belongs to the technical field of integrated circuits, and particularly relates to a SUBLVDS-based transmission interface circuit.

Background

In the present day of rapid development of information technology, high-speed transmission of signals is becoming an important ring in the information world. Since the high-speed signal is difficult to be directly transmitted from the inside of the chip to the outside of the chip, there is a large difference in data transmission speed between the inside and the outside of the chip, and this difference becomes an important factor affecting the performance of the system. The use of a low voltage, low swing high speed data transmission interface is an effective solution to this problem.

The LVDS interface is an interface technology for realizing high-speed data transmission between point and point by using a low-voltage low-swing differential signal, and has the advantages of high speed, low power consumption, low cost and the like. The SUBLVDS interface is a new technology developed by the LVDS interface, and its operating voltage is further reduced compared to LVDS, and it can operate under 1.2V supply voltage. The common mode level value is reduced to 0.9V, the differential swing is reduced to 150mV, and the power consumption is further reduced compared with LVDS.

The conventional SUBLVDS output interface is shown in fig. 1, and the structure has the following disadvantages: firstly, due to the existence of the external terminal resistor, serious signal reflection can be caused when a signal passes through a transmission line with a sudden change of the resistor, and the impedance matching performance is poor; secondly, the output common mode of the signals cannot be maintained, and the output cannot be stably received; thirdly, due to parasitic capacitance and inductance on the transmission line, overshoot and oscillation attenuation often occur in the response signal, affecting the transmission quality.

Disclosure of Invention

In order to overcome the defects in the prior art, such as poor impedance matching, unstable output common mode, overshoot and oscillation attenuation of an output signal, the invention provides a transmission interface circuit based on the SUBLVDS.

The invention is realized by the following technical scheme:

a transmission interface circuit based on SUBLVDS is used for transmitting high-speed signals inside a chip to the outside of the chip and comprises a single-ended-to-differential module, an input buffer module and a common-mode feedback output driving module; the single-ended to differential module is used for converting an input single-ended signal into a differential signal and outputting the differential signal to the input buffer module; the input buffer module is used for transmitting the received differential signal to the common-mode feedback output driving module after the signal driving capability of the received differential signal is improved through the two stages of buffers; the common-mode feedback output driving module changes the received signals into differential submit signals with the swing of 150mV through an internal double-current-source driver structure and outputs the differential submit signals.

Furthermore, the single-ended to differential module consists of a positive phase signal output part and a negative phase signal output part, and input ends of the two parts are connected together and used for receiving an input single-ended signal; the inverted signal output part is formed by cascading three inverters, and an input single-ended signal is inverted for three times and then outputs an inverted signal; the normal phase signal output part is formed by connecting two inverters and a TG transmission gate in sequence, the input end of the TG transmission gate is connected with the output end of the two-stage inverters, and the input single-ended signal passes through the two cascaded inverters first and outputs the normal phase signal after twice phase inversion. The transmission delay is caused because the inverted phase signal passes through one more inverter than the normal phase signal, so that the normal phase signal needs to pass through one TG transmission gate to increase the transmission delay, and the delayed normal phase signal and the delayed inverted phase signal can be delayed to be consistent by adjusting the parameters of the transmission gate.

Furthermore, the input buffer module is divided into two parts which are respectively used for providing driving force for the positive phase output signal and the negative phase output signal, and the two parts have consistent circuit structures and are formed by cascading four-level inverters; the sizes of the NMOS tube and the PMOS tube of the phase inverter are gradually enlarged by four times from the first stage to the fourth stage, namely the size of the phase inverter at the fourth stage is 64 times that of the first stage.

Further, the common-mode feedback output driving module is a common-mode feedback loop composed of a core driving module, an internal terminal resistance module, a common-mode adjusting module and a reference common-mode generating module; the core driving module has four input ends which are two signal input ends and two current source input ends respectively, the two signal input ends of the core driving module are connected with the input differential signal, and the two current source input ends are connected with the two output ends of the common-mode adjusting module respectively; two output ends of the core driving module are connected to two input ends of the internal terminal resistance module, the internal terminal resistance module has three output ends in total, two signal output ends are differential output ends of the whole interface circuit, and the other one is an induced common-mode voltage output end; the input end of the reference common mode generation module is connected with a band gap reference voltage with a voltage value of 1.2V provided by the outside, and the output end of the reference common mode generation module is a common mode reference voltage with a voltage value of 0.9V; two input ends of the common mode adjusting module are respectively connected with the induced common mode voltage output end of the internal terminal resistor module and the output end of the reference common mode generating module.

Furthermore, the core driving module adopts a dual-current-source driving structure with slew rate compensation, and adopts a method of combining output transconductance and an RC network to pre-emphasize the output signal and compensate the oscillation ringing phenomenon of the response signal. The core driving module comprises two pairs of mirror current sources, two pairs of inverters, four driver switching tubes and an RC delay network; the dual current source driving structure is two pairs of mirror current sources, wherein the two pairs of mirror current sources are respectively M1 and M2, M3 and M4 and are used for providing current for the driver; a PMOS mirror current source formed by M1 and M2, wherein the drain terminal of M2 is connected with the source terminals of M7 and M9; an NMOS mirror current source formed by M3 and M4, wherein the drain terminal of M4 is connected with the source terminals of M8 and M10; the two pairs of inverters are respectively an inverter formed by M11 and M12 and an inverter formed by M5 and M6; the grid ends of the M5 and the M6, namely the input end of the inverter, are connected with the positive phase input signal INP, and the output end of the inverter is connected with one end of a resistor RD 1; the grid ends of the M11 and the M12, namely the input end of the other inverter, are connected with an inverted input signal INN, and the output end of the other inverter is connected with one end of a resistor RD 2; the four driver switching tubes are M7, M8, M9 and M10; m7 and M9 are PMOS tubes, and the source ends of the PMOS tubes are connected; m8 and M10 are NMOS tubes, and the source ends of the two are connected; m7 is connected with the drain terminal of M8, and the connection position of the drain terminals of the M7 and the M8 is used as an inverted output signal OUTN; m9 is connected to the drain of M10, and the drain is connected to serve as the non-inverting output signal OUTP. M7 is connected with the gate terminal of M8 and is connected with one end of a resistor RD 1; m9 is connected with the gate terminal of M10 and is connected with one end of a resistor RD 2; the RC delay network comprises two resistors RD and a capacitor CD; one end of a resistor RD1 is connected to the drain terminals of M5 and M6, namely the output terminal of the inverter, and the other end is connected to the gate terminals of M7 and M8; one end of a resistor RD2 is connected to the drain terminals of M11 and M12, namely the output terminal of the inverter, and the other end is connected to the gate terminals of M9 and M10; one end of the capacitor CD is connected to the gate terminals of M7 and M8, and the other end is connected to the gate terminals of M9 and M10.

Furthermore, the internal terminal resistance module is used for performing impedance matching and sensing output common-mode value and consists of a resistance array and a switch MOS (metal oxide semiconductor) tube; the resistor array comprises a matching resistor, a shunt resistor and an induction resistor; m1 and M2 are switching MOS transistors for controlling whether to shunt, and R0 is an internal matching resistor with a resistance of 100 Ω for impedance matching. The adjustable resistor is made in the design, and the on-off of the branch where the adjustable resistor is located can be changed by adjusting the grid end voltages of M1 and M2, so that the internal matching resistance is reduced. The resistors R1, R2, R3 and R4 are shunt resistors. R5 and R6 are sense resistors for sensing the common mode voltage value of the output. R1, M1, R2 are connected in series, R3, M2 and R4 are connected in series, R5 is connected in series with R6, and the three branches are connected with R0 in parallel. R5 and R6 have the same resistance and are both 100k Ω resistors, and are used to sense the output common mode level of the SUBLVDS driver.

Further, the common mode adjusting module adjusts the gate voltages VB1 and VB2 of the two mirror current sources of the core driving module through the input reference common mode value and the output common mode value sensed by the internal terminal resistor, so as to adjust the magnitude of the current and make the output common mode approach the reference value; the module has two input ends in common, one end is connected with a reference common-mode voltage VREF, the other end is connected with a sensing common-mode voltage VCM, when the two voltage values are different, voltages VB1 and VB2 can be changed, the change of two current source current values of the core driving module can be controlled through the change of VB1 and VB2, and the module is formed by a typical fully differential five-tube operational amplifier.

Further, the reference common mode generation module is an operational amplifier working in a negative feedback mode, and obtains an output standard voltage VREF through a positive input voltage VBG; three resistors R1, R2 and R3 are connected in series between the output end of the operational amplifier and the ground, the negative input end of the operational amplifier is connected to the intersection point of the resistors R1 and R2 to form a negative feedback mode, the positive input end of the amplifier is connected with a band-gap reference voltage VBG, and the output end VREF is connected to the intersection point of the resistors R2 and R3.

Compared with the prior art, the invention has the following advantages:

the transmission interface circuit based on the SUBLVDS adopts a driving structure with slew rate compensation, a high-speed transmission interface circuit is designed, pre-emphasis is carried out on an output signal, ringing and overshoot of the output signal are reduced, and signal quality is enhanced; the circuit forms a common mode feedback loop, so that the output common mode is more stable, stable receiving is easier to realize, and the data transmission rate can reach 1.28 Gbps.

Drawings

Fig. 1 is a schematic diagram of a conventional SUBLVDS output interface;

fig. 2 is a schematic structural diagram of a SUBLVDS-based transmission interface circuit according to the present invention;

FIG. 3 is a schematic diagram of a single-ended to differential module according to the present invention;

FIG. 4 is a schematic diagram of an input buffer module according to the present invention;

FIG. 5 is a schematic diagram of a common mode feedback output driver module according to the present invention;

FIG. 6 is a schematic circuit diagram of a common mode feedback output driving module according to the present invention;

FIG. 7 is a schematic diagram of a core driver module according to the present invention;

FIG. 8 is a schematic diagram of an internal termination resistance module of the present invention;

FIG. 9 is a schematic diagram of a transmit side and receive side resistor matching model of the present invention;

FIG. 10 is a schematic diagram of a common mode adjustment module of the present invention;

FIG. 11 is a schematic diagram of a reference common mode generating module according to the present invention;

FIG. 12 is a schematic view of a five tube run configuration of the present invention;

Detailed Description

The following detailed description of embodiments of the invention refers to the accompanying drawings. It should be understood that the detailed description and specific examples, while indicating the present invention, are given by way of illustration and explanation only, not limitation.

The specific embodiment of the single-ended to differential module is combined with fig. 3. The module consists of a positive phase signal output part and a negative phase signal output part, wherein the input ends of the two parts are connected together and used for receiving an input single-ended signal IN. The inverted signal output part is formed by cascading three inverters, and the input single-ended signal is inverted for three times to output an inverted signal OUTN. The positive phase signal output part is formed by connecting two inverters and a TG transmission gate, and the input end of the TG transmission gate is connected with the output end of the two-stage inverters. The input single-ended signal firstly passes through two cascaded inverters, and outputs a positive phase signal after two inversions. Since the inverted signal passes through one more inverter than the non-inverted signal, a transmission delay is caused. Therefore, the normal phase signal needs to pass through a TG transmission gate to increase the transmission delay and output the signal OUTP. By adjusting the transmission gate parameters, the delayed positive phase signal OUTP and the delayed negative phase signal OUTN can be delayed to be consistent.

The input buffer module, in an embodiment, is combined with fig. 4. The module is divided into two parts, which are respectively used for improving the driving capability of a positive phase output signal and a negative phase output signal. The two parts of circuits have the same structure and are formed by cascading 4-level inverters. The size of the inverter is gradually enlarged by four times from the first stage to the fourth stage, namely the size of the inverter at the fourth stage is 64 times of that of the first stage. The positive phase signal is input into INN, and is cascaded by 4-stage inverters to output a signal OUTN. The inverted signal is input into INP, and is cascaded by 4 stages of inverters to output a signal OUTP.

The common mode feedback loop realizes output common mode stabilization, and the specific implementation mode is combined with fig. 6. M9 is connected to the reference common mode level VREF, and M10 is connected to the output common mode level VCM sensed by the internal termination resistance module. When the two are equal, the current flowing through M9 and M10 is the same, and a dual current source is provided for the core driver module by bias voltages VB1 and VB 2. When the sensed common mode is lower than the reference value, the current flowing through M9 is larger than M10, so that the current flowing through M2 of the core driving module is larger than the current flowing through M4. Due to the early effect, the drain-source voltage of M2 can be reduced, and the drain-source voltage of M4 can be increased, so that the output common-mode value can be improved. Similarly, when the induced common mode is higher than the reference value, the current flowing through M9 is smaller than the current flowing through M10, and then due to the early effect, the drain-source voltage of M2 is increased, and the drain-source voltage of M4 is reduced, so that the output common mode value is reduced. Therefore, the output common mode is regulated and stabilized to be about the reference common mode through the common mode feedback loop.

The core driving module adopts a double-current-source driving structure with slew rate compensation, and adopts a method of combining output transconductance and an RC network to pre-emphasize output signals and compensate oscillation ringing of response signals. The core driving module comprises two pairs of mirror current sources, two pairs of inverters, four driver switching tubes and an RC delay network; the dual current source driving structure is two pairs of mirror current sources, wherein the two pairs of mirror current sources are respectively M1 and M2, M3 and M4 and are used for providing current for the driver; a PMOS mirror current source formed by M1 and M2, wherein the drain terminal of M2 is connected with the source terminals of M7 and M9; an NMOS mirror current source formed by M3 and M4, wherein the drain terminal of M4 is connected with the source terminals of M8 and M10; the two pairs of inverters are respectively an inverter formed by M11 and M12 and an inverter formed by M5 and M6; the grid ends of the M5 and the M6, namely the input end of the inverter, are connected with the positive phase input signal INP, and the output end of the inverter is connected with one end of a resistor RD 1; the grid ends of the M11 and the M12, namely the input end of the other inverter, are connected with an inverted input signal INN, and the output end of the other inverter is connected with one end of a resistor RD 2; the four driver switching tubes are M7, M8, M9 and M10; m7 and M9 are PMOS tubes, and the source ends of the PMOS tubes are connected; m8 and M10 are NMOS tubes, and the source ends of the two are connected; m7 is connected with the drain terminal of M8, and the connection position of the drain terminals of the M7 and the M8 is used as an inverted output signal OUTN; m9 is connected to the drain of M10, and the drain is connected to serve as the non-inverting output signal OUTP. M7 is connected with the gate terminal of M8 and is connected with one end of a resistor RD 1; m9 is connected with the gate terminal of M10 and is connected with one end of a resistor RD 2; the RC delay network comprises two resistors RD and a capacitor CD; one end of a resistor RD1 is connected to the drain terminals of M5 and M6, namely the output terminal of the inverter, and the other end is connected to the gate terminals of M7 and M8; one end of a resistor RD2 is connected to the drain terminals of M11 and M12, namely the output terminal of the inverter, and the other end is connected to the gate terminals of M9 and M10; one end of the capacitor CD is connected to the gate ends of M7 and M8, and the other end of the capacitor CD is connected to the gate ends of M9 and M10; when INP is high INN is low, M7 and M10 are turned on, M8 and M9 are turned off, and current flows from OUTN to OUTP through an external termination resistor, so that a negative voltage drop is generated; when INP is low and INN is high, M8 and M10 open and current flows from OUTP to OUTN, creating a forward voltage drop.

The slew rate compensation pre-emphasis structure is implemented as follows. As shown in fig. 6, the input signal INP is connected to the gate terminals of M11 and M12, and the input signal INN is connected to the gate terminals of M13 and M14. M11 and M12 form an inverter, and M13 and M14 form an inverter. The resistor RD1 has one end connected to the drain terminals of M11 and M12, i.e. the output terminal of the inverter, and the other end connected to the gate terminals of M5 and M6. The resistor RD2 has one end connected to the drain terminals of M13 and M14, i.e. the output terminal of the inverter, and the other end connected to the gate terminals of M7 and M8. One end of the capacitor CD is connected to the gate terminals of M5 and M6, and the other end is connected to the gate terminals of M7 and M8. The method of combining output transconductance and the RC network is adopted to pre-emphasize the output signal and compensate the oscillation ringing phenomenon of the response signal. With an RC delay network, a portion of the output current is delayed from being delivered to the load, thereby suppressing output overshoot.

The internal termination resistance module is described in the detailed description with reference to fig. 8. The method is used for impedance matching and sensing output common mode values. Since the SUBLVDS uses a termination resistor with a resistance of 100 Ω at the receiving end to complete the current loop, a matching resistor of 100 Ω is also connected in parallel between the differential output end and the transmission line. R0 is an internal matching resistor having a resistance of 100 Ω for impedance matching. The adjustable resistor is made in the design, and the on-off of the branch where the adjustable resistor is located can be changed by adjusting the grid end voltages of M1 and M2, so that the internal matching resistance is reduced. R1, M1, R2 are connected in series, R3, M2 and R4 are connected in series, and the two groups of branches are connected in parallel with R0. By default, the gate voltages of M1 and M2 are low. R5 is in series with R6 and in parallel with R0. The R5 and R6 have the same resistance value, and are both 100k Ω resistors, and are used for sensing the output common mode level of the SUBLVDS driver, and the intersection point of the connection of R5 and R6 is used as the output sensing common mode voltage VCM. The reason why the impedances of R5 and R6 are selected to be so large is not to affect the output impedance of the driver. If the driver is found to have insufficient driving capability, the current of the driver is increased, the output swing amplitude is increased to exceed the protocol specification, and at the moment, the branch circuit can be started to divide the current, so that the output swing amplitude meets the requirement.

The common mode adjusting module is combined with the specific embodiment of fig. 10. The module adjusts the grid voltage of two mirror current sources of the core driving module through an input reference common-mode value and an output common-mode value sensed by the internal terminal resistor, so that the current is adjusted, and the output common mode tends to the reference value. The module has two input ends, namely the grid ends of a pair of PMOS input geminate transistors, and the grid ends are respectively connected with a reference common-mode voltage VREF and an induction common-mode voltage VCM. When the two voltage values are the same. The currents flowing through the two PMOS transistors are the same, so that the gate voltages VB1 and VB2 of the two NMOS transistors connected thereto are also the same. When VREF is different from VCM, voltages VB1 and VB2 change, and the change of the current values of the two current sources of the core driving module can be controlled through VB1 and VB2 changes. The module is composed of a fully differential five-tube operational amplifier, VREF and VCM are used as differential input ends, and VB1 and VB2 are used as differential output ends.

The reference common mode generation module is combined with the specific embodiment of fig. 11. Mainly by an operational amplifier operating in negative feedback mode. The bandgap reference voltage VBG is connected as an input to this block at the positive input of the amplifier. Three resistors R1, R2 and R3 are connected in series between the output of the amplifier and ground. The negative input of the amplifier is connected to the junction of the resistors R1 and R2, forming a negative feedback mode. The output terminal VREF is connected to the intersection of the resistors R2 and R3. The voltage value of VBG is 1.2V, and the voltage serving as a band gap reference voltage does not change along with temperature and power supply voltage. According to the negative feedback mode of operation, the voltage at the intersection of resistors R1 and R2 is the same as VBG. The resistance ratio of R2 to R3 is 4: and 3, the VREF voltage value of 0.9V can be obtained according to the resistor voltage division, and the output voltage is not changed along with the temperature and the power supply voltage like VBG.

The preferred embodiments of the present invention have been described in detail with reference to the accompanying drawings, however, the present invention is not limited to the specific details of the above embodiments, and various simple modifications can be made to the technical solution of the present invention within the technical idea of the present invention, and these simple modifications are within the protective scope of the present invention.

It should be noted that the various technical features described in the above embodiments can be combined in any suitable manner without contradiction, and the invention is not described in any way for the possible combinations in order to avoid unnecessary repetition.

In addition, any combination of the various embodiments of the present invention is also possible, and the same should be considered as the disclosure of the present invention as long as it does not depart from the spirit of the present invention.

Claims

1. A transmission interface circuit based on SUBLVDS is used for transmitting high-speed signals inside a chip to the outside of the chip and is characterized by comprising a single-ended-to-differential module, an input buffer module and a common-mode feedback output driving module; the single-ended to differential module is used for converting an input single-ended signal into a differential signal and outputting the differential signal to the input buffer module; the input buffer module is used for transmitting the received differential signal to the common-mode feedback output driving module after the signal driving capability of the received differential signal is improved through the two stages of buffers; the common-mode feedback output driving module changes the received signals into differential submit signals with the swing of 150mV through an internal double-current-source driver structure and outputs the differential submit signals.

2. A transmission interface circuit according to claim 1, wherein the single-ended to differential module is composed of a positive phase signal output and a negative phase signal output, and the input terminals of the two parts are connected together for receiving the input single-ended signal; the inverted signal output part is formed by cascading three inverters, and an input single-ended signal is inverted for three times and then outputs an inverted signal; the normal phase signal output part is formed by connecting two inverters and a TG transmission gate in sequence, the input end of the TG transmission gate is connected with the output end of the two-stage inverters, and the input single-ended signal passes through the two cascaded inverters first and outputs the normal phase signal after twice phase inversion. The transmission delay is caused because the inverted phase signal passes through one more inverter than the normal phase signal, so that the normal phase signal needs to pass through one TG transmission gate to increase the transmission delay, and the delayed normal phase signal and the delayed inverted phase signal can be delayed to be consistent by adjusting the parameters of the transmission gate.

3. The SUBLVDS-based transmission interface circuit according to claim 1, wherein the input buffer module is divided into two parts for providing driving force for the positive phase output signal and the negative phase output signal, and the two parts have the same circuit structure and are formed by cascading four stages of inverters; the sizes of the NMOS tube and the PMOS tube of the phase inverter are gradually enlarged by four times from the first stage to the fourth stage, namely the size of the phase inverter at the fourth stage is 64 times that of the first stage.

4. The SUBLVDS-based transmission interface circuit according to claim 1, wherein the common mode feedback output driving module is a common mode feedback loop consisting of a core driving module, an internal termination resistance module, a common mode adjusting module and a reference common mode generating module; the core driving module has four input ends which are two signal input ends and two current source input ends respectively, the two signal input ends of the core driving module are connected with the input differential signal, and the two current source input ends are connected with the two output ends of the common-mode adjusting module respectively; two output ends of the core driving module are connected to two input ends of the internal terminal resistance module, the internal terminal resistance module has three output ends in total, two signal output ends are differential output ends of the whole interface circuit, and the other one is an induced common-mode voltage output end; the input end of the reference common mode generation module is connected with a band gap reference voltage with a voltage value of 1.2V provided by the outside, and the output end of the reference common mode generation module is a common mode reference voltage with a voltage value of 0.9V; two input ends of the common mode adjusting module are respectively connected with the induced common mode voltage output end of the internal terminal resistor module and the output end of the reference common mode generating module.

5. The SUBLVDS-based transmission interface circuit according to claim 4, wherein the core driving module comprises two pairs of mirror current sources, two pairs of inverters, four driver switches and an RC delay network; the dual current source driving structure is two pairs of mirror current sources, wherein the two pairs of mirror current sources are respectively M1 and M2, M3 and M4 and are used for providing current for the driver; a PMOS mirror current source formed by M1 and M2, wherein the drain terminal of M2 is connected with the source terminals of M7 and M9; an NMOS mirror current source formed by M3 and M4, wherein the drain terminal of M4 is connected with the source terminals of M8 and M10; the two pairs of inverters are respectively an inverter formed by M11 and M12 and an inverter formed by M5 and M6; the grid ends of the M5 and the M6, namely the input ends of the inverters, are connected with a non-phase input signal INP; the grid ends of M11 and M12, namely the input end of the other inverter, are connected with an inverted input signal INN; the four driver switching tubes are M7, M8, M9 and M10; m7 and M9 are PMOS tubes, and the source ends of the PMOS tubes are connected; m8 and M10 are NMOS tubes, and the source ends of the two are connected; m7 is connected with the drain terminal of M8, and the connection position of the drain terminals of the M7 and the M8 is used as an inverted output signal OUTN; m9 is connected with the drain terminal of M10, and the connection position of the drain terminals of the M9 and the M10 is used as a positive phase output signal OUTP; m7 is connected with the gate terminal of M8 and is connected with one end of a resistor RD 1; m9 is connected with the gate terminal of M10 and is connected with one end of a resistor RD 2; the RC delay network comprises two resistors RD and a capacitor CD; one end of a resistor RD1 is connected to the drain terminals of M5 and M6, namely the output terminal of the inverter, and the other end is connected to the gate terminals of M7 and M8; one end of a resistor RD2 is connected to the drain terminals of M11 and M12, namely the output terminal of the inverter, and the other end is connected to the gate terminals of M9 and M10; one end of the capacitor CD is connected to the gate terminals of M7 and M8, and the other end is connected to the gate terminals of M9 and M10.

6. A SUBLVDS-based transmission interface circuit according to claim 4, wherein the switching of the branch where M1 and M2 are located can be changed by adjusting the gate voltages of M1 and M2, so as to reduce the internal matching resistance. The resistors R1, R2, R3 and R4 are shunt resistors. R5 and R6 are sense resistors for sensing the common mode voltage value of the output. R1, M1, R2 are connected in series, R3, M2 and R4 are connected in series, R5 is connected in series with R6, and the three branches are connected with R0 in parallel. R5 and R6 have the same resistance and are both 100k Ω resistors, and are used to sense the output common mode level of the SUBLVDS driver.

7. The SUBLVDS-based transmission interface circuit according to claim 4, wherein the internal termination resistor module for performing impedance matching and sensing output common mode values comprises a resistor array and a switching MOS transistor; the resistor array comprises a matching resistor, a shunt resistor and an induction resistor; m1 and M2 are switching MOS transistors for controlling whether to shunt or not, and R0 is an internal matching resistor with the resistance value of 100 omega and is used for impedance matching; the on-off of the branch where the M1 and M2 are located can be changed by adjusting the gate terminal voltages of the M1 and the M2, so that the internal matching resistance is reduced; the resistors R1, R2, R3 and R4 are shunt resistors. R5 and R6 are sense resistors for sensing the common mode voltage value of the output; r1, M1, R2 are connected in series, R3, M2 and R4 are connected in series, R5 is connected in series with R6, and the three branches are connected with R0 in parallel; r5 and R6 have the same resistance and are both 100k Ω resistors, and are used to sense the output common mode level of the SUBLVDS driver.

8. The SUBLVDS-based transmission interface circuit as claimed in claim 4, wherein the reference common mode generating module is an operational amplifier operating in a negative feedback mode, and obtains an output standard voltage VREF from the positive input voltage VBG; three resistors R1, R2 and R3 are connected in series between the output end of the operational amplifier and the ground, the negative input end of the operational amplifier is connected to the intersection point of the resistors R1 and R2 to form a negative feedback mode, the positive input end of the amplifier is connected with a band-gap reference voltage VBG, and the output end VREF is connected to the intersection point of the resistors R2 and R3.