CN112564689A - Multi-protocol IO multiplexing circuit - Google Patents
Multi-protocol IO multiplexing circuit Download PDFInfo
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
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Abstract
The invention provides a multi-protocol IO multiplexing circuit.A output driving module comprises a pull-up branch and a pull-down branch, wherein the pull-up branch comprises a pull-up transistor, the pull-down branch comprises a pull-down transistor, a first driving output end outputs a first driving signal, and a second driving output end outputs a second driving signal; and the bias generation module comprises an output copy circuit, a pull-up negative feedback loop and a pull-down negative feedback loop, wherein the output copy circuit copies the output driving module in an equal proportion and obtains a high direct current working point of the first driving signal and a low direct current working point of the second driving signal. The output driving module meets the requirements of a low-speed single-ended driving mode and a high-speed differential driving mode, and controls the output polarities of the first driving signal and the second driving signal through digital signals.
Description
Technical Field
The invention relates to the field of chip design, in particular to a multi-protocol IO multiplexing circuit.
Background
IO is an English abbreviation for Output and Output (Input/Output). The IO circuit is an important component of an electronic circuit, particularly an integrated circuit, in which an internal core of the integrated circuit is connected with a peripheral circuit to perform functions of level matching, impedance transformation, power amplification, protection and the like. In a high-speed serial interface IO circuit, especially an IO driving circuit in a voltage output mode, in order to ensure signal consistency, the magnitude of a capacitive load may affect the rising or falling time of a signal, and further affect the data transmission rate. In addition, for consumer electronics, in order to reduce chip cost, a certain design is required to satisfy multiple application scenarios simultaneously, including interface electrical standards that need to be adapted to multiple application platforms. In the prior art, IO circuits of various electrical standards are connected in parallel at an output end, but the parallel connection of a plurality of IOs can cause the multiplication of capacitive load.
Typical high-speed serial interface signals are generally characterized by differential and low swing, and can be divided into voltage driving and current driving from driving types. The general current-driven IO circuit is provided with constant driving current by a tail current source, an output common-mode point of the constant driving current is determined by a common-mode feedback circuit, and the LVDS interface generally adopts a current-driven IO structure. The IO circuit adopting the voltage driving logic determines the performance of common-mode output, differential swing amplitude and the like by managing the power supply voltage of an output stage, and the MIPI interface generally adopts the voltage driving logic.
In the electrical standard of the high-speed serial interface, the direct current performance and the alternating current performance of a signal are generally defined, wherein the direct current performance includes a signal swing, a common mode range and the like; the ac performance includes ripple size, signal conversion time, etc. The ac performance of the IO interface mainly depends on the output equivalent impedance and the load condition, wherein the magnitude of the capacitive load not only affects the signal conversion time, but also affects the ripple magnitude, and the higher the interface rate, the higher the requirements for shortening the signal conversion time and suppressing the ripple are. The control of the capacitive load at the output is greatly facilitated if different electrical standards can be met with one drive configuration. Therefore, the same circuit structure is adopted to meet different interface electrical standards, and no effective solution for the problem exists.
Disclosure of Invention
The present invention is directed to overcome the above-mentioned defects in the prior art, and to provide a multi-protocol IO multiplexing circuit.
To achieve the above object, the present invention provides a multi-protocol IO multiplexing circuit, including:
the output driving module is provided with a pull-up input end, a pull-down input end, a first digital input end, a second digital input end, a first driving output end and a second driving output end, the output driving module comprises a pull-up branch and a pull-down branch, the pull-up branch comprises a pull-up transistor, the pull-down branch comprises a pull-down transistor, a grid electrode of the pull-up transistor is connected with the pull-up input end and is connected with a pull-up bias signal, a grid electrode of the pull-down transistor is connected with the pull-down input end and is connected with a pull-down bias signal, the first driving output end outputs a first driving signal, and the second driving output end outputs a second driving signal;
the bias generation module is provided with a pull-up reference input end, a pull-down reference input end, a pull-up feedback output end and a pull-down feedback output end and comprises an output replication circuit, a pull-up negative feedback loop and a pull-down negative feedback loop, wherein the output replication circuit replicates the output driving module in equal proportion to obtain a high direct current working point of a first driving signal and a low direct current working point of a second driving signal; one side of the pull-up negative feedback loop is connected with the pull-up reference input end and is accessed with a pull-up analog reference signal, the pull-up analog reference signal and the high direct current working point are compared, and a pull-up analog feedback signal is output to a pull-up feedback output end, one side of the pull-down negative feedback loop is connected with the pull-down reference input end and is accessed with a pull-down analog reference signal, the pull-down analog reference signal and the low direct current working point are compared, and a pull-down analog feedback signal is output to the pull-down feedback output end;
a first pull-up input end of the pull-up two-way one-choice selector is connected with the pull-up feedback output end, a second pull-up input end of the pull-up two-way one-choice selector is connected with a first potential, a pull-up output end of the pull-up two-way one-choice selector is connected with the pull-up input end, and a pull-up control end of the pull-up two-way one-choice selector is connected with a;
a first pull-down input end of the pull-down two-way selector is connected with the pull-down feedback output end, a second pull-down input end is connected with a second potential, a pull-down output end is connected with the pull-down input end, and a pull-down control end is connected with the control node;
the mode control module is provided with a control input end, a first input end, a second input end, a third input end, a first output end and a second output end, the control input end is connected with the control node, the control node is connected with a mode control signal, the first input end is connected with a first control signal, the second input end is connected with a second control signal, the third input end is connected with a third control signal, the first output end is connected with the first digital input end, the second output end is connected with the second digital input end, the first control signal and the second control signal are low-speed single-ended bit signals, and the third control signal is a high-speed differential signal.
Preferably, the mode control signal is a low potential, the bias generation module is in an off state, the pull-up output terminal outputs a first potential, the pull-down output terminal outputs a second potential, the gate of the pull-up transistor is set low, the gate of the pull-down transistor is set high, the pull-up transistor and the pull-down transistor are in linear region operation, and the potentials of the first driving signal and the second driving signal are full swing signals.
Preferably, the first potential is a ground potential, and the second potential is a power point; or, the first potential is a power supply potential, and the second potential is a ground potential.
Preferably, the mode control signal is a high potential, the bias generation module is in an on state, the pull-up output terminal outputs the pull-up analog feedback signal, the pull-down output terminal outputs the pull-down analog feedback signal, the pull-up transistor and the pull-down transistor operate in a saturation region, and potentials of the first drive signal and the second drive signal are low swing differential signals.
Preferably, the pull-up branch further includes a first pull-up differential switch and a second pull-up differential switch, and the pull-down branch further includes a first pull-down differential switch and a second pull-down differential switch; the first control signal controls the first pull-up differential switch and the first pull-down differential switch to be connected or disconnected, and the second control signal controls the second pull-up differential switch and the second pull-down differential switch to be connected or disconnected.
Preferably, the first pull-up differential switch is a first pull-up differential transistor, the second pull-up differential switch is a second pull-up differential transistor, the first pull-down differential switch is a first pull-down differential transistor, the second pull-up differential switch is a second pull-up differential transistor, a gate of the first pull-up differential transistor and a gate of the first pull-down differential transistor are commonly connected to the first digital input terminal, and a gate of the second pull-up differential transistor and a gate of the second pull-down differential transistor are commonly connected to the second digital input terminal, wherein: the source electrode of the pull-up transistor is connected with a power supply, the grid electrode of the pull-up transistor is connected with the pull-up input end, and the drain electrode of the pull-up transistor is connected with the source electrode of the first pull-up differential transistor and the source electrode of the second pull-up differential transistor; the drain electrode of the first pull-up differential transistor is connected with a first end of a first resistor, a second end of the first resistor is connected with the first driving output end, a first node is arranged between the second end of the first resistor and the first driving output end, the anode of a first diode and the cathode of a second diode are connected to the first node together, the cathode of the first diode is connected with the power supply, and the anode of the second diode is grounded; the drain electrode of the second pull-up differential transistor is connected with the first end of a second resistor, the second end of the second resistor is connected with the second driving output end, a second node is arranged between the second end of the second resistor and the second driving output end, the anode of a third diode and the cathode of a fourth diode are connected to the second node together, the cathode of the third diode is connected with the power supply, and the anode of the fourth diode is grounded; the source electrode of the pull-down transistor is connected with a power supply, the grid electrode of the pull-down transistor is connected with the pull-down input end, and the drain electrode of the pull-down transistor is connected with the source electrode of the first pull-down differential transistor and the source electrode of the second pull-up differential transistor; the drain of the first pull-down differential transistor and the drain of the first pull-up differential transistor are commonly connected to the first end of the first resistor, and the drain of the second pull-down differential transistor and the drain of the second pull-up differential transistor are commonly connected to the first end of the second resistor.
Preferably, the pull-up transistor, the first pull-up differential transistor and the second pull-up differential transistor are PMOS transistors, and the pull-down transistor, the first pull-down differential transistor and the second pull-up differential transistor are NMOS transistors; or the pull-up transistor, the first pull-up differential transistor and the second pull-up differential transistor are NMOS transistors, and the pull-down transistor, the first pull-down differential transistor and the second pull-up differential transistor are PMOS transistors.
Preferably, the output stage replica circuit includes a first replica transistor, a second replica transistor, a third replica transistor, a fourth replica transistor, a first replica resistor, a second replica resistor, and a third replica resistor, the pull-up negative feedback loop includes a pull-up amplifier, and the pull-down negative feedback loop includes a pull-down amplifier; the source of the first replica transistor is connected with the power supply, the gate is connected with the output end of the pull-up amplifier, the drain is connected with the source of the second replica transistor, the gate of the second replica transistor is grounded, the drain is connected with the first end of the first replica resistor, the second end of the first replica resistor and the first end of the second replica resistor are connected with the reverse input end of the pull-up amplifier, the forward input end of the pull-up amplifier is connected with the pull-up analog reference signal, the output end outputs a pull-up analog feedback signal to the first replica transistor, the second end of the second replica resistor and the first end of the third replica resistor are connected with the forward input end of the pull-down amplifier, the reverse input end of the pull-down amplifier is connected with the pull-down analog reference signal, and the output end outputs a pull-down analog feedback signal to the fourth replica transistor, the second end of the third replication resistor is connected with the drain electrode of the third replication transistor, the grid electrode of the third replication transistor is connected with the power supply, the source electrode of the third replication transistor is connected with the drain electrode of the fourth replication transistor, the source electrode of the fourth replication transistor is grounded, and the grid electrode of the fourth replication transistor is connected with the output end of the pull-down amplifier.
Preferably, the first replica transistor replicates the pull-up transistor in equal proportion, the first replica resistor replicates the first resistor in equal proportion, the second replica transistor replicates the second resistor in equal proportion, and the fourth replica transistor replicates the pull-down transistor in equal proportion.
Preferably, the mode control module includes a first inverter, a second inverter, a third inverter, a fourth inverter, a first mode selector and a second mode selector, an input end of the first inverter is connected to the first input end, an output end of the first inverter is connected to the first selection input end of the first mode selector, an input end of the second inverter is connected to the second input end, an output end of the second inverter is connected to the first selection input end of the second mode selector, an input end of the third inverter is connected to the third input end, an output end of the third inverter is connected to the input end of the fourth inverter, and an output end of the fourth inverter is connected to the second selection input end of the second mode selector; the second selection input end of the first mode selector is connected with the output end of the third phase inverter, the control end of the first mode selector and the control end of the second mode selector are connected to the control input end together, the output end of the first mode selector is connected with the first output end, and the output end of the second mode selector is connected with the second output end.
According to the technical scheme, the multi-protocol IO multiplexing circuit provided by the invention has the advantages that one output driving circuit realizes a low-speed single-ended driving mode and a high-speed differential driving mode through IO multiplexing, the output polarity of a driving signal is controlled through a digital signal, the interface circuit using the structure can simultaneously meet the requirements of different application platforms on serial interfaces and parallel interfaces, the parasitic capacitance of the output end is greatly reduced, the guarantee of the interface speed is facilitated, the area of the IO circuit is greatly reduced, the structure is a low-cost, high-speed and high-compatibility IO driving circuit structure, and the structure has obvious significance.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
Fig. 1 is a schematic diagram of a multi-protocol IO multiplexing circuit according to a preferred embodiment of the invention.
Fig. 2 is a schematic structural diagram of an output driving module of a multi-protocol IO multiplexing circuit according to a preferred embodiment of the invention.
Fig. 3 is a schematic structural diagram of a bias generation output module of a multi-protocol IO multiplexing circuit according to a preferred embodiment of the invention.
Fig. 4 is a schematic structural diagram of an output mode control module of a multi-protocol IO multiplexing circuit according to a preferred embodiment of the invention.
Detailed Description
In order to make the contents of the present invention more comprehensible, the present invention is further described below with reference to the accompanying drawings. The invention is of course not limited to this particular embodiment, and general alternatives known to those skilled in the art are also covered by the scope of the invention.
In the following detailed description of the embodiments of the present invention, in order to clearly illustrate the structure of the present invention and to facilitate explanation, the structure shown in the drawings is not drawn to a general scale and is partially enlarged, deformed and simplified, so that the present invention should not be construed as limited thereto.
To make the objects, technical solutions and advantages of the present invention clearer, the following describes a specific embodiment of the present invention in detail with reference to fig. 1 and fig. 2, where fig. 1 is a schematic structural diagram of a multi-protocol IO multiplexing circuit according to a preferred embodiment of the present invention, and fig. 2 is a schematic structural diagram of an output driving module of a multi-protocol IO multiplexing circuit according to a preferred embodiment of the present invention.
As shown in fig. 1, a schematic structural diagram of a multi-protocol IO multiplexing circuit according to a preferred embodiment of the present invention includes an output driving module 1, a mode control module 3, and a bias generation module 2, wherein one side of the output driving module 1 is connected to the mode control module 3 and the bias generation module 2, and the other side outputs driving signals, and the driving signals include a first driving signal OP and a second driving signal ON. The output driving module 1 is provided with a pull-up input end, a pull-down input end, a first digital input end, a second digital input end, a first driving output end and a second driving output end, wherein the first driving output end outputs the first driving signal OP, and the second driving output end outputs the second driving signal ON.
The bias generation module 2 is connected to the output driving module 1 through a two-way selection circuit, one side of the bias generation module 2 inputs an analog reference signal, the other side of the bias generation module outputs an analog feedback signal to the two-way selection circuit, the two-way selection circuit outputs a bias signal to the output driving module 1 according to the analog feedback signal, the bias signal comprises an up bias signal VBP and a down bias signal VBN, the up input end inputs the up bias signal VBP, and the down input end inputs the down bias signal VBN.
The output driving module 1 switches output modes according to the bias signal, wherein the output modes include a differential mode and a single-ended mode. The differential mode is a high-speed differential output mode, and the single-ended mode is a low-speed single-ended output mode. Output drive module 1 includes pull-up branch road and drop-down branch road, the pull-up branch road includes the pull-up transistor, the drop-down branch road includes the drop-down transistor, the grid of pull-up transistor is connected the pull-up input, the grid of drop-down transistor is connected the drop-down input.
One side of the mode control module 3 is connected to a control node M, and the other side outputs a digital signal to the output driving module 1, the digital signal controls the output polarity of the driving signal, the digital signal includes a first digital signal INP and a second digital signal INN, wherein the first digital signal INP controls the polarity of the first driving signal OP, the second digital signal INN controls the polarity of the second driving signal ON, the first digital input end is connected to the first digital signal INP, and the second digital input end is connected to the second digital signal INN.
The bias generation module 2 is provided with a pull-up reference input end, a pull-down reference input end, a pull-up feedback output end and a pull-down feedback output end, and the two-way selection circuit comprises a pull-up two-way alternative selector and a pull-down two-way alternative selector. One side of the bias generation module 2 inputs an analog reference signal, and the other side is respectively connected with a pull-up two-way alternative selector and a pull-down two-way alternative selector. The bias generation module 2 outputs an analog feedback signal to the two-way selection circuit according to the analog reference signal. The analog reference signals include a pull-up analog reference signal VREF _ H and a pull-down analog reference signal VREF _ L, and the analog feedback signals include a pull-up analog feedback signal VBP _ FB and a pull-down analog feedback signal VBN _ FB.
The pull-up reference input end is connected to the pull-up analog reference signal VREF _ H, and the pull-down reference input end is connected to the pull-down analog reference signal VREF _ L. The first pull-up input end of the pull-up two-way alternative selector is connected with the pull-up feedback output end and is connected with a pull-up analog feedback signal VBP _ FB, the second pull-up input end is connected with the first potential FIX _ H, the pull-up output end is connected with the pull-up input end and outputs the pull-up bias signal VBP, and the pull-up control end is connected with the control node M. The first pull-down input end of the pull-down two-way alternative selector is connected with the pull-down feedback output end and connected with a pull-down analog feedback signal VBN _ FB, the second pull-down input end is connected with a second potential FIX _ L, the pull-down output end is connected with the pull-down input end and outputs the pull-down bias signal VBN, and the pull-down control end is connected with the control node M.
The bias generation module 2 includes an output replica circuit, a pull-up negative feedback loop, and a pull-down negative feedback loop, where the output replica circuit replicates the output driving module 1 in equal proportion, and obtains a high dc operating point of the first driving signal OP and a low dc operating point of the second driving signal ON, where the high dc operating point represents a high potential of the first driving signal OP, and the low dc operating point represents a low potential of the second driving signal ON. The pull-up negative feedback loop automatically adjusts the pull-up bias voltage by comparing the high direct current operating point with the pull-up analog reference voltage, and the pull-down negative feedback loop automatically adjusts the pull-down bias voltage by comparing the low direct current operating point with the pull-down analog reference voltage.
One side of the pull-up negative feedback loop is connected with the pull-up reference input end and is accessed to a pull-up analog reference signal VREF _ H, the pull-up analog reference signal and the high direct current working point are compared, a pull-up analog feedback signal VBP _ FB is output to a pull-up feedback output end, one side of the pull-down negative feedback loop is connected with the pull-down reference input end and is accessed to a pull-down analog reference signal VREF _ L, and the pull-down analog reference signal and the low direct current working point are compared, and a pull-down analog feedback signal VBN _ FB is output to the pull-down feedback output end.
As shown in fig. 1, the control end of the pull-up two-way selector and the control end of the pull-down two-way controller are both connected to the control node M, the control node M is connected to a MODE control signal MODE _ CTR, when the MODE control signal MODE _ CTR is at a high potential, the differential MODE is a high-speed signal transmission MODE, the bias generation module 2 is in an ON state, the pull-up two-way selector outputs the pull-up bias signal VBP to the gate of the pull-up transistor, the pull-down two-way selector outputs the pull-down bias signal VBN to the gate of the pull-down transistor, the pull-up transistor and the pull-down transistor are in a saturation region, and the first drive signal OP and the second drive signal ON are low swing differential signals. When the MODE control signal MODE _ CTR is a low potential, the single-ended MODE is a low-speed signal transmission MODE, the bias generation module 2 is in an off state, the pull-up output end of the pull-up two-way one-choice selector outputs a first potential FIX _ H, the pull-down output end of the pull-down two-way one-choice selector outputs a second potential FIX _ L, the gate of the pull-up transistor is set to be low, the gate of the pull-down transistor is set to be high, the pull-up transistor and the pull-down transistor operate in a linear region, and the potentials of the first drive signal and the second drive signal are full swing signals.
The first potential FIX _ H is a ground potential, and the second potential FIX _ L is a power point position; or, the first potential FIX _ H is a power supply potential, and the second potential FIX _ L is a ground potential. In the high-speed interface electrical standard, a differential swing VOD and a common mode voltage VCM are generally defined, corresponding to an output voltage with a high voltage level of VCM + VOD/2 and a low voltage level of VCM-VOD/2. The VCM and VOD defined by different high-speed interface protocols are different, so long as the voltage VREF _ H of the pull-up analog reference signal VREF _ H is VCM + VOD/2, and the voltage VREF _ L of the pull-down analog reference signal VREF _ L is VCM-VOD/2, the voltage of the output pull-up bias signal and the voltage of the pull-down bias signal meet the interface-related electrical standard requirements through the pull-up negative feedback loop and the pull-down negative feedback loop in the bias generation circuit 2. Meanwhile, in the single-ended mode, the bias generation module 2 is in a sleep state to save power consumption.
The mode control module 3 is provided with a control input end, a first input end, a second input end, a third input end, a first output end and a second output end, the control input end is connected with the control node M, the control node M is connected with a mode control signal, the first input end is connected with a first control signal, the second input end is connected with a second control signal, the third input end is connected with a third control signal, the first output end is connected with the first digital input end, the second output end is connected with the second digital input end, wherein the first control signal and the second control signal are low-speed single-ended bit signals, and the third control signal is a high-speed differential signal.
Fig. 2 is a schematic structural diagram of an output driving module of a multi-protocol IO multiplexing circuit according to a preferred embodiment of the invention. The output driving module 1 comprises a pull-up branch and a pull-down branch, the pull-up branch further comprises a first pull-up differential switch and a second pull-up differential switch, and the pull-down branch further comprises a first pull-down differential switch and a second pull-down differential switch. The first digital signal controls the first pull-up differential switch and the first pull-down differential switch to be switched on or off, and the second digital signal controls the second pull-up differential switch and the second pull-down differential switch to be switched on or off. The first pull-up differential switch and the first pull-down differential switch are PMOS transistors, and the second pull-up differential switch and the second pull-down differential switch are NMOS transistors; or, the first pull-up differential switch and the first pull-down differential switch are NMOS transistors, and the second pull-up differential switch and the second pull-down differential switch are PMOS transistors.
In the present embodiment, the first pull-up differential switch is a first pull-up differential transistor SW _ P1, the second pull-up differential switch is a second pull-up differential transistor SW _ P2, the first pull-down differential switch is a first pull-down differential transistor SW _ N1, and the second pull-up differential switch is a second pull-up differential transistor SW _ N2; the gates of the first pull-up differential transistor SW _ P1 and the first pull-down differential transistor SW _ N1 are commonly connected to the first digital input, the gates of the second pull-up differential transistor SW _ P2 and the second pull-down differential transistor SW _ N2 are commonly connected to the second digital input, wherein: the source of the pull-up transistor PM0 is connected to the power supply VDDA, the gate is connected to the pull-up input terminal, the pull-up bias signal VBP is connected to the gate of the pull-up transistor PM0, and the drain is commonly connected to the source of the first pull-up differential transistor SW _ P1 and the source of the second pull-up differential transistor SW _ P2; the gate of the first pull-up differential transistor SW _ P1 is connected to the first digital input terminal, the first digital signal INP is connected to the gate of the first pull-up differential transistor SW _ P1, the drain of the first pull-up differential transistor SW _ P1 is connected to the first end of a first resistor R1, the second end of the first resistor R1 is connected to the first driving output terminal, the first driving output terminal is used for outputting a first driving signal OP, a first node is arranged between the second end of the first resistor R1 and the first driving output terminal, the anode of the first diode and the cathode of the second diode are connected to the first node in common, the cathode of the first diode is connected to the power supply VDDA, and the anode of the second diode is grounded (VSSA); the gate of the second pull-up differential transistor SW _ P2 is connected to the second digital input terminal, the second digital signal INN is connected to the gate of the second pull-up differential transistor SW _ P2, the drain of the second pull-up differential transistor SW _ P2 is connected to the first end of a second resistor R2, the second end of the second resistor R2 is connected to the second driving output terminal, the second driving output terminal is used for outputting a second driving signal ON, a second node is arranged between the second end of the second resistor R2 and the second driving output terminal, the anode of a third diode and the cathode of a fourth diode are connected to the second node in common, the cathode of the third diode is connected to the power supply VDDA, and the anode of the fourth diode is grounded (VSSA); a source of the pull-down transistor NM0 is connected to a power supply VDDA, a gate thereof is connected to the pull-down input terminal, the second bias signal VBN is connected to a gate of the pull-down transistor NM0, and a drain of the pull-down transistor NM0 is commonly connected to a source of the first pull-down differential transistor SW _ N1 and a source of the second pull-up differential transistor SW _ N2; the gate of the first pull-down differential transistor SW _ N1 is connected to the first digital input terminal, the first digital signal INP is connected to the gate of the first pull-down differential transistor SW _ N1, the drain of the first pull-down differential transistor SW _ N1 and the drain of the first pull-up differential transistor SW _ N2 are commonly connected to the first end of the first resistor R1, the gate of the second pull-up differential transistor SW _ N2 is connected to the second digital input terminal, the second digital signal INN is connected to the gate of the second pull-down differential transistor SW _ N2, and the drain of the second pull-up differential transistor SW _ P2 and the drain of the second pull-down differential transistor SW _ N2 are commonly connected to the first end of the second resistor R2. In one embodiment, the pull-up transistor PM0, first pull-up differential transistor SW _ P1, and second pull-up differential transistor SW _ P2 are NMOS transistors; the pull-down transistor NM0, the first pull-down differential transistor SW _ N1 and the second pull-up differential transistor SW _ N2 are PMOS transistors; in another embodiment, the pull-up transistor PM0, first pull-up differential transistor SW _ P1, and second pull-up differential transistor SW _ P2 are PMOS transistors; the pull-down transistor NM0, the first pull-down differential transistor SW _ N1, and the second pull-up differential transistor SW _ N2 are NMOS transistors.
In the high-speed differential output mode, the pull-up two-way alternative selector selects to output the pull-up analog feedback signal VBP _ FB to the pull-up input terminal, that is, the pull-up bias signal VBP is the pull-up analog feedback signal VBP _ FB, the pull-down two-way alternative selector selects to output the pull-down analog feedback signal VBN _ FB to the pull-down input terminal, that is, the pull-down bias signal VBN is the pull-down analog feedback signal VBN _ FB, and the pull-up transistor PM0 and the pull-down transistor NM0 both operate in a saturation region and are equivalent to a tail current source; the first pull-up differential transistor SW _ P1, the second pull-up differential transistor SW _ P2, the first pull-down differential transistor SW _ N1 and the second pull-down differential transistor SW _ N2 all operate in a linear region, which is equivalent to a switching device, wherein when the gate voltage is low, the first pull-up differential transistor SW _ P1 and the second pull-up differential transistor SW _ P2 are in an on state; when the gate voltage is a high level, the first pull-down differential transistor SW _ N1 and the second pull-down differential transistor SW _ N2 are turned ON, otherwise, the first pull-down differential transistor SW _ N1 and the second pull-down differential transistor SW _ N2 are turned off, and the potentials of the first driving signal OP and the second driving signal ON are low swing differential signals.
In the low-speed single-ended mode, the bias generation module 2 is in an off state, the outputs of the pull-up two-way selector and the pull-down two-way selector are respectively pulled to a fixed value, the pull-up two-way one-way selector selects and outputs the first potential FIX _ H, and the pull-down two-way selector selects and outputs the second potential FIX _ L. In an embodiment, the first potential FIX _ H is a ground potential, the second potential FIX _ L is a power point, the pull-up bias signal VBP is a ground potential, the pull-down bias signal VBN is a power point, the pull-up transistor PM0 and the pull-down transistor NM0 both operate in a linear region, and may be equivalent to a conducting switch, and the potentials of the first driving signal OP and the second driving signal ON are full-swing signals. In another embodiment, the first potential FIX _ H is a power supply potential, the second potential FIX _ L is a ground potential, the pull-up bias signal VBP is a power supply point, the pull-down bias signal VBN is a ground potential, the pull-up transistor PM0 and the pull-down transistor NM0 are both in an off region, which is equivalent to an open switch, the pull-up branch and the pull-down branch of the output driving module 1 are both open, and the output is in a high-resistance state, which is equivalent to a buffer circuit with enable control.
As shown in fig. 3, fig. 3 is a schematic structural diagram of a bias generation output module 3 of a multi-protocol IO multiplexing circuit according to a preferred embodiment of the invention. The output stage replica circuit includes a first replica transistor PM0_ cp, a second replica transistor PM1, a third replica transistor NM1, a fourth replica transistor NM0_ cp, a first replica resistor r1, a second replica resistor r _ term, and a third replica resistor r2, the pull-up negative feedback loop includes a pull-up amplifier, and the pull-down negative feedback loop includes a pull-down amplifier; the source of the first replica transistor PM0_ cp is connected to the power supply VDDA, the gate is connected to the output terminal of the pull-up amplifier, and the drain is connected to the source of the second replica transistor PM 1; a gate of the second replica transistor PM1 is grounded (VSSA), a drain is connected to a first terminal of the first replica resistor r1, a second terminal of the first replica resistor r1 and a first terminal of the second replica resistor r _ term are commonly connected to a reverse input terminal of the pull-up amplifier, a forward input terminal of the pull-up amplifier is connected to the pull-up analog reference signal VREF _ H, an output terminal outputs a pull-up analog feedback signal to a gate of the first replica transistor PM0_ cp, a second terminal of the second replica resistor r _ term and a first terminal of the third replica resistor r2 are commonly connected to a forward input terminal of the pull-down amplifier, a reverse input terminal of the pull-down amplifier is connected to the pull-down analog reference signal VREF _ L, an output terminal outputs a pull-down analog feedback signal to a gate of the fourth transistor, a second terminal of the third replica resistor r2 is connected to a drain of the third replica transistor NM1, a gate of third replica transistor NM1 is connected to the power supply VDDA, a source thereof is connected to the drain of fourth replica transistor NM0_ cp, a source thereof is grounded, and a gate thereof is connected to an output terminal of the pull-down amplifier. In the present embodiment, the first replica transistor PM0_ cp and the second replica transistor PM1 are PMOS transistors, and the third replica transistor NM1 and the fourth replica transistor NM0_ cp are NMOS transistors; in another embodiment, the first replica transistor PM0_ cp and the second replica transistor PM1 are NMOS transistors, and the third replica transistor NM1 and the fourth replica transistor NM0_ cp are PMOS transistors.
In the high-speed differential output mode, since the pull-up bias signal is a pull-up analog feedback signal, i.e. VBP ═ VBP _ FB, the first replica transistor PM0_ cp is a replica of the pull-up transistor PM0 in the output driver module 1; in the low-speed single-ended mode, the bias generating module 2 is in an off state, the gate of the second replica transistor PM1 is set to be low, the pull-up negative feedback loop replicates the first pull-up differential transistor SW _ P1 and the second pull-up differential transistor SW _ P1 in the output driving module 1, the first replica resistor R1 and the third replica resistor R2 are replicates the first resistor R1 and the second resistor R2 in the output driving module 2, and the second replica resistor R _ term is replicate the termination resistor of the high-speed differential interface; the gate of the third replica transistor NM1 is set high, the pull-down negative feedback loop replicates the first and second pull-down and pull-up differential transistors SW _ N1 and SW _ N2 in the output driving module 1, the source of the fourth replica transistor NM0_ cp is grounded, and the fourth replica transistor NM0_ cp replicates the pull-down transistor in the output driving module 1. In a normal operating state, the quiescent operating current of the output driver module 1 is in milliampere magnitude, and in order to save power consumption of the replica circuit, the device sizes of the transistors in the output stage replica circuit are set according to a certain proportion of the device sizes of the corresponding transistors in the output driver module 1, wherein the widths of the devices PM0_ cp/PM1/NM0_ cp/NM1 are respectively 1/k times of the corresponding replica devices in the output driver circuit 1, and correspondingly, the values of r1/r2/r _ term are k times of the corresponding replica devices in the output driver circuit 1.
As shown in fig. 4, fig. 4 is a schematic structural diagram of an output mode control module of a multi-protocol IO multiplexing circuit according to a preferred embodiment of the invention. The control signal input end is connected with the control node MODE _ CTR, the first control input end is accessed with a first control signal SG _ IN <0>, the second control input end is accessed with a second control signal SG _ IN <1>, the third control input end is accessed with a third control signal DIF _ IN, the first control output end is accessed with the first digital input end, the second control output end is accessed with the second digital input end, the first control signal SG _ IN <0> and the second control signal SG _ IN <1> are single-ended bit signals with low speed, and the third control signal DIF _ IN is a differential signal with high speed.
The mode control module 3 comprises a first inverter, a second inverter, a third inverter, a fourth inverter, a first mode selector and a second mode selector, wherein the input end of the first inverter is connected with the first control input end, the output end of the first inverter is connected with the first selection input end of the first mode selector MUX _0, the input end of the second inverter is connected with the second control input end, the output end of the second inverter is connected with the first selection input end of the second mode selector MUX _1, the input end of the third inverter is connected with the third control input end, the output end of the third inverter is connected with the input end of the fourth inverter, and the output end of the fourth inverter is connected with the second selection input end of the second mode selector MUX _ 1; a second selection input terminal of the first mode selector MUX _0 is connected to the input terminal of the fourth inverter and receives an inverted signal of the third control signal, a control terminal of the first mode selector MUX _0 and a control terminal of the second mode selector MUX _1 are commonly connected to the control node, an output terminal of the first mode selector MUX _1 is connected to the first control output terminal and outputs the first digital signal INP, and an output terminal of the second mode selector MUX _1 is connected to the second control output terminal and outputs the second digital signal INN.
And switching of digital signals in different MODEs is realized through the MODE control signal MODE _ CTR. In the low-speed single-ended mode, the first control output end outputs the first control signal to the first digital input end, the second control output end outputs the second control signal to the second digital input end, and the output driving module 1 is equivalent to a buffer circuit with enable control. In this mode, INP/INN are two independent signals, and are controlled by the mode selection circuit 3 to satisfy
In a high-speed differential output mode, the third controlA control output terminal outputs the third control signal,
INN＝DIFF_IN。
the multi-protocol IO multiplexing circuit prepared based on the method realizes that the same output drive circuit is used for realizing a low-speed single-ended drive mode and a high-speed differential drive mode, an interface circuit using the structure can simultaneously meet the requirements of different application platforms on a serial interface and a parallel interface, because the output drive circuit generally needs to drive a larger load, in order to meet the requirement of interface speed, a current of a few milliamperes needs to be provided, the size is generally larger, and in terms of MOS devices, the drain parasitic capacitance of an output MOS device generally reaches the pF magnitude, so that the highest transmission speed which can be supported by the interface is severely limited if a plurality of output IOs are connected in parallel. The invention realizes the support of various interface modes and electrical standards under the condition of not additionally connecting the IO driving circuit in parallel by mode control of the same IO circuit, greatly reduces the parasitic capacitance of the output end, is beneficial to ensuring the interface speed, greatly reduces the area of the IO circuit, is an IO driving circuit structure with low cost, high speed and high compatibility, and has obvious significance.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (10)
1. A multi-protocol IO multiplexing circuit, comprising:
the output driving module is provided with a pull-up input end, a pull-down input end, a first digital input end, a second digital input end, a first driving output end and a second driving output end, the output driving module comprises a pull-up branch and a pull-down branch, the pull-up branch comprises a pull-up transistor, the pull-down branch comprises a pull-down transistor, a grid electrode of the pull-up transistor is connected with the pull-up input end and is connected with a pull-up bias signal, a grid electrode of the pull-down transistor is connected with the pull-down input end and is connected with a pull-down bias signal, the first driving output end outputs a first driving signal, and the second driving output end outputs a second driving signal;
the bias generation module is provided with a pull-up reference input end, a pull-down reference input end, a pull-up feedback output end and a pull-down feedback output end and comprises an output replication circuit, a pull-up negative feedback loop and a pull-down negative feedback loop, wherein the output replication circuit replicates the output driving module in equal proportion to obtain a high direct current working point of a first driving signal and a low direct current working point of a second driving signal; one side of the pull-up negative feedback loop is connected with the pull-up reference input end and is accessed with a pull-up analog reference signal, the pull-up analog reference signal and the high direct current working point are compared, and a pull-up analog feedback signal is output to a pull-up feedback output end, one side of the pull-down negative feedback loop is connected with the pull-down reference input end and is accessed with a pull-down analog reference signal, the pull-down analog reference signal and the low direct current working point are compared, and a pull-down analog feedback signal is output to the pull-down feedback output end;
a first pull-up input end of the pull-up two-way one-choice selector is connected with the pull-up feedback output end, a second pull-up input end of the pull-up two-way one-choice selector is connected with a first potential, a pull-up output end of the pull-up two-way one-choice selector is connected with the pull-up input end, and a pull-up control end of the pull-up two-way one-choice selector is connected with a;
a first pull-down input end of the pull-down two-way selector is connected with the pull-down feedback output end, a second pull-down input end is connected with a second potential, a pull-down output end is connected with the pull-down input end, and a pull-down control end is connected with the control node;
the mode control module is provided with a control input end, a first input end, a second input end, a third input end, a first output end and a second output end, the control input end is connected with the control node, the control node is connected with a mode control signal, the first input end is connected with a first control signal, the second input end is connected with a second control signal, the third input end is connected with a third control signal, the first output end is connected with the first digital input end, the second output end is connected with the second digital input end, the first control signal and the second control signal are low-speed single-ended bit signals, and the third control signal is a high-speed differential signal.
2. The multi-protocol IO multiplexing circuit of claim 1, wherein the mode control signal is a low potential, the bias generation module is in an off state, the pull-up output outputs a first potential, the pull-down output outputs a second potential, a gate of the pull-up transistor is set low, a gate of the pull-down transistor is set high, the pull-up transistor and the pull-down transistor are in linear region operation, and potentials of the first driving signal and the second driving signal are full swing signals.
3. The multi-protocol IO multiplexing circuit of claim 2, wherein the first potential is a ground potential and the second potential is a power supply point; or, the first potential is a power supply potential, and the second potential is a ground potential.
4. The multi-protocol IO multiplexing circuit of claim 1, wherein the mode control signal is a high level, the bias generation module is in an on state, the pull-up output terminal outputs the pull-up analog feedback signal, the pull-down output terminal outputs the pull-down analog feedback signal, the pull-up transistor and the pull-down transistor are in a saturation region, and the first driving signal and the second driving signal are low swing differential signals.
5. The multi-protocol IO multiplexing circuit of claim 1, wherein the pull-up leg further comprises a first pull-up differential switch and a second pull-up differential switch, and the pull-down leg further comprises a first pull-down differential switch and a second pull-down differential switch; the first control signal controls the first pull-up differential switch and the first pull-down differential switch to be connected or disconnected, and the second control signal controls the second pull-up differential switch and the second pull-down differential switch to be connected or disconnected.
6. The multi-protocol IO multiplexing circuit of claim 5, wherein the first pull-up differential switch is a first pull-up differential transistor, the second pull-up differential switch is a second pull-up differential transistor, the first pull-down differential switch is a first pull-down differential transistor, the second pull-up differential switch is a second pull-up differential transistor, a gate of the first pull-up differential transistor and a gate of the first pull-down differential transistor are commonly connected to the first digital input, a gate of the second pull-up differential transistor and a gate of the second pull-down differential transistor are commonly connected to the second digital input, wherein: the source electrode of the pull-up transistor is connected with a power supply, the grid electrode of the pull-up transistor is connected with the pull-up input end, and the drain electrode of the pull-up transistor is connected with the source electrode of the first pull-up differential transistor and the source electrode of the second pull-up differential transistor; the drain electrode of the first pull-up differential transistor is connected with a first end of a first resistor, a second end of the first resistor is connected with the first driving output end, a first node is arranged between the second end of the first resistor and the first driving output end, the anode of a first diode and the cathode of a second diode are connected to the first node together, the cathode of the first diode is connected with the power supply, and the anode of the second diode is grounded; the drain electrode of the second pull-up differential transistor is connected with the first end of a second resistor, the second end of the second resistor is connected with the second driving output end, a second node is arranged between the second end of the second resistor and the second driving output end, the anode of a third diode and the cathode of a fourth diode are connected to the second node together, the cathode of the third diode is connected with the power supply, and the anode of the fourth diode is grounded; the source electrode of the pull-down transistor is connected with a power supply, the grid electrode of the pull-down transistor is connected with the pull-down input end, and the drain electrode of the pull-down transistor is connected with the source electrode of the first pull-down differential transistor and the source electrode of the second pull-up differential transistor; the drain of the first pull-down differential transistor and the drain of the first pull-up differential transistor are commonly connected to the first end of the first resistor, and the drain of the second pull-down differential transistor and the drain of the second pull-up differential transistor are commonly connected to the first end of the second resistor.
7. The multi-protocol IO multiplexing circuit of claim 6, wherein the pull-up transistor, first pull-up differential transistor, and second pull-up differential transistor are PMOS transistors, and the pull-down transistor, first pull-down differential transistor, and second pull-up differential transistor are NMOS transistors; or the pull-up transistor, the first pull-up differential transistor and the second pull-up differential transistor are NMOS transistors, and the pull-down transistor, the first pull-down differential transistor and the second pull-up differential transistor are PMOS transistors.
8. The multi-protocol IO multiplexing circuit of claim 6, wherein the output stage replica circuit comprises a first replica transistor, a second replica transistor, a third replica transistor, a fourth replica transistor, a first replica resistor, a second replica resistor, and a third replica resistor, the pull-up negative feedback loop comprises a pull-up amplifier, and the pull-down negative feedback loop comprises a pull-down amplifier; the source of the first replica transistor is connected with the power supply, the gate is connected with the output end of the pull-up amplifier, the drain is connected with the source of the second replica transistor, the gate of the second replica transistor is grounded, the drain is connected with the first end of the first replica resistor, the second end of the first replica resistor and the first end of the second replica resistor are connected with the reverse input end of the pull-up amplifier, the forward input end of the pull-up amplifier is connected with the pull-up analog reference signal, the output end outputs a pull-up analog feedback signal to the first replica transistor, the second end of the second replica resistor and the first end of the third replica resistor are connected with the forward input end of the pull-down amplifier, the reverse input end of the pull-down amplifier is connected with the pull-down analog reference signal, and the output end outputs a pull-down analog feedback signal to the fourth replica transistor, the second end of the third replication resistor is connected with the drain electrode of the third replication transistor, the grid electrode of the third replication transistor is connected with the power supply, the source electrode of the third replication transistor is connected with the drain electrode of the fourth replication transistor, the source electrode of the fourth replication transistor is grounded, and the grid electrode of the fourth replication transistor is connected with the output end of the pull-down amplifier.
9. The multi-protocol IO multiplexing circuit of claim 8, wherein the first replica transistor replicates the pull-up transistor in equal proportion, the first replica resistor replicates the first resistor in equal proportion, the second replica transistor replicates the second resistor in equal proportion, and the fourth replica transistor replicates the pull-down transistor in equal proportion.
10. The multi-protocol IO multiplexing circuit of claim 6, wherein the mode control module comprises a first inverter, a second inverter, a third inverter, a fourth inverter, a first mode selector, and a second mode selector, wherein an input of the first inverter is connected to the first input, an output of the first inverter is connected to the first selection input of the first mode selector, an input of the second inverter is connected to the second input, an output of the second inverter is connected to the first selection input of the second mode selector, an input of the third inverter is connected to the third input, an output of the third inverter is connected to an input of the fourth inverter, and an output of the fourth inverter is connected to the second selection input of the second mode selector; the second selection input end of the first mode selector is connected with the output end of the third phase inverter, the control end of the first mode selector and the control end of the second mode selector are connected to the control input end together, the output end of the first mode selector is connected with the first output end, and the output end of the second mode selector is connected with the second output end.
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| CN115065358A (en) * | 2022-07-26 | 2022-09-16 | 广东高云半导体科技股份有限公司 | IO driving circuit and chip |
| CN115065358B (en) * | 2022-07-26 | 2024-05-17 | 广东高云半导体科技股份有限公司 | IO driving circuit and chip |
| CN116561035A (en) * | 2023-07-07 | 2023-08-08 | 西安智多晶微电子有限公司 | Method and device for two-way communication between FPGA and MIPI and electronic equipment |
| CN116561035B (en) * | 2023-07-07 | 2023-10-31 | 西安智多晶微电子有限公司 | Method and device for two-way communication between FPGA and MIPI and electronic equipment |
| CN117097326A (en) * | 2023-10-19 | 2023-11-21 | 四川艾瑞维尔科技有限公司 | Driving circuit compatible with LVDS and HCSL level standards |
| CN117097326B (en) * | 2023-10-19 | 2023-12-22 | 四川艾瑞维尔科技有限公司 | Driving circuit compatible with LVDS and HCSL level standards |
| CN117831590A (en) * | 2024-01-04 | 2024-04-05 | 上海奎芯集成电路设计有限公司 | Multi-mode memory driving circuit and multi-protocol interface compatible PHY chip |
| CN117831590B (en) * | 2024-01-04 | 2024-05-28 | 上海奎芯集成电路设计有限公司 | Multi-mode memory driving circuit and multi-protocol interface compatible PHY chip |
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| Publication number | Publication date |
|---|---|
| CN112564689B (en) | 2024-05-28 |
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