CN117831590A - Multi-mode memory driving circuit and multi-protocol interface compatible PHY chip - Google Patents
Multi-mode memory driving circuit and multi-protocol interface compatible PHY chip Download PDFInfo
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Abstract
The invention provides a multi-mode memory driving circuit and a multi-protocol interface compatible PHY chip, which form the multi-mode memory driving circuit through a high-speed level shifter array, a high-speed multi-mode selector, a pull-up driving array and a pull-down driving array, utilize the high-speed level shifter array to output a first output signal positioned in a first voltage domain and a second output signal positioned in a second voltage domain, utilize the high-speed multi-mode selector to output corresponding first data signals and second data signals based on mode control signals, control the pull-up driving array based on the first data signals and the first output signals positioned in the first voltage domain, control the pull-down driving array based on the second data signals and the second output signals positioned in the second voltage domain, obtain driving signals output by an output end of the driving circuit, can be compatible with different memory interface protocols simultaneously, simultaneously meet the requirements of various memory interface protocols on the memory driving circuit, and remarkably reduce SOC design difficulty and cost.
Description
Technical Field
The present invention relates to the field of memory technologies, and in particular, to a multi-mode memory driving circuit and a multi-protocol interface compatible PHY chip.
Background
With the trend of large Data, cloud computing and artificial intelligence technology towards scale application, memory interface protocols such as DDR (Double Data Rate) memory/protocols and LPDDR (Low Power Double Data Rate, low power consumption Double Data Rate) memory/protocols are continuously accelerated and pushed to develop towards high speed and low power consumption, so that the memory interface protocol specification performs an upgrade iteration every two to three years. For example, DRAM (Dynamic Random-Access Memory) particles currently exist in a variety of different protocols such as DDR3/DDR4/DDR5, LPDDR3/4/5/5X, etc. On the commercial market, and each generation of interface specifications is continuously changed, resulting in different ODT (On-Die-terminator) modes, interface voltages, and transmission speeds. However, most of the existing memory driving circuits only support one to two specific memory interface protocols, so that the difficulty of simultaneously adapting the SOC (System On Chip) main control Chip to the memories of different interface protocols is continuously increased, and the production cost is obviously increased.
Disclosure of Invention
The invention provides a multi-mode memory driving circuit and a multi-protocol interface compatible PHY chip, which are used for solving the defect that an SOC main control chip is difficult to simultaneously adapt to memories with different interface protocols in the prior art.
The present invention provides a multi-mode memory driving circuit, comprising:
a high speed level shifter array, a high speed multimode selector, a pull-up drive array, and a pull-down drive array;
the high-speed level shifter array is used for outputting a first output signal in a first voltage domain and a second output signal in a second voltage domain based on an input signal in an initial voltage domain, a first protection voltage and a second protection voltage; the first voltage domain represents a voltage range from the first protection voltage to a preset power supply voltage, and the second voltage domain represents a voltage range from a preset ground voltage to the second protection voltage;
the high-speed multimode selector is used for outputting corresponding first data signals and second data signals based on a mode control signal, transmitting the first data signals and the first output signals in a first voltage domain to the pull-up driving array, and transmitting the second data signals and the second output signals in a second voltage domain to the pull-down driving array, wherein the preset power supply voltage, the preset ground voltage and the mode control signal are determined based on a current interface protocol;
the pull-up driving array is connected with the output end of the pull-down driving array and is used for outputting driving signals.
According to the multi-mode memory driving circuit provided by the invention, the first data signal is used for controlling the opening and closing of the pull-up driving array, and is used for controlling the number of the pull-up driving units which are opened in the pull-up driving array when the pull-up driving array is opened; the number of the turned-on pull-up driving units in the pull-up driving array is determined based on an interface protocol indicated by the mode control signal;
the second data signal is used for controlling the opening and closing of the pull-down driving array, and is used for controlling the number of pull-down driving units which are opened in the pull-down driving array when the pull-down driving array is opened; the number of turned-on pull-down driving units in the pull-down driving array is determined based on an interface protocol indicated by the mode control signal;
the mode control signal is used for indicating a low power consumption mode, an ODT mode corresponding to different interface protocols or a driving mode corresponding to different interface protocols.
According to the present invention there is provided a multimode memory drive circuit, the high speed multimode selector being particularly for:
outputting a first data signal and a second data signal to turn off the pull-up driving array based on the first data signal and to turn off the pull-down driving array based on the second data signal when the mode control signal indicates a low power consumption mode;
when the mode control signal indicates an ODT mode corresponding to any interface protocol, outputting a first data signal and a second data signal based on the any interface protocol so as to control the pull-up driving array and the pull-down driving array, and determining the connection mode of an ODT terminal based on the any interface protocol;
when the mode control signal indicates a driving mode corresponding to any interface protocol, outputting a first data signal and a second data signal to start the pull-up driving array based on the first data signal and start the pull-down driving array based on the second data signal; the number of the pull-up driving units started in the pull-up driving array and/or the number of the pull-down driving units started in the pull-down driving array is determined based on any interface protocol.
According to the multi-mode memory driving circuit provided by the invention, the high-speed level shifter array comprises a preset number of high-speed level shifters, and each high-speed level shifter comprises a first level shifting unit and a second level shifting unit which are identical in structure; the first level conversion unit is used for outputting a first output signal in a first voltage domain based on an input signal of an initial voltage domain and a first protection voltage; the second level conversion unit is used for outputting a second output signal in a second voltage domain based on the input signal of the initial voltage domain and a second protection voltage.
According to the present invention, there is provided a multi-mode memory driving circuit, the first level shift unit or the second level shift unit including:
an input voltage domain inverter, an ac coupling capacitor, an output voltage domain latch, and a controllable dc level path;
wherein the input signal is connected with the input voltage domain inverter; the output end of the input voltage domain inverter is connected with the input end of the alternating current coupling capacitor and the input end of the controllable direct current level channel; the output end of the alternating current coupling capacitor and the output end of the controllable direct current level channel are connected with the input end of the output voltage domain latch; the output voltage domain latch consists of two output voltage domain inverters with input and output being in short circuit with each other; the output voltage domain inverter of the first level conversion unit is connected with the first protection voltage and the preset power supply voltage, and the output voltage domain inverter of the second level conversion unit is connected with the preset ground voltage and the second protection voltage.
According to the multi-mode memory driving circuit provided by the invention, the pull-up driving array comprises a preset number of pull-up driving units, and the pull-down driving array comprises a preset number of pull-down driving units;
the pull-up driving unit is formed by connecting a first transistor, a second transistor and a pull-up resistor in series; the pull-down driving unit is formed by connecting a third transistor, a fourth transistor and a pull-down resistor in series;
the source electrode of the first transistor is connected with the preset power supply voltage, the drain electrode of the first transistor is connected with the source electrode of the second transistor, the drain electrode of the second transistor is connected with the pull-up resistor, and the other end of the pull-up resistor is the output end of the pull-up driving unit; the control end of the first transistor is connected with the first data signal, and the control end of the second transistor is connected with the first protection voltage;
the source electrode of the third transistor is connected with the preset ground voltage, the drain electrode of the third transistor is connected with the source electrode of the fourth transistor, and the drain electrode of the fourth transistor is connected with the pull-down resistor; the other end of the pull-down resistor is the output end of the pull-down driving unit; the control end of the third transistor is connected with the second data signal, and the control end of the fourth transistor is connected with the second protection voltage.
According to the multi-mode memory driving circuit provided by the invention, the first transistor and the third transistor are both array-type size-adjustable transistors; the first transistor and the third transistor are transistors of a first conductivity type, and the second transistor and the fourth transistor are transistors of a second conductivity type, the second conductivity type being different from the first conductivity type.
According to the multi-mode memory driving circuit provided by the invention, the first protection voltage is different from the second protection voltage.
The invention also provides a multi-protocol interface compatible PHY chip, which comprises an integrated circuit of any one of the multi-mode memory driving circuits.
According to the multi-protocol interface compatible PHY chip provided by the invention, the multi-protocol interface compatible PHY chip further comprises an integrated circuit of an impedance calibration circuit for performing impedance calibration on the pull-up driving array and the pull-down driving array.
The multi-mode memory driving circuit and the multi-protocol interface compatible PHY chip provided by the invention form the multi-mode memory driving circuit by utilizing the high-speed level shifter array, the high-speed multi-mode selector, the pull-up driving array and the pull-down driving array, and utilize the high-speed level shifter array to output a first output signal positioned in a first voltage domain and a second output signal positioned in a second voltage domain based on an input signal, a first protection voltage and a second protection voltage of an initial voltage domain, and utilize the high-speed multi-mode selector to output corresponding first data signals and second data signals based on a mode control signal, and control the pull-up driving array based on the first data signals and the first output signal positioned in the first voltage domain, and control the pull-down driving array based on the second data signals and the second output signal positioned in the second voltage domain, so that driving signals jointly formed by the output ends of the driving circuit of the pull-up driving array and the pull-down driving array can be compatible with different memory interface protocols such as DDR3/DDR4/DDR5, LPDDR3/4/5/5X and the like, and simultaneously meet the requirements of various memory interfaces on the design of the memory protocols, and the cost of the driving circuit is remarkably reduced.
Drawings
In order to more clearly illustrate the invention or the technical solutions of the prior art, the following description will briefly explain the drawings used in the embodiments or the description of the prior art, and it is obvious that the drawings in the following description are some embodiments of the invention, and other drawings can be obtained according to the drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic diagram of a multi-mode memory driver circuit provided by the present invention;
fig. 2 is a schematic diagram of a structure of a first level shifter unit or a second level shifter unit according to the present invention;
FIG. 3 is an exemplary diagram of voltage, speed, and ODT modes for different memory interface protocols with which the present invention is compatible;
fig. 4 is a schematic structural diagram of a pull-up driving unit and a pull-down driving unit provided by the present invention.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the present invention more apparent, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings, and it is apparent that the described embodiments are some embodiments of the present invention, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
FIG. 1 is a schematic diagram of a multi-mode memory driving circuit according to the present invention, as shown in FIG. 1, the circuit includes: a high speed level shifter array 110, a high speed multimode selector 120, a pull-up drive array 130, and a pull-down drive array 140.
The high-speed level shifter array 110, the high-speed multimode selector 120, the pull-up driving array 130, and the pull-down driving array 140 are compatible with a plurality of different interface voltages. The high-speed level shifter array 110 is used to convert digital signals into voltages required by different interface protocols, and the high-speed multimode selector 120 is used to switch ODT modes, low power modes and driving modes required by different memory interface protocols and control the pull-up driving array 130/pull-down driving array 140 to complete the final signal output. Through compatibility design of various power supply voltages, various ODT modes, driving modes and low-power consumption modes, the requirements of various memory interface protocols on a memory driving circuit can be met, and SOC design difficulty and cost are remarkably reduced.
Specifically, the high-speed level shifter array 110 is an input terminal of the integrated driving circuit, an input signal of an initial voltage domain is connected to the high-speed level shifter array 110, and the high-speed level shifter array 110 outputs a first output signal in a first voltage domain and a second output signal in a second voltage domain based on the input signal of the initial voltage domain, a first protection voltage and a second protection voltage that are externally input. The first voltage domain represents a voltage range from the first protection voltage VPROTL to the preset power voltage VDDQ, the second voltage domain represents a voltage range from the preset ground voltage VSSQ to the second protection voltage VPROTH, and the first protection voltage VPROTL and the second protection voltage VPROTH may be different. The preset power supply voltage VDDQ and the preset ground voltage VSSQ are determined based On the current interface protocol, so that the device can be compatible with various different interface protocols, such as DDR3/DDR4/DDR5, LPDDR3/4/5/5X, etc., so as to meet the transmission requirements of various memory interface levels, such as SSTL (Stub Series Terminated Logic, serial terminal logic), POD (Point-to-Point On-Die Termination), LVSTL (Low Voltage Stub Series Terminated Logic, low voltage serial terminal logic), etc.
In some embodiments, the high-speed level shifter array 110 includes a preset number of high-speed level shifters, each of which includes a first level shifter unit and a second level shifter unit having the same structure. The first level conversion unit is used for outputting a first output signal in a first voltage domain based on an input signal of the initial voltage domain and a first protection voltage VPROTL; the second level converting unit is used for outputting a second output signal in a second voltage domain based on the input signal of the initial voltage domain and a second protection voltage VPROTH.
Fig. 2 is a schematic structural diagram of a first level shifter unit or a second level shifter unit according to the present invention, and as shown in fig. 2, the first level shifter unit or the second level shifter unit includes: an input voltage domain inverter 210, an ac coupling capacitor 220, an output voltage domain latch 230, and a controllable dc level path 240. Wherein, the input signal is connected with the input voltage domain inverter 210, and voltages VDD1 and VSS1 connected with the input voltage domain inverter 210 correspond to the initial voltage domain; the output of the input voltage domain inverter 210 is connected to the input of the ac coupling capacitor 220 and the input of the controllable dc level path 240; the output of ac coupling capacitor 220 and the output of controllable dc level path 240 are both connected to the input of output voltage domain latch 230. The output voltage domain latch 230 is composed of two output voltage domain inverters with inputs and outputs shorted to each other. The output voltage domain inverter of the first level conversion unit is connected with the first protection voltage and the preset power supply voltage, namely voltages VDD2 and VSS2 connected with the output voltage domain inverter are in a first voltage domain; the output voltage domain inverter of the second level shifting unit is connected with a preset ground voltage and a second protection voltage, namely, voltages VDD2 and VSS2 connected with the output voltage domain inverter are in a second voltage domain. Further, the first level shift unit/second level shift unit further includes an enable control access terminal Ctrl for controlling the opening or closing of the controllable dc level path 240.
Specifically, the input signal level is an initial voltage domain, is driven through the input voltage domain inverter 210, is rapidly coupled to the first/second voltage domain through the ac coupling capacitor 220, and is latched by the output voltage domain latch 230, while converting the output signal into the signal level of the first/second voltage domain. It should be noted that the gain of the input voltage domain inverter 210 should be ensured to be greater than that of the output voltage domain latch 230, so that the output signal can break the latch state when the input signal changes and latch the next input signal quickly, and thus the size of the input voltage domain inverter 210 should be greater than that of the output voltage domain inverter where the two input outputs of the output voltage domain latch 230 are shorted to each other. In addition, to ensure that the output of ac coupling capacitor 220 has the correct initial dc level, a suitable enable control signal may be tested to cause the initial level of the input signal to be transferred to the output via the controllable dc level path, thereby completing a high-speed accurate signal level conversion.
Therefore, under the condition that the existing level converter has the problems of single conversion level, slower speed, deterioration of the duty ratio of the converted signal and the like, the alternating-current coupling capacitor is adopted in the embodiment to isolate the input voltage domain from the output voltage domain, meanwhile, the deterioration of the duty ratio performance of the signal can not be caused, multiple modes of low-voltage conversion, high-voltage conversion, low-voltage conversion and the like can be compatible in the range of the safe working voltage of the device, the working speed of the circuit is improved through the output voltage domain latch, and the driving capability of the circuit at the later stage is enhanced.
The output signals of the high-speed level shifter array 110 (i.e., the first output signal in the first voltage domain and the second output signal in the second voltage domain) are connected to the high-speed multimode selector 120, and the high-speed multimode selector 120 is configured to output corresponding first and second data signals based on the mode control signals, transfer the first data signals and the first output signal in the first voltage domain to the pull-up driving array 130, and transfer the second data signals and the second output signal in the second voltage domain to the pull-down driving array 140, so as to control the opening and closing of the pull-up driving array 130 and the pull-down driving array 140 and the number of the specifically opened pull-up/pull-down driving units. Wherein the mode control signal is determined based on the current interface protocol. The output terminals of the pull-up driving array 130 and the pull-down driving array 140 are connected to form an output terminal of the driving circuit together, for outputting driving signals.
FIG. 3 is an exemplary diagram of voltage, speed and ODT modes of different memory interface protocols compatible with the present invention, as shown in FIG. 3, for compatible DDR3 interface protocols, the preset supply voltage VDDQ may be 1.35V or 1.5V, with SSTL level interface drive, the speed is required to be compatible with 1600Mbps to 2133Mbps, and the ODT is required to be terminated to one half of the preset supply voltage; in order to be compatible with DDR4/5 interface protocol, the preset power supply voltage can be 1.2V or 1.1V, POD level interface driving is adopted, the speed is required to be compatible with 3200Mbps to 6400Mbps, and ODT is required to be connected to the preset power supply voltage; in order to be compatible with the LPDDR4/4x/5 interface protocol, the preset power supply voltage can be 1.1V, 0.6V or 0.5V, LVSTL level interface driving is adopted, the speed is required to be compatible with 4266Mbps to 8533Mbps, and the ODT is required to be connected to the preset ground voltage.
In order to be compatible with the requirements of different interface protocols, the high-speed multimode selector 120 outputs respective first and second data signals based on the mode control signal. The mode control signal is used for indicating a low power consumption mode, an ODT mode corresponding to different interface protocols or a driving mode corresponding to different interface protocols; the first data signal is used for controlling the opening and closing of the pull-up driving array 130, and when the pull-up driving array 130 is opened, the first data signal is used for controlling the number of the pull-up driving units opened in the pull-up driving array 130, and the number of the pull-up driving units opened in the pull-up driving array 130 is determined based on the interface protocol indicated by the mode control signal so as to adapt to the regulations of different interface protocols on the transmission speed; the second data signal is used to control the opening and closing of the pull-down driving array 140, and when the pull-down driving array 140 is turned on, the number of pull-down driving units turned on in the pull-down driving array 140 is also determined based on the interface protocol indicated by the mode control signal, so as to adapt to the regulations of different interface protocols on the transmission speed.
In some embodiments, when the mode control signal indicates the low power mode, the high-speed multimode selector 120 outputs the first data signal and the second data signal to turn off the pull-up driving array 130 based on the first data signal and turn off the pull-down driving array 140 based on the second data signal, so that the output terminals of the whole driving circuit (the output terminals of the pull-up driving array 130 and the pull-down driving array 140 are connected together to form the output terminal of the driving circuit) are in a high-resistance state, and in this state, the leakage current of the driving circuit is minimized, thereby significantly reducing the standby power consumption.
When the mode control signal indicates an ODT mode corresponding to any one of the interface protocols, the first data signal and the second data signal are output based on the interface protocol to control the pull-up driving array 130 and the pull-down driving array 140, and a connection manner of the ODT terminal is determined based on the interface protocol. Specifically, for the DDR3 interface protocol, the high-speed multimode selector 120 outputs the first data signal and the second data signal to ensure that the pull-up driving array 130 and the pull-down driving array 140 are simultaneously turned on, and the ODT termination level is one half of the preset power supply voltage VDDQ; for the DDR4/5 interface protocol, the high speed multimode selector 120 outputs a first data signal and a second data signal, which causes the pull-up driving array 130 to be turned on and the pull-down driving array 140 to be turned off, the ODT termination level being a preset power supply voltage VDDQ; for the LPDDR4/4x/5 interface protocol, the high speed multimode selector 120 outputs a first data signal and a second data signal, turning the pull-up driving array 130 off, turning the pull-down driving array 140 on, and the ODT termination level is a preset ground voltage VSSQ.
When the mode control signal indicates a driving mode corresponding to any interface protocol, the high-speed multimode selector 120 outputs a first data signal and a second data signal to turn on the pull-up driving array 130 based on the first data signal and turn on the pull-down driving array 140 based on the second data signal, and the high-speed data transmission is performed by driving the subsequent pull-up driving array 130 and the pull-down driving array 140 at the same time, so that the wide-range signal level output of 0.5-1.5V under each interface protocol can be satisfied.
It should be noted that the number of pull-up driving units turned on in the pull-up driving array 130 and/or the number of pull-down driving units turned on in the pull-down driving array 140 are determined based on the corresponding interface protocol.
It can be seen that the high-speed multimode selector 120 can ensure that the pull-up driving array 130 operates in the first voltage domain (VDDQ-VPROTL) and the pull-down driving array 140 operates in the second voltage domain (VPROTH-VSSQ) by transferring the first data signal and the first output signal in the first voltage domain to the pull-up driving array 130 and transferring the second data signal and the second output signal in the second voltage domain to the pull-down driving array 140, thereby ensuring that both the pull-up driving array 130 and the pull-down driving array 140 operate in the safe voltage range under different interface level protocols.
In some embodiments, the pull-up driving array 130 includes a predetermined number of pull-up driving units, and the pull-down driving array 140 includes a predetermined number of pull-down driving units. Wherein the number of pull-up driving units, the number of pull-down driving units, and the number of high-speed level shifters are the same.
Fig. 4 is a schematic structural diagram of a pull-up driving unit and a pull-down driving unit provided by the present invention, as shown in fig. 4, the pull-up driving unit is composed of a first transistor 411, a second transistor 412 and a pull-up resistor 413 connected in series; the pull-down driving unit is composed of a third transistor 421, a fourth transistor 422, and a pull-down resistor 423 connected in series. The source of the first transistor 411 is connected with a preset power supply voltage VDDQ, the drain of the first transistor 411 is connected with the source of the second transistor 412, the drain of the second transistor 412 is connected with the pull-up resistor 413, and the other end of the pull-up resistor 413 is the output end of the pull-up driving unit; the control terminal of the first transistor 411 is connected to the first data signal, and the control terminal of the second transistor 412 is connected to the first protection voltage VPROTL. The source of the third transistor 421 is connected to the preset ground voltage VSSQ, the drain of the third transistor 421 is connected to the source of the fourth transistor 422, the drain of the fourth transistor 422 is connected to the pull-down resistor 423, and the other end of the pull-down resistor 423 is the output end of the pull-down driving unit; the control terminal of the third transistor 421 is connected to the second data signal, and the control terminal of the fourth transistor 422 is connected to the second protection voltage VPROTH.
Wherein, the first transistor 411 and the third transistor 421 are both array-type size-adjustable transistors; the first transistor 411 and the third transistor 421 are transistors of a first conductivity type, and the second transistor 412 and the fourth transistor 422 are transistors of a second conductivity type, which is different from the first conductivity type.
It should be noted that, the transistors may be designed by adopting Core Voltage Device in CMOS technology, so that the highest working speed of different interface protocols can be satisfied, and under the clamping of the input first protection voltage and the second protection voltage, the withstand voltage requirements of different technologies can be satisfied, so that the circuit works within the safe voltage range; meanwhile, the array type size-adjustable transistor is adopted, the output of the pull-up driving unit and the output of the pull-down driving unit have consistent impedance and driving capability under the change of external conditions such as process, voltage, temperature and the like through the calibration circuit, and the reliability of the driving circuit is improved.
According to the driving circuit provided by the embodiment of the invention, the high-speed level converter array, the high-speed multimode selector, the pull-up driving array and the pull-down driving array are utilized to form the multimode memory driving circuit, the high-speed level converter array is utilized to output the first output signal in the first voltage domain and the second output signal in the second voltage domain based on the input signal, the first protection voltage and the second protection voltage of the initial voltage domain, the high-speed multimode selector is utilized to output the corresponding first data signal and the second data signal based on the mode control signal, the pull-up driving array is controlled based on the first data signal and the first output signal in the first voltage domain, the pull-down driving array is controlled based on the second data signal and the second output signal in the second voltage domain, and the driving signal output by the driving circuit output end jointly formed by the output ends of the pull-up driving array and the pull-down driving array is obtained, so that different memory interface protocols such as the DDR3/DDR4/DDR5, the LPDDR3/4/5/5X and the like can be compatible simultaneously, meanwhile, the requirements of multiple memory interface protocols on the memory interface on the memory driving circuit are met, and the design and cost are remarkably reduced.
Based on any one of the above embodiments, the embodiment of the present invention further provides a multi-protocol interface compatible PHY (Physical) chip, where the chip includes an integrated circuit of the multi-mode memory driving circuit provided in any one of the above embodiments, and is compatible with DDR/LPDDR multi-interface protocols.
Based on any of the above embodiments, the chip further includes an integrated circuit for impedance calibration of the pull-up driving array and the pull-down driving array.
The apparatus embodiments described above are merely illustrative, wherein the elements illustrated as separate elements may or may not be physically separate, and the elements shown as elements may or may not be physical elements, may be located in one place, or may be distributed over a plurality of network elements. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of this embodiment. Those of ordinary skill in the art will understand and implement the present invention without undue burden.
From the above description of the embodiments, it will be apparent to those skilled in the art that the embodiments may be implemented by means of software plus necessary general hardware platforms, or of course may be implemented by means of hardware. Based on this understanding, the foregoing technical solution may be embodied essentially or in a part contributing to the prior art in the form of a software product, which may be stored in a computer readable storage medium, such as ROM/RAM, a magnetic disk, an optical disk, etc., including several instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to execute the method described in the respective embodiments or some parts of the embodiments.
Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present invention, and are not limiting; although the invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit and scope of the technical solutions of the embodiments of the present invention.
Claims (10)
1. A multi-mode memory drive circuit, comprising:
a high speed level shifter array, a high speed multimode selector, a pull-up drive array, and a pull-down drive array;
the high-speed level shifter array is used for outputting a first output signal in a first voltage domain and a second output signal in a second voltage domain based on an input signal in an initial voltage domain, a first protection voltage and a second protection voltage; the first voltage domain represents a voltage range from the first protection voltage to a preset power supply voltage, and the second voltage domain represents a voltage range from a preset ground voltage to the second protection voltage;
the high-speed multimode selector is used for outputting corresponding first data signals and second data signals based on a mode control signal, transmitting the first data signals and the first output signals in a first voltage domain to the pull-up driving array, and transmitting the second data signals and the second output signals in a second voltage domain to the pull-down driving array, wherein the preset power supply voltage, the preset ground voltage and the mode control signal are determined based on a current interface protocol;
the pull-up driving array is connected with the output end of the pull-down driving array and is used for outputting driving signals.
2. The multi-mode memory driver circuit of claim 1, wherein the first data signal is for controlling an opening and closing of the pull-up drive array and for controlling a number of pull-up drive units that are turned on in the pull-up drive array when the pull-up drive array is turned on; the number of the turned-on pull-up driving units in the pull-up driving array is determined based on an interface protocol indicated by the mode control signal;
the second data signal is used for controlling the opening and closing of the pull-down driving array, and is used for controlling the number of pull-down driving units which are opened in the pull-down driving array when the pull-down driving array is opened; the number of turned-on pull-down driving units in the pull-down driving array is determined based on an interface protocol indicated by the mode control signal;
the mode control signal is used for indicating a low power consumption mode, an ODT mode corresponding to different interface protocols or a driving mode corresponding to different interface protocols.
3. The multi-mode memory driver circuit of claim 2, wherein the high-speed multi-mode selector is specifically configured to:
outputting a first data signal and a second data signal to turn off the pull-up driving array based on the first data signal and to turn off the pull-down driving array based on the second data signal when the mode control signal indicates a low power consumption mode;
when the mode control signal indicates an ODT mode corresponding to any interface protocol, outputting a first data signal and a second data signal based on the any interface protocol so as to control the pull-up driving array and the pull-down driving array, and determining the connection mode of an ODT terminal based on the any interface protocol;
when the mode control signal indicates a driving mode corresponding to any interface protocol, outputting a first data signal and a second data signal to start the pull-up driving array based on the first data signal and start the pull-down driving array based on the second data signal; the number of the pull-up driving units started in the pull-up driving array and/or the number of the pull-down driving units started in the pull-down driving array is determined based on any interface protocol.
4. The multi-mode memory driver circuit of claim 1, wherein the high-speed level shifter array comprises a predetermined number of high-speed level shifters, each high-speed level shifter comprising a first level shifter unit and a second level shifter unit having the same structure; the first level conversion unit is used for outputting a first output signal in a first voltage domain based on an input signal of an initial voltage domain and a first protection voltage; the second level conversion unit is used for outputting a second output signal in a second voltage domain based on the input signal of the initial voltage domain and a second protection voltage.
5. The multi-mode memory driver circuit of claim 4, wherein the first level shift unit or the second level shift unit comprises:
an input voltage domain inverter, an ac coupling capacitor, an output voltage domain latch, and a controllable dc level path;
wherein the input signal is connected with the input voltage domain inverter; the output end of the input voltage domain inverter is connected with the input end of the alternating current coupling capacitor and the input end of the controllable direct current level channel; the output end of the alternating current coupling capacitor and the output end of the controllable direct current level channel are connected with the input end of the output voltage domain latch; the output voltage domain latch consists of two output voltage domain inverters with input and output being in short circuit with each other; the output voltage domain inverter of the first level conversion unit is connected with the first protection voltage and the preset power supply voltage, and the output voltage domain inverter of the second level conversion unit is connected with the preset ground voltage and the second protection voltage.
6. The multi-mode memory driver circuit of claim 1, wherein the pull-up driver array comprises a preset number of pull-up driver cells and the pull-down driver array comprises a preset number of pull-down driver cells;
the pull-up driving unit is formed by connecting a first transistor, a second transistor and a pull-up resistor in series; the pull-down driving unit is formed by connecting a third transistor, a fourth transistor and a pull-down resistor in series;
the source electrode of the first transistor is connected with the preset power supply voltage, the drain electrode of the first transistor is connected with the source electrode of the second transistor, the drain electrode of the second transistor is connected with the pull-up resistor, and the other end of the pull-up resistor is the output end of the pull-up driving unit; the control end of the first transistor is connected with the first data signal, and the control end of the second transistor is connected with the first protection voltage;
the source electrode of the third transistor is connected with the preset ground voltage, the drain electrode of the third transistor is connected with the source electrode of the fourth transistor, and the drain electrode of the fourth transistor is connected with the pull-down resistor; the other end of the pull-down resistor is the output end of the pull-down driving unit; the control end of the third transistor is connected with the second data signal, and the control end of the fourth transistor is connected with the second protection voltage.
7. The multi-mode memory driver circuit of claim 6, wherein the first transistor and the third transistor are each array-type size-tunable transistors; the first transistor and the third transistor are transistors of a first conductivity type, and the second transistor and the fourth transistor are transistors of a second conductivity type, the second conductivity type being different from the first conductivity type.
8. The multi-mode memory driver circuit of claim 1, wherein the first protection voltage is different from the second protection voltage.
9. A multi-protocol interface compatible PHY chip comprising an integrated circuit of a multi-mode memory driver circuit according to any one of claims 1 to 8.
10. The multi-protocol interface compatible PHY chip of claim 9 further comprising an integrated circuit of an impedance calibration circuit that performs impedance calibration of the pull-up drive array and the pull-down drive array.
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