KR100434512B1 - Semiconductor memory device comprising circuit of precharging data line - Google Patents

Abstract

A semiconductor memory device having a circuit for precharging a data line is disclosed. A semiconductor memory device according to the present invention comprises: a first precharge circuit for precharging a first pair of data lines to a first voltage level in a precharge operation state; A second precharge circuit for precharging the second data line pair to a second voltage level in a precharge operation state; A data input driver for receiving data and driving the data to the first data line pair; A switch connecting or disconnecting the first data line pair and the second data line pair in response to the selection signal; And a charge sharing control circuit for sharing charge between one line of the first data line pair and one line of the second data line pair in response to the selection signal. According to the present invention, there is an advantage that current consumption can be reduced in a semiconductor memory device which repeats precharge and write operations.

Description

Semiconductor memory device comprising circuit of precharging data line

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly, to a semiconductor memory device capable of reducing current consumption by sharing charge of a pair of data lines during a data write operation.

In general, a semiconductor memory device requires a circuit for precharging a data line to a predetermined voltage level before performing an operation of writing external data.

1 is a diagram illustrating a semiconductor memory device 100 having a precharge circuit according to the prior art, and FIG. 2 is a table illustrating voltage levels of data line pairs according to the operation of the semiconductor memory device in FIG. 1. to be. The voltage level corresponding to the logic 'high' shown in FIG. 2 is the power supply voltage Vcc or the difference between the power supply voltage Vcc and the transistor threshold voltage Vt (Vcc-Vt).

The semiconductor memory device 100 illustrated in FIG. 1 includes a data input driver 110, a first data line pair charge circuit 120, a switching circuit 130, and a second data line pair charge circuit. 140). Data of the second data line pair DATA2 and / DATA2 is input to a memory array (not shown).

The data input driver 110 is connected to the first data line pair DATA1 and / DATA1 and receives predetermined data from the data input terminal DATA_IN to drive the first data line pair DATA1 and / DATA1.

The first data line pair charge circuit 120 precharges the first data line pair DATA1 and / DATA1 to a predetermined voltage level in response to the control signal DP1. The second data line pair charge circuit 140 precharges the second data line pair DATA2 and / DATA2 to a predetermined voltage level in response to the control signal DP2.

The switching circuit 130 connects the first data line pair DATA1 and / DATA1 and the second data line pair DATA2 and / DATA2 in response to the selection signal SEL.

A semiconductor memory device 100 according to the related art will be described with reference to FIGS. 1 and 2 as follows. In the state where the data line is precharged, predetermined control signals DP1 and DP2 transition to a logic low (ground voltage VSS level), and the first data line pair DATA1, / DATA1 and the second data line pair DATA2. , / DATA2 are all precharged to a logic high state, that is, the power supply voltage Vcc or the power supply voltage-threshold voltage Vcc-Vt in response to predetermined control signals DP1 and DP2.

Subsequently, in the data write operation, the first data line pair DATA1 and / DATA1 transition to DATA1 = logical high, / DATA1 = logical low or vice versa according to the data driven by the data input driver 110, and the switching circuit By operation 130, the second data line pair DATA2. / DATA2 also transitions to the same voltage level as the first data line pair DATA1, / DATA1.

After the data write operation is finished, the display returns to the precharge state. In this case, as described above, both the first data line pair DATA1 and / DATA1 and the second data line pair DATA2 and / DATA2 are connected to the power supply voltage. Precharged.

At this time, one line of the first data line pair DATA1 and / DATA1 and one line of the second data line pair DATA2 and / DATA2 are logic low by the write operation in the logic high state by the precharge operation. Transition to the state and then to logic high by the precharge operation again. Therefore, they have a problem in that they consume current while repeating the write operation and the precharge operation.

Accordingly, an aspect of the present invention is to provide a semiconductor memory device which reduces the amount of current consumed during the repetition of data writing and precharging.

BRIEF DESCRIPTION OF THE DRAWINGS In order to better understand the drawings cited in the detailed description of the invention, a brief description of each drawing is provided.

1 is a diagram illustrating a semiconductor memory device having a precharge circuit according to the prior art.

FIG. 2 is a table illustrating voltage levels of data line pairs according to an operation of the semiconductor memory device in FIG. 1.

3 illustrates a semiconductor memory device having a precharge circuit according to the present invention.

FIG. 4 is a table illustrating voltage levels of data line pairs according to the operation of the semiconductor memory device in FIG. 3.

5 is a graph illustrating an operation of a data line in a semiconductor memory device according to the related art.

6 is a graph illustrating an operation of a data line in the semiconductor memory device according to the present invention.

One aspect of the present invention for achieving the above technical problem relates to a semiconductor memory device. A semiconductor memory device according to the present invention comprises: a precharge circuit for precharging a first data line pair and a second data line pair respectively to a predetermined voltage level in a precharge operation state; A data input driver for receiving data and driving the data to the first data line pair; And connecting or disconnecting the first data line pair and the second data line pair in response to a selection signal, and disconnecting one line of the first data line pair from the second data line pair in response to the selection signal. It is characterized by including the control circuit which connects with one line.

Preferably, the precharge circuit comprises: a first precharge circuit for precharging the first pair of data lines to a first voltage level in response to a first control signal; And a second precharge circuit configured to precharge the second data line pair to a second voltage level in response to a second control signal, wherein the first voltage level and the second voltage level are different from each other. Characterized in that the voltage level.

Preferably, the control circuit may be configured such that the voltage level of one line of the first data line pair and the voltage level of one line of the second data line pair correspond to the first voltage level in response to the selection signal. And control to be a predetermined voltage level between the second voltage levels.

Another aspect of the present invention for achieving the above technical problem relates to a semiconductor memory device. A semiconductor memory device according to the present invention comprises: a first precharge circuit for precharging a first pair of data lines to a first voltage level in a precharge operation state; A second precharge circuit for precharging the second data line pair to a second voltage level in a precharge operation state; A data input driver for receiving data and driving the data to the first data line pair; A switch connecting or disconnecting the first data line pair and the second data line pair in response to the selection signal; And a charge sharing control circuit for sharing charge between one line of the first data line pair and one line of the second data line pair in response to the selection signal.

Preferably, the first voltage level and the second voltage level is characterized in that the different voltage level.

Also preferably, the charge sharing control circuit may further include a voltage level at one line of the first data line pair and a voltage level at one line of the second data line pair in response to the selection signal. And a predetermined voltage level between the voltage level and the second voltage level.

Another aspect of the present invention for achieving the above technical problem relates to a semiconductor memory device. In an embodiment, a semiconductor memory device may include a first data line pair; A second data line pair; A data input driver connected to the first data line pair and configured to drive input data into the first data line pair; And a line connected between the first data line pair and the second data line pair, and one line of the first data line pair and one line of the second data line pair in a first step of precharge operation. And a charge sharing control circuit for connection.

Preferably, the first data line pair is precharged to a first voltage level in a second step of the precharge operation, and the second data line pair is precharged to a second voltage level in a second step of the precharge operation. The voltage level of one line of the first data line pair and one line of the second data line pair connected to each other in the first step of the precharge operation is between the first voltage level and the second voltage level. It is characterized in that the predetermined voltage level of.

DETAILED DESCRIPTION In order to fully understand the present invention, the operational advantages of the present invention, and the objects achieved by the practice of the present invention, reference should be made to the accompanying drawings which illustrate preferred embodiments of the present invention and the contents described in the drawings.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. Like reference numerals in the drawings denote like elements.

3 is a diagram illustrating a semiconductor memory device 300 including a precharge circuit according to the present invention. The semiconductor memory device 300 illustrated in FIG. 3 includes a data input driver 310, a first precharge circuit 320, a switching circuit 330, a charge-sharing control circuit 340, and a second free circuit. A charge circuit 350 is provided.

The data input driver 310 is connected to the first data line pair DATA1 and / DATA1 and drives the input data DATA_IN as the first data line pair DATA1 and / DATA1.

The first precharge circuit 320 precharges the first data line pair DATA1 and / DATA1 to a first voltage level (eg, the ground voltage VSS level) in response to the first control signal DP1. In the above embodiment, the first precharge circuit 320 uses the first control signal DP1 as a gate input, and the NMOS transistors MN35 and MN36 having drains connected to the first data line pair DATA1 and / DATA1, respectively. Implemented as

The switching circuit 330 connects or disconnects the first data line pair DATA1 and / DATA1 and the second data line pair DATA2 and / DATA2 in response to the selection signal SEL. In this embodiment, the switching circuit 330 is implemented with two transmission gates XTA and XTB and one inverter 331.

The charge sharing control circuit 340 occupies between one line of the first data line pair DATA1 and / DATA1 and one line of the second data line pair DATA2 and / DATA2 in response to the selection signal SEL. share the charge.

In the present embodiment, the charge sharing control circuit 340 receives the second data line DATA2 and the selection signal SEL, and outputs a first logical signal to the first NOR gate 341 and the second data line / DATA2. And a second NOR gate 342 for receiving the selection signal SEL and outputting a second logic signal, and using the first logic signal as an input of a gate, and a source and a drain of the second data line DATA2 and the first data, respectively. The NMOS transistor MN33 connected to the line / DATA1 and the NMOS transistor MN34 connected to the second data line / DATA2 and the first data line DATA1 are respectively implemented.

The second precharge circuit 350 receives the second control signal DP2 and subtracts the transistor threshold voltage Vt from the second data line pair (eg, the power supply voltage VCC level or the power supply voltage). VCC-Vt) level). The second precharge circuit 350 includes the PMOS transistors MP31 and MP32, the second control signal DP2 is input to the gates of the PMOS transistors MP31 and MP32, and the PMOS transistor MP31 is formed of the second precharge circuit 350. It is connected between two data lines DATA2 and VCC, and the PMOS transistor MP32 is connected between the complementary second data line / DATA2 and VCC. The second precharge circuit 350 precharges the second data line pair DATA2 and / DATA2 to the power supply voltage VCC level in response to the deactivated (eg, logic 'low') second control signal DP2. .

The semiconductor memory device 300 illustrated in FIG. 3 receives data from the data input driver 310, and the second data line pair DATA2 and / DATA2 are connected to a memory array (not shown) to receive the input data. To a memory array (not shown).

4 is a table illustrating voltage levels during each operation of the semiconductor memory device according to the circuit of FIG. 3. Referring to Figures 3 and 4 the operation of the circuit according to the present invention will be described.

First, in the precharge operation state, the first data line pair DATA1 and / DATA1 and the second data line pair DATA2 and / DATA2 each have a predetermined voltage level (for example, a power supply voltage VCC level or power supply). The voltage VCC is precharged to the voltage level VCC-Vt or the ground voltage VSS level minus the transistor threshold voltage Vt. In the precharge operation state, the first control signal DP1 becomes logic high and the second control signal DP2 becomes logic low.

The first precharge circuit 320 precharges the first data line pair DATA1 and / DATA1 to a logic low in response to the first control signal DP1 transitioned to a logic high. When the first control signal DP1 transitions to logic high, the NMOS transistors MN35 and MN36 are turned on to precharge the first data line pair DATA1 and / DATA1 to logic low.

The second precharge circuit 350 precharges the second data line pair DATA2 and / DATA2 to logic high in response to the second control signal DP2 transitioned to a logic low. When the second control signal DP2 transitions to a logic low, the PMOS transistors MP31 and MP32 are turned on to precharge the second data line pair DATA2 and / DATA2 to a logic high.

That is, in the precharge state, the first data line pair DATA1 and / DATA1 and the second data line pair DATA2 and / DATA2 are precharged to different voltage levels. At this time, the select signal SEL becomes a logic low so that the switching circuit 330 does not connect the first data line pair DATA1 and / DATA1 and the second data line pair DATA2 and / DATA2.

In the state where data is written into a memory cell (not shown), data is received at the data input terminal DATA_IN, and the data input driver 310 drives the first data line pair DATA1 and / DATA1. That is, in the first data line pair DATA1 and / DATA1, DATA1 transitions to logic high and / DATA1 transitions to logic high and vice versa.

For example, the case where DATA1 transitions to logic high and / DATA1 transitions to logic low will be described. In the data write state, the selection signal SEL transitions to logic high and the switching circuit 330 responds to the selection signal SEL to the first data line pair DATA1 and / DATA1 and the second data line pair DATA2 and /. Connect DATA2). The second data line pair DATA2 and / DATA2 transition to a logic state in response to the first data line pair DATA1 and / DATA1. For convenience of explanation, it is assumed that DATA2 transitions to logic high and / DATA2 transitions to logic low.

When the precharge operation is started after the write operation is completed, the selection signal SEL becomes logic low, and the transmission gates XTA and XTB are disabled in response to the selection signal SEL. At this time, the 1NOR gate 341 of the charge sharing control circuit 340 outputs a logic low to turn off the transistor MN33.

However, the 2NOR gate 342 outputs a logic high to turn on the transistor MN34 so that the charge of the first data line DATA1 moves to the second data line / DATA2. Accordingly, the second data line / DATA2 is precharged to a voltage level between the logic low state and the logic high state in the logic low state. In addition, the first data line DATA1 is precharged to a voltage level between a logic low state and a logic high state at logic high.

Subsequently, the second selection signal DP2 transitions to a logic low and the first selection signal DP1 transitions to a logic high, and again the first data line pair DATA1, / DATA1 and the second data line pair DATA2, / DATA2) are precharged to levels of logic high and logic low, respectively.

In the present example, the second data line pair DATA2 and / DATA2 have states of logic high and logic low, respectively, during a write operation. However, in the case of the opposite logic state, the same method may be described. Of course, the logical state in this case has been described in parentheses in Figs.

5 is a graph illustrating an operation of a data line in a semiconductor memory device according to the related art, and FIG. 6 is a graph illustrating an operation of a data line in a semiconductor memory device according to the present invention.

As shown in FIG. 5, in the conventional technology, the operation of the data line repeats the write operation and the precharge operation, and changes from the power supply voltage (Vcc or Vcc-Vt) corresponding to the logic high to the power supply voltage corresponding to the logic low. Repeated transitions consume a lot of current.

However, as shown in FIG. 6, in the present invention, the operation of the data line includes charge sharing between the first data line pair DATA1 and / DATA1 and the second data line pair DATA2 and / DATA2 between the write operation and the precharge operation. After charging to a predetermined power supply voltage level between the power supply voltage level of logic high and the power supply voltage level of logic low by charge sharing, the battery is precharged again (60), thereby consuming the amount of current consumed by charge sharing. Can be reduced.

As described above, optimal embodiments have been disclosed in the drawings and the specification. Although specific terms have been used herein, they are used only for the purpose of describing the present invention and are not intended to limit the scope of the invention as defined in the claims or the claims. Therefore, those skilled in the art will understand that various modifications and equivalent other embodiments are possible therefrom. Therefore, the true technical protection scope of the present invention will be defined by the technical spirit of the appended claims.

As described above, the semiconductor memory device according to the present invention uses the charge of the data line charged to the logic high among the first data line pair in the data writing step to fill the data line to be charged to the logic high among the second data line pair. In this case, the amount of current consumed and the power consumed during the data write operation can be reduced.

Claims (9)

In a semiconductor memory device, A precharge circuit for precharging each of the first data line pair and the second data line pair to a predetermined voltage level in a precharge operation state; A data input driver for receiving data and driving the data to the first data line pair; And, The first data line pair and the second data line pair are connected or disconnected in response to a selection signal, and one line of the first data line pair is connected to one of the second data line pairs in response to the selection signal. And a control circuit connected to the line. The method of claim 1, wherein the precharge circuit A first precharge circuit for precharging the first data line pair to a first voltage level in response to a first control signal; And, And a second precharge circuit for precharging the second data line pair to a second voltage level in response to a second control signal. The method of claim 2, wherein the first voltage level and the second voltage level is A semiconductor memory device, characterized in that at different voltage levels. The method of claim 1, wherein the control circuit In response to the selection signal, the voltage level of one line of the first data line pair and the voltage level of one line of the second data line pair are predetermined voltages between the first voltage level and the second voltage level. A semiconductor memory device, characterized in that the control to be a level. A first precharge circuit for precharging the first pair of data lines to a first voltage level in a precharge operation state; A second precharge circuit for precharging the second data line pair to a second voltage level in a precharge operation state; A data input driver for receiving data and driving the data to the first data line pair; A switch connecting or disconnecting the first data line pair and the second data line pair in response to the selection signal; And, And a charge sharing control circuit for sharing charge between one line of the first data line pair and one line of the second data line pair in response to the selection signal. The method of claim 5, wherein the first voltage level and the second voltage level is A semiconductor memory device, characterized in that at different voltage levels. The method of claim 5, wherein the charge sharing control circuit In response to the selection signal, the voltage level at one line of the first data line pair and the voltage level at one line of the second data line pair are predetermined between the first voltage level and the second voltage level. A semiconductor memory device, characterized in that the voltage level. In a semiconductor memory device, A first data line pair; A second data line pair; A data input driver connected to the first data line pair and configured to drive input data into the first data line pair; And Connected between the first data line pair and the second data line pair, and connecting one line of the first data line pair and one line of the second data line pair in a first step of precharge operation. And a charge sharing control circuit for the semiconductor memory device. The method of claim 8, The first data line pair is precharged to a first voltage level in a second step of precharge operation, The second data line pair is precharged to a second voltage level in a second step of the precharge operation, The voltage level of one line of the first data line pair and one line of the second data line pair connected to each other in the first step of the precharge operation is a predetermined value between the first voltage level and the second voltage level. A semiconductor memory device, characterized in that the voltage level.