KR20070092557A - Level shifter - Google Patents

Abstract

A level shifter is provided to maintain the level of an output port even though a low driving voltage is applied in a deep standby mode. In a level shifter comprising two output ports, a pull-up driving part performs pull-up driving of one of the two output ports with a first voltage according to output port voltages of the two output ports. A first pull-down driving part performs pull-down driving of one of the two output ports by driving an input signal with a second voltage. A second pull-down driving part maintains the levels of the two output ports according to the output port voltages and a third voltage during a power saving operation.

Description

Level shifter {LEVEL SHIFTER}

1 is a circuit diagram of a level shifter according to the prior art.

2 is a circuit diagram of a level shifter according to an embodiment of the present invention.

Explanation of symbols on the main parts of the drawings

PM21, PM22: PMOS transistor NM21 ~ NM26: NMOS transistor

INV21, INV22: Inverter

TECHNICAL FIELD The present invention relates to semiconductor circuits, and more particularly, to level shifters.

In general, a level shifter is a device used to convert a voltage level at a part where a circuit using power voltages of different voltage levels is connected to generate a voltage higher or lower than a reference voltage as needed.

In particular, the level shifter is commonly used for word line drivers or block selection circuits of semiconductor memories.

Cell transistors of semiconductor memories are designed to have a relatively larger threshold voltage than other normal transistors in order to reduce leakage current. When the cell transistor is turned on, the charge stored in the cell capacitor is loaded on the bit line (or bit bar line) (read operation) or vice versa from the bit line (or bit bar line) to the cell capacitor (write operation).

At this time, the voltage level of the bit line may not sufficiently increase due to the large threshold voltage of the cell transistor, and thus the sense amplifier may not detect it. This problem occurs not only in memory cells but also in many parts of semiconductor memories such as data input / output bus lines. In order to solve the above problem, the word line is driven using an internal boost voltage Vpp having a higher activation voltage level than the power supply voltage Vcc.

However, since the internal boost voltage Vpp accumulates and generates charges supplied by the power supply voltage Vcc, it is difficult to supply a large amount of power like the power supply voltage Vcc. Therefore, in order to realize low power consumption, it is desirable to use as little internal boost voltage (Vpp) as possible.

In order to suppress the consumption of the internal boost voltage Vpp, it is necessary to output the internal boost voltage Vpp only when necessary, and to suppress the generation and output of the internal boost voltage Vpp when it is not necessary. A level shifter is used for this.

FIG. 1 is a circuit diagram of a conventional level shifter and includes an inverter INV1 (INV2), an NMOS transistor NM1 (NM2), and a PMOS transistor PM1 (PM2). .

The output terminal of the inverter INV1 for inverting the input signal INPUT is connected to the gate of the NMOS transistor NM1, and the output terminal of the inverter INV2 for inverting the output signal of the inverter INV1 is the NMOS transistor NM2. Is connected to the gate.

Sources of the PMOS transistor PM1 and the second PMOS transistor PM2 are connected to an internal voltage VDD.

A drain of the PMOS transistor PM1 is connected in common with a drain of the NMOS transistor NM1, and a source of the NMOS transistor NM1 is grounded. The drain of the PMOS transistor PM2 is connected in common with the drain of the NMOS transistor NM2, and the source of the NMOS transistor NM2 is grounded.

In addition, the gate of the PMOS transistor PM1 is commonly connected to the drains of the PMOS transistor PM2 and the NMOS transistor NM2, and the gate of the PMOS transistor PM2 is connected to the PMOS transistor PM1 and the yen. Commonly connected to the drain of the MOS transistor NM1.

The common drain of the PMOS transistor PM1 and the NMOS transistor NM1 is connected to an output terminal out-A, and the common drain of the PMOS transistor PM2 and the NMOS transistor NM2 is an output terminal ( out-B), and the output terminal out-A (out-B) has a VDD voltage or a GND voltage.

The driving voltage Vcc applied to the inverters INV1 and INV2 is 2.8V in normal operation and 1.5V is applied in the power saving mode, and then turned off.

The voltage VDD applied to the source terminal of the PMOS transistors PM1 and PM2 is 5V.

The operation of the conventional level shifter configured as described above is as follows.

The input signal INPUT is inverted through the inverter INV1 and the inverted signal is inverted again through the inverter INV2.

For example, when the input signal INPUT changes from the ground voltage GND level to the high potential Vcc level, the potential of the output terminal of the inverter INV1 goes from the high potential Vcc level to the ground voltage GND level. Since the inverter INV2 inverts the signal of the ground voltage GND level, the gate potential of the NMOS transistor NM2 is changed to the high potential Vcc level.

At this time, since the gate potential of the NMOS transistor NM2 is changed from the ground voltage GND level to the high potential Vcc level, the NMOS transistor NM2 is turned on so that the potential of the output terminal out-B is pulled down. The change from the internal voltage (VDD) level to the ground voltage (GND) level.

Accordingly, since the potential of the output terminal out-B becomes the ground voltage GND level by turning on the NMOS transistor NM2, the PMOS transistor PM1 is turned on and the PMOS transistor PM1 is turned on. As a result, the potential of the output terminal out-A becomes the internal voltage VDD level, and the PMOS transistor PM2 is maintained in the turn-off state.

On the contrary, when the input signal INPUT changes from the high potential Vcc level to the ground voltage GND level, the output terminal potential of the inverter INV1 transitions to the high potential Vcc level, and the output terminal potential of the inverter INV2. Transitions to the ground voltage (GND) level.

At this time, the NMOS transistor NM1 is turned on by the high potential Vcc signal of the output terminal of the inverter INV1, and the NMOS transistor NM2 is turned on by the ground voltage GND potential of the output terminal of the inverter INV2. Is turned off.

Accordingly, since the potential of the output terminal out-A becomes the ground voltage GND level by turning on the NMOS transistor NM1, the PMOS transistor PM2 to which the ground voltage GND is applied to the gate terminal. Is turned on to shift the potential of the output terminal out-B to the level of the internal voltage VDD, and the PMOS transistor PM1 to which the internal voltage VDD of the output terminal out-B is applied to the gate terminal is By turning off, the potential of the output terminal out-A maintains the ground voltage GND level.

That is, the level shifter of FIG. 1 receives the input signal INPUT of a predetermined voltage level Vcc or GND by performing the above operation whenever the level of the input signal is changed, thereby outputting the output terminal out-A (out-B). Is to output a VDD voltage or a GND voltage.

공정의 칩에는 딥 스탠바이 모드(deep standby mode)라는 절전 기능이 구비되는데, 이는 칩이 동작할 필요가 없을 때 칩에서 소비하는 전력(power)을 줄이기 위해 아날로그 회로의 소비 전력을 최소화하고 디지털 회로의 소비 전력을 오프시키는 것이다. 0.18 recently produced

The chip in the process is equipped with a power saving function called deep standby mode, which minimizes the power consumption of the analog circuitry and reduces the power consumption of the digital circuitry in order to reduce the power consumed by the chip when the chip does not need to operate. It is to turn off the power consumption.

공정으로 생산되는 저전압 트랜지스터의 전압은 기본적으로 1.5V~1.8V를 사용하게 되었다. 이는 디지털 회로와 메모리에서 낮은 전압을 사용함으로써 전류소모를 줄이기 위한 것이다. By the way, the power supply voltage of the inverter provided in the conventional level shifter is 2.8V, but recently 0.18

The voltage of low voltage transistor produced by the process basically used 1.5V ~ 1.8V. This is to reduce current consumption by using low voltages in digital circuits and memories.

In other words, when the digital circuit is not used, the analog circuit generating the Vcc of 1.5 V to 1.8 V is powered down to cut off the current consumed by the digital circuit.

However, in the conventional level shifter, when the analog circuit which generates the operating power of the digital circuit is powered down when the digital circuit is not used, a problem occurs in the analog circuit which operates by receiving the output signal of the level shifter.

In other words, referring to the operation of the level shifter of FIG. 1, when the voltage Vcc is applied at 1.5 V in the deep standby mode, the VDD value is output at the output terminal out-A and at the output terminal out-B. The GND value is output, and the analog circuit is controlled by the output voltage of the output terminals out-A and out-B.

However, when the voltage VCC of 1.5V, which is the digital power supply, is turned off, the voltage level input to the gates of the transistors NM1 and NM2 of both ends is GND, and the output terminal out-A of the voltage VDD level is provided. Since the transistor NM1 is continuously turned off, the transistor NM1 is maintained at the voltage VDD level.

However, the output terminal out-B does not maintain the voltage VDD level because the transistor NM2 is turned off, and becomes an intermediate value between the voltage VDD and the GND value.

Therefore, when the conventional level shifter is operated in the deep standby mode, the voltage level of the output terminal (out-B) becomes an intermediate value between VDD and GND, and thus can operate on a transistor of an analog circuit controlled by the output terminal (out-B_). There is a problem that a malfunction occurs because the voltage is input.

Accordingly, an object of the present invention is to provide a level shifter invented to maintain a level of an output terminal even when a low driving voltage is input as an operation of a power saving function in order to improve the conventional problem.

That is, an object of the present invention is to maintain the voltage level of the output terminal even if the level of the input voltage is changed by the power saving function.

The present invention provides a level shifter having two output terminals, in order to achieve the above object, a pull-up driving unit which pulls up one of the two output terminals to a first voltage according to an input signal, and drives a second voltage. A first pull-down driving unit which pulls down one of the two output terminals according to an input signal as a voltage, and maintains an off state in a normal operation, and operates by a third voltage in a power saving operation to operate the two output terminals; And a second pull-down driving unit for maintaining the level state of the device.

The second pull-down driving unit is configured to connect two NMOS transistors in series between each output terminal and a ground terminal, and apply a third voltage and the output terminal voltage to a gate terminal of each NMOS transistor in a power saving operation. In this way, the voltage level of the two output terminals can be maintained even if the level of the input voltage is changed in the power saving mode.

The second voltage is turned off after being down from 2.8V to 1.5V in the power saving operation, and the third voltage is applied to 2.8V in the off state in the power saving operation.

공정으로 제작한 레벨 쉬프터에 있어서, 소모 전력을 줄이기 위해 디지털 회로에 사용하는 전압(1.5V~1.8V)을 다운시켰을 때 아날로그 회로에 비정상적인 전압이 인가되는 문제점을 개선함으로써 상기 1.5V~1.8V의 전압이 다운되어 레벨 쉬프터 내의 인버터가 오동작하여도 아날로그 회로에 인가되는 출력단자의 전압값을 유지시키도록 하는 것이다. That is, the present invention is 0.18

In the level shifter fabricated in the process, an abnormal voltage is applied to the analog circuit when the voltage (1.5 V to 1.8 V) used in the digital circuit is reduced to reduce power consumption. The voltage is kept down to maintain the voltage value of the output terminal applied to the analog circuit even if the inverter in the level shifter malfunctions.

Hereinafter, the present invention will be described.

Technical configuration of the present invention will be described in detail in the preferred embodiment. In the preferred embodiment of the present invention will be described a number of specific details such as a specific processing flow as well as accompanying drawings to help the overall understanding of the present invention. In addition, detailed descriptions of well-known functions and configurations that may unnecessarily obscure the subject matter of the present invention will be omitted.

2 is a block diagram of an apparatus for an embodiment of the present invention, as shown therein, a PMOS transistor PM21 (PM22) operating as a pull-up driving unit and an inverter INV21 (INV22) operating as a first pull-down driving unit. ) And NMOS transistors NM21 (NM22) and NMOS transistors NM23 to NM26 that operate as the second pull-down driving unit.

An embodiment of the present invention is configured in the same manner as the circuit of FIG. 1 by using the inverters INV21 (INV22), PMOS transistors PM21 (PM22), and NMOS transistors NM21 (NM22). An NMOS transistor NM23 having a voltage VB applied to the gate terminal and an NMOS transistor having an output terminal out-B voltage applied to the gate terminal between the output terminal out-A and the ground terminal GND. The NMOS transistor NM25 and the output terminal (out-A) voltage having the voltage VB applied to the gate terminal between the output terminal (out-B) and the ground terminal (GND) are connected in series. The NMOS transistor NM26 applied to is connected in series.

The operating power Vcc of the inverters INV21 and INV22 is applied with 2.8 V in the normal operation and 1.5 V in the power saving mode.

The voltage VB is applied with 2.8V when the operating power source Vcc is applied at 1.5V and then turned off by the power saving mode.

Referring to the operation and effect of the embodiment of the present invention configured as described above are as follows.

First, when the voltage Vcc is input at 2.8 V, the inverter INV21 (INV22) sequentially inverts the input signal INPUT and applies it to the gate terminal of the NMOS transistors NM21 and NM22. However, Vcc <VDD.

At this time, since the voltage VB is at the ground voltage GND level, the NMOS transistors NM23 and NM25 maintain a turn-off state.

Therefore, when the input signal INPUT is input as a high signal, the NMOS transistor NM21 is turned off, the NMOS transistor NM22 is turned on, the PMOS transistor PM21 is turned on, and the PMOS transistor PM22 is turned on. Is off.

Accordingly, the output terminal out-A becomes the VDD level by the turned-on PMOS transistor PM21, and the output terminal out-B turns off the PMOS transistor PM22 and the NMOS transistor NM22. GND level is turned on by.

On the contrary, when the input signal INPUT is input as a low signal, the output terminal out-A becomes the GND level and the output terminal out-B becomes the VDD level.

If the voltage Vcc is input at 1.5V while operating in the power saving mode, the input signal INPUT is also 1.5V. The NMOS transistor NM21 is turned off by the output signal of the inverter INV21 and the inverter INV22 is turned on. ), The NMOS transistor NM22 is turned on by the output signal.

Accordingly, the PMOS transistor PM21 is turned on so that the signal of the output terminal out-A is output at the VDD level, and the output terminal out- is turned on by turning on the PMOS transistor PM22 and turning on the NMOS transistor NM22. The signal of B) is output at the GND level.

After that, when the voltage Vcc of 1.5 V is turned off, the operations of the inverters INV21 and INV22 are turned off, and the NMOS transistors NM21 and NM22 are turned off, but the output terminal out-A is at VDD level. State and the output terminal (out-B) is the GND level state.

At this time, the voltage VB is applied to the gate terminal of the NMOS transistors NM23 and NM25 at 2.8V, thereby turning on the NMOS transistors NM23 and NM25.

Therefore, since the level of the output terminal out-A is VDD and the level of the output terminal out-B is GND, the NMOS transistor NM25 is turned on and the NMOS transistor NM26 is turned off.

Accordingly, the PMOS transistor PM21 is turned on by the turn-on of the NMOS transistors NM25 and NM26 so that the output terminal out-A maintains the VDD level, and the NMOS transistor NM24 is turned on. The output terminal out-B maintains the GND level by turning off the PMOS transistor PM22.

On the other hand, while the preferred embodiment of the present invention has been described above, the present invention is not limited to the above embodiments, those skilled in the art related to the present invention and the spirit of the present invention described in the claims Various modifications and variations of the present invention will be possible without departing from the scope thereof.

As described in detail above, the present invention has an effect of preventing malfunction of the analog circuit connected to the output terminal by maintaining the output terminal level when the power saving function of the deep standby mode is operated.

That is, according to the present invention, when the power saving function is operated, the voltage level of the output terminal is maintained at the value when the power of the digital block is turned off, thereby solving the problem that occurred in the related art.

Claims (8)

In the level shifter having two output terminals, A pull-up driving unit configured to pull-up one of the two output terminals to a first voltage according to the two output terminal voltages; A first pull-down driving unit which drives an input signal to a second voltage and pulls down one of the two output terminals; And a second pull-down driver configured to maintain a level state of the two output terminals in accordance with a third voltage and the output terminal voltage during a power saving operation. However, the first voltage> second and third voltage. The method of claim 1, wherein the pull-up driving unit A first pull-up transistor connected between the first voltage and the first output terminal to apply a second output terminal voltage to the gate; And a second start-up transistor connected between the first voltage and the second output terminal and to which the first output terminal voltage is applied to the gate. The method of claim 1, wherein the first pull-down driving unit First and second inverters driven by a second voltage to sequentially invert the input signal; A first NMOS transistor connected between a first output terminal and a ground terminal and to which an output signal of the first inverter is applied to a gate; And a second NMOS transistor connected between a second output terminal and a ground terminal and to which an output signal of the second inverter is applied to a gate. The level shifter according to claim 1 or 3, wherein the second voltage is turned off after being changed from 2.8V to 1.5V during the power cut operation. The method of claim 2, wherein the second pull-down driving unit And at least one pull-down transistor between each of the first and second output terminals and the ground terminal. The method of claim 1, wherein the first pull-down driving unit A first NMOS transistor connected between a first output terminal and a ground terminal and having a second output terminal connected to a gate; And a second NMOS transistor connected between the second output terminal and the ground terminal and connected to the gate of the first output terminal. The NMOS transistor of claim 6, further comprising: a third NMOS transistor connected between the first output terminal and the first NMOS transistor and having a third voltage applied to the gate; And a fourth NMOS transistor connected between the second output terminal and the second NMOS transistor and to which a third voltage is applied to the gate. The method of claim 1 or 7, wherein the third voltage is The level shifter is applied at 2.8V in the off state during the power saving operation.

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