KR100334536B1 - Semiconductor memory device having input buffer - Google Patents

Abstract

The semiconductor memory device including the input buffer of the present invention incorrectly recognizes the external low voltage TTL level LVTTL by preventing the minimum voltage VIH to be recognized as the high level even if the external power supply voltage VEXT continues to rise. In a semiconductor memory device using an input buffer, a first internal power supply voltage generation unit for generating a first internal power supply voltage used in an internal circuit, and a second internal device used in the input buffer, so as to prevent an error that may occur. And a second internal power supply voltage generator for generating a power supply voltage and an internal reference voltage generator for generating an internal reference voltage used for the input buffer, wherein the second internal power supply voltage and the internal reference voltage are used in a burn-in mode. Maintain a constant voltage level even when the external power supply voltage increases, and the input buffer further includes a level shift unit to provide a first internal voltage and a second internal voltage. And to perform a stable operation even if the voltage difference between the negative voltage is larger.

Description

Semiconductor memory device having an input buffer

The present invention relates to a semiconductor memory device including an input buffer, and more particularly, to an input buffer capable of maintaining a constant potential even when a switching potential of an input buffer that receives a low voltage TTL signal and changes it to a CMOS level performs a burn-in mode. A semiconductor memory device is included.

Generally, in DRAM, power potential input from the outside is not directly used, but power potential is made internally. In addition, in order to ensure the accuracy of the test during burn-in mode operation, an internal power supply potential generated internally is used in the normal mode, and when the burn-in mode operation, the internal operating potential uses the same potential as the power supply potential input from the outside. Method is used. In this case, the burn-in mode enters the burn-in mode by inputting a special test mode signal from the outside, and the method used in the synchronous DRAM (SDRAM) includes the mode register set (MRS) instruction and the seventh address being high. To become a level.

In general, LVTTL uses the signal level outside the DRAM, and CMOS level inside the DRAM.

That is, since the voltage level of the DRAM and the external voltage is used differently, a buffer circuit that recognizes whether the level of the signal input from the DRAM is high or low level is used. As such a buffer circuit, input methods such as a CMOS inverter type buffer and a differential type input buffer are used.

The CMOS inverter type input buffer recognizes whether the level of the signal input from the outside of the DRAM is high or low by using the threshold voltage of the transistor, and the differential type input buffer refers to the internal reference voltage VREF. This is a method of recognizing whether it is high or low.

FIG. 1 is a circuit diagram illustrating a general CMOS inverter type input buffer. As shown in FIG. 1, first and second inverters INV1 and INV2 for sequentially inverting an enable signal EN, an internal power supply voltage QVDD, Internal ground to the first PMOS transistor (PM1) and the bulk to which the internal power supply voltage (QVDD) is applied to the bulk connected to the internal ground voltage (QVSS) in series, the gate is commonly connected to the external input signal (EXTIN) The first NMOS transistor NM1 to which a voltage QVSS is applied, the output of the second inverter INV2 to a gate, and the second NMOS transistor NM2 to which an internal ground voltage QVSS is applied to a bulk. And a third inverter INV3 for outputting the output signal OUT by reversing the voltage of the drain connected to the first PMOS transistor PM1 and the first NMOS transistor NM1, and an internal power supply voltage to the source. (QVDD) is applied, the second inverter (INV2) to the gate The control outputs are applied is configured to include a second PMOS transistor (PM2) of the pull-up the voltage of the common connected drains of the first PMOS transistor (PM1) and the first NMOS transistor (NM1).

FIG. 2 is a circuit diagram illustrating a differential type input buffer. As shown in FIG. 2, an internal power supply voltage QVDD is applied to a source, a gate is commonly connected, and a first supply voltage is applied to a bulk. A MOS transistor PM11, a second PMOS transistor PM12 having a gate and a drain connected in common, and a drain connected to the drains of the first and second PMOS transistors PM11 and PM12, respectively, and a source connected in common; The first and second NMOS transistors NM11 and NM12 to which an internal ground voltage QVSS is applied to the bulk, and an external input signal EXTIN and an internal reference voltage VREF are applied to the gate, respectively, and a drain thereof. A third NMOS connected to the common source of the first and second NMOS transistors NM11 and NM12, an internal ground voltage QVSS is applied to the drain and the bulk, and an enable signal EN is applied to the gate Transistor NM13 and said first PMOS Transistor (PM11) of the first en invert the voltage of the common connected drains of the MOS transistor (NM11) is configured to include a first inverter (INV11) to output an output signal (OUT).

In this case, the specification (SPEC) defines the lowest level (VIH) for recognizing that the external input voltage level is 'high' and the highest level (VIL) for recognizing the 'low'. In general, the voltage level of the internal input buffer uses a low noise internal power supply voltage (QVDD).

FIG. 3 is a block diagram of a circuit for making the internal power supply voltage QVDD. The reference voltage generator 1 generates a reference voltage VREF08 by an external power supply voltage VEXT, and the reference voltage VREF08 is leveled. The shifter 2 generates the set voltage VR1, and the multiplexer 4 separates the burn-in control signal BICON of the set voltage VR1 and the burn-in level detection unit 3 into a normal operation and a burn-in mode. For example, the control voltage VR25 for generating the internal power supply voltage QVDD of 2.5 V is output.

The control voltage VR25 causes the internal power supply voltage driver 5 to output the internal power supply voltage QVDD maintaining a 2.5 V level.

The power supply voltage VDD is also generated by the same method as the method of generating the internal power supply voltage QVDD.

On the other hand, in order to generate the internal reference voltage (VREF) used for the differential type input buffer is generated by the same method as the method for generating the internal power supply voltage (QVDD).

However, as shown in FIG. 4, when the level of the external power supply voltage VEXT is increased in the burn-in mode of the chip, the internal voltages VDD, QVDD, and VREF may be to some extent irrespective of the external power supply voltage VEXT. Although the level is constant, when the level of the external power supply voltage VEXT continues to increase, the level of the internal voltages VDD, QVDD, and VREF also increases proportionally according to the external power supply voltage VEXT.

When the special function test (SFT) is performed, the level of the external power supply voltage VEXT and the internal voltages VDD and QVDD may be the same.

At this time, when the level of the internal power supply voltage QVDD of the buffer circuit increases, the external voltage level that can be recognized as high also increases, and the minimum level VIH that recognizes that the input potential is 'high' goes up. There is a problem in that the probability of malfunction that causes the high level data to be incorrectly recognized as the low level increases.

An object of the present invention for solving the above problems is to separate the voltage level of each internal voltage used in the chip to set a constant value regardless of the level of the internal power supply voltage and the internal reference voltage used in the input buffer regardless of the level of the external power supply. A semiconductor memory device including an input buffer capable of holding and performing a stable operation is provided.

A semiconductor memory device including an input buffer of the present invention for achieving the above object,

The input buffer includes a level shift unit driven by a first internal power supply voltage used in an internal circuit and a second internal power supply voltage used in the input buffer.

The first internal power supply voltage used for the internal circuit and the second internal power supply voltage used for the input buffer are maintained even if the external voltage increases in the burn-in mode.

The above and other objects and features and advantages of the present invention will become more apparent from the following detailed description taken in conjunction with the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a circuit diagram showing a typical CMOS type input buffer.

2 is a circuit diagram showing an input buffer of a general differential type.

3 is a block diagram of a circuit for generating general internal power supply voltages VDD and QVDD and a reference voltage VREF.

4 is a waveform diagram illustrating changes in the internal power supply voltages VDD and QVDD and the reference voltage VREF according to the external power supply voltage VEXT in the block diagram of FIG. 3.

5 is a circuit diagram showing an input buffer of a CMOS type according to the present invention;

6A and 6B are circuit diagrams showing an apparatus for generating a power supply voltage VDD according to the present invention.

7A and 7B are circuit diagrams showing an apparatus for generating an internal power supply voltage QVDD and a reference voltage VREF according to the present invention.

8 is a circuit diagram showing an input buffer of a differential type according to the present invention;

FIG. 9 is a waveform diagram illustrating changes in the internal power supply voltages VDD and QVDD and the reference voltage VREF according to the external power supply voltage VEXT in the circuit diagrams of FIGS. 5 and 7.

<Description of Symbols for Major Parts of Drawings>

10: reference voltage generator

20: level shift unit

40, 60: multiplexer

50: Voltage driver

LS1, LS2: Level Shift Section

INV21-INV23, INV51: Inverter

PM21-PM25, PM31-PM312, PM41-PM412, PM51-PM55: PMOS transistor

NM21-NM25, NM31-NM313, NM41-NM413, NM51-NM57: NMOS Transistors

FIG. 5 is a circuit diagram illustrating a CMOS inverter type input buffer according to the present invention. As shown in FIG. 5, first and second inverters INV21 and INV22 sequentially inverting the enable signal EN, and an internal power supply voltage. A first PMOS transistor PM21 and a bulk connected in series between the QVDD) and the internal ground voltage QVSS, and having a gate connected in common, and to which the internal power supply voltage QVDD is applied to the bulk to which the external input signal EXTIN is applied. The first NMOS transistor NM21 to which the internal ground voltage QVSS is applied to the gate, and the second NMOS transistor to which the output of the second inverter INV22 is applied to the gate and the internal ground voltage QVSS to the bulk are applied. NM22 and an internal power supply voltage QVDD are applied to a source, and an output of the second inverter INV22 is applied to a gate to control the first PMOS transistor PM21 and the first NMOS transistor NM21. To pull up the voltage of the common connected drain A level shift unit LS1 for shifting a voltage of a drain connected in common between a second PMOS transistor PM22, the first PMOS transistor PM21, and the first NMOS transistor NM21, and the level shift unit And a third inverter INV23 for inverting the output of the LS1 and outputting the output signal OUT.

The level shift part LS1 is disposed between an internal power supply voltage QVDD and an internal ground voltage QVSS to invert a voltage of a drain connected in common between the first PMOS transistor PM21 and the first NMOS transistor NM21. The third PMOS transistor PM23 and the third NMOS transistor NM23, the source and the bulk, which are connected in series to the bulk, and are supplied with an internal power supply voltage QVDD and an internal ground voltage QVSS, respectively. The fourth and fifth PMOS transistors PM24 and PM25 having a power supply voltage VDD applied thereto and whose gates are connected to drains thereof, and drains of the fourth and fifth PMOS transistors PM24 and PM25 respectively. Respectively connected to the source, a ground voltage VSS is applied to a source, and a gate is commonly connected to the first PMOS transistor PM21 and the first NMOS transistor NM21 and the fourth PMOS transistor PM24, respectively. ) And the fourth NMOS transistor (NM2) The fourth and fifth NMOS transistors NM24 and NM25 connected to the common connected drain of 4) may be configured to include voltages of the common connected drains of the fifth PMOS transistor PM25 and the fifth NMOS transistor NM25. Is output.

The level shift unit is used to stabilize the operation when the difference between the power supply voltage VDD level and the internal power supply voltage QVDD level becomes large when the burn-in mode or the special method test SFT is performed.

The operation of the semiconductor memory device using the CMOS inverter type input buffer according to the present invention configured as described above is as follows.

The power supply voltage VDD used in the general circuit is generated in the same manner as the conventionally used method.

That is, the reference voltage generator 10 generates the reference voltage VREF08 by the external power supply voltage VEXT and shifts the set voltage VR1 by shifting the reference voltage VREF08 by the level shifter 20. For example, the set voltage VR1 and the burn-in control signal BICON of the burn-in level detection unit 3 are divided by the multiplexer 40 to generate a 2.5 V power supply voltage VDD, for example, by separating the normal operation and the burn-in mode. The control voltage VR25 is outputted.

Subsequently, the control voltage VR25 outputs a power supply voltage VDD maintained at a 2.5 V level by the power supply voltage driver 50.

Accordingly, as shown in FIG. 9, when the external power supply voltage VEXT increases in the normal mode, the power supply voltage VDD also increases, and when the power supply voltage VDD reaches 2.5 V, the control voltage VR25. To maintain the 2.5 V level. Subsequently, when the external power supply voltage VEXT continues to increase to 4.3 V, the power supply voltage VDD also increases as the external power supply voltage VEXT increases. Here, even if the external power supply voltage VEXT continues to increase depending on the device, the power supply voltage VDD may be continuously maintained at a 2.5 V level.

In the burn-in mode, as the external power supply voltage VEXT increases, the power supply voltage VDD also increases.

6A and 6B show a circuit for generating the power supply voltage VDD.

That is, as shown in FIG. 6A, the reference voltage generator 10 has an external power supply voltage VEXT applied to a gate, and a first NMOS transistor NM31 and a drain having a common source, drain, and bulk. A second NMOS transistor connected to a source and a drain connected to the first NMOS transistor NM31, an internal ground voltage QVSS is applied to the source and the bulk, and an external power supply voltage VEXT is applied to the gate. An NM32 and a node having a common source and drain of the first NMOS transistor NM31 and a drain of the second NMOS transistor NM32 connected to each other are connected to the gate, and an internal ground voltage QVSS connected to the source and the drain. ) Is applied to the third NMOS transistor NM33 to output the reference voltage VREF08 at the drain.

The level shift unit 20 includes a first PMOS transistor PM31 and a second PMOS transistor PM32 to which an external power supply voltage is applied to a source and a bulk, a gate is commonly connected, and a gate is commonly connected to a drain; A fourth NMOS transistor NM34 and a source having a drain connected to the drains of the first and second PMOS transistors PM31 and PM32, a gate connected in common, and an internal ground voltage QVSS applied to the bulk. An internal ground voltage QVSS is applied to the resistor, and a fifth NMOS transistor NM35 having a gate commonly connected to the drain, and a resistor connected between the drain of the fourth NMOS transistor NM34 and the internal ground voltage QVSS. And a set voltage VR1 is output from a drain connected to the second PMOS transistor PM32 and the fifth NMOS transistor NM35 in common.

The multiplexer 30 includes an external power supply voltage VEXT applied to a source and a bulk, a third PMOS transistor PM33 having a common gate connected thereto, a fourth PMOS transistor PM34 having a common gate connected to the drain, and a drain. The third and fourth PMOS transistors PM34 and PM35 are connected to drains, respectively, an internal ground voltage QVSS is applied to a bulk, a source is commonly connected, and the set voltage VR1 is applied to a gate. The sixth NMOS transistor NM36 and the seventh NMOS transistor NM37 and a drain are connected to a common connected source of the sixth and seventh NMOS transistors NM36 and NM37, and are internally grounded to the source and the bulk. An eighth NMOS transistor NM38 to which a voltage QVSS is applied, the set voltage VR1 is applied to a gate thereof, and a gate and a drain thereof are commonly connected to a gate of the seventh NMOS transistor NM37. , Sour and bulk inside The ninth NMOS transistor NM39 to which the ground voltage QVSS is applied is connected in series between the external power supply voltage VEXT and the internal ground voltage QVSS, and the external power supply voltage VEXT is applied to the bulk, and the gate A fifth PMOS transistor PM35 connected to a common connected drain of the third PMOS transistor PM33 and the sixth NMOS transistor NM36, a bulk and a source are commonly connected, and a gate and a drain are commonly connected to each other. The internal ground voltage QVSS is applied to the sixth PMOS transistor PM36 connected to the gate of the seventh NMOS transistor NM37 and the source and the bulk, and the gate of the fifth PMOS transistor PM35 is drained and formed. A sixth NMOS transistor NM310 connected to a node where a source of the six PMOS transistor PM36 is commonly connected, a drain of the fifth PMOS transistor PM35, a source of the sixth PMOS transistor PM36, and a tenth Nmost The fifth PMOS transistor PM35 includes a voltage drop unit 41 configured to pull up a voltage of a node to which the gate of the jitter NM310 is commonly connected to a voltage lowered from the external power supply voltage VEXT to a predetermined voltage. The voltage at the node where the drain of the source, the source of the sixth PMOS transistor PM36 and the gate of the tenth NMOS transistor NM310 are commonly connected is output as the control voltage VR25. Here, the voltage drop unit 41 includes an external power supply voltage VEXT, a drain of the fifth PMOS transistor PM35, a source of the sixth PMOS transistor PM36, and a gate of the tenth NMOS transistor NM310. Are connected in series between the nodes connected in common, an external power supply voltage VEXT is applied to the bulk, and the seventh and eighth PMOS transistors PM37 and PM38 connected in common to the drain and the gate are internal ground voltage QVSS. And a ninth PMOS transistor PM39 connected thereto.

As shown in FIG. 6B, the power supply voltage driver 50 includes an external power supply voltage VEXT applied to a source and a bulk, and a gate connected to a drain and a tenth PMOS transistor PM310 and a gate connected to a drain. An 11 PMOS transistor PM311 and a drain are respectively connected to drains of the 10th and 11th PMOS transistors PM310 and PM311, an internal ground voltage QVSS is applied to the bulk, and a source is commonly connected; A source connected to the eleventh NMOS transistor NM311 and the twelfth NMOS transistor NM312 to which the control voltage VR25 is applied to a gate, and a drain thereof are commonly connected to the eleventh and twelfth NMOS transistors NM311 and NM312. A thirteenth NMOS transistor NM313 connected to the source, the internal ground voltage QVSS is applied to the source and the bulk, and the set voltage VR1 is applied to the gate, and an external power supply voltage VEXT at the source and the bulk. Applied, the gate A drain connected to a common connection drain of the tenth PMOS transistor PM310 and an eleventh NMOS transistor NM311 and a drain connected to a gate of the twelfth NMOS transistor NM312 to adjust a level of a power supply voltage VDD. And a twelfth PMOS transistor PM312 for driving.

Meanwhile, the circuit for generating the internal power supply voltage QVDD generates the reference voltage VREF08 by the external power supply voltage VEXT in the reference voltage generator 10, as shown in FIGS. 7A and 7B. The set voltage VR1 obtained by shifting the reference voltage VREF08 by the level shift unit 20 is generated, and the burn-in control signal BICON of the set voltage VR1 and the burn-in level detection unit 30 is supplied to the power supply voltage. The new multiplexer 60 removes the voltage drop section 41 connected to the output terminal of the multiplexer 40 for generating (VDD) even when the external power supply voltage VEXT increases in normal operation and burn-in mode. The control voltage QVR25 for holding is output.

Subsequently, the power supply voltage driver 50 outputs the internal power supply voltage QVDD maintained at a 2.5 V level by the control voltage QVR25.

In order to generate the internal reference voltage VREF used in the differential input buffer to a voltage capable of maintaining the 2.5 V level even when the external power supply voltage VEXT increases, the same circuit as that for generating the internal power supply voltage QVDD is used. Generated by the circuit.

Accordingly, the internal power supply voltage QVDD and the internal reference voltage VREF are equal to the external voltage up to 2.5 V when the external power supply voltage VEXT is increased in the normal mode and the burn-in mode as shown in FIG. 10. It increases and maintains 2.5V level by the control voltage QVR25.

The reference voltage generator 10 has an external power supply voltage VEXT applied to a gate thereof, and a first NMOS transistor NM41 having a source, a drain, and a bulk connected in common, and a drain thereof having the first NMOS transistor NM41. A second NMOS transistor NM42 connected to a common source and drain of the second source, an internal ground voltage QVSS applied to the source and the bulk, and an external power supply voltage VEXT applied to a gate thereof, and a gate of the first NMOS transistor NM42. A node connected to a common source and drain of the NMOS transistor NM41 and a drain of the second NMOS transistor NM42 is connected, and an internal ground voltage QVSS is applied to the source and the drain so that the reference voltage VREF08 is applied at the drain. ) Is configured to include a third NMOS transistor NM43.

The level shift unit 20 includes a first PMOS transistor PM41 and a second PMOS transistor PM42 having an external power supply voltage applied to a source and a bulk, a gate of which is commonly connected, and a gate of which is commonly connected to a drain; A fourth NMOS transistor NM44 and a source having a drain connected to the drains of the first and second PMOS transistors PM41 and PM42, the gates connected in common, and an internal ground voltage QVSS applied to the bulk. An internal ground voltage QVSS is applied to the fifth NMOS transistor NM45 having a gate commonly connected to the drain, and a resistor connected between the drain of the fourth NMOS transistor NM44 and the internal ground voltage QVSS. The set voltage VR1 may be output from the drain connected to the second PMOS transistor PM42 and the fifth NMOS transistor NM45.

The multiplexer 60 includes an external power supply voltage VEXT applied to a source and a bulk, a third PMOS transistor PM43 having a common gate connected thereto, a fourth PMOS transistor PM44 having a common gate connected to the drain, and a drain. The third and fourth PMOS transistors PM44 and PM45 are respectively connected to drains, an internal ground voltage QVSS is applied to a bulk, a source is commonly connected, and the set voltage VR1 is applied to a gate. The sixth NMOS transistor NM46 and the seventh NMOS transistor NM47 and a drain are connected to a common connected source of the sixth and seventh NMOS transistors NM46 and NM47, and are internally grounded to the source and the bulk. An eighth NMOS transistor NM48 to which a voltage QVSS is applied, the set voltage VR1 is applied to a gate thereof, and a gate and a drain thereof are commonly connected to a gate of the seventh NMOS transistor NM47. , Sour and bulk inside The ninth NMOS transistor NM49 to which the ground voltage QVSS is applied is connected in series between the external power supply voltage VEXT and the internal ground voltage QVSS, and the external power supply voltage VEXT is applied to the bulk, and the gate A fifth PMOS transistor PM45 connected to a common connected drain of the third PMOS transistor PM43 and the sixth NMOS transistor NM46, a bulk and a source are commonly connected, and a gate and a drain are commonly connected to each other. The internal ground voltage QVSS is applied to the sixth PMOS transistor PM46 connected to the gate of the seventh NMOS transistor NM47 and the source and the bulk, and the gate of the fifth PMOS transistor PM45 is drained and formed. A source of the sixth PMOS transistor PM46 includes a tenth NMOS transistor NM410 connected to a node to which a common PMOS transistor PM46 is connected, and a source of the fifth PMOS transistor PM46 and a source of the sixth PMOS transistor PM46. And a voltage at a node to which the gates of the tenth NMOS transistor NM410 are commonly connected are output as the control voltage VR625.

As shown in FIG. 7B, the power supply voltage driver 50 includes an external power supply voltage VEXT applied to a source and a bulk, a gate connected to a drain, and a tenth PMOS transistor PM410 and a gate connected to a drain. An 11 PMOS transistor PM411 and a drain are respectively connected to drains of the 10th and 11th PMOS transistors PM410 and PM411, an internal ground voltage QVSS is applied to the bulk, and a source is commonly connected; A source connected to an eleventh NMOS transistor NM411 and a twelfth NMOS transistor NM412 to which a control voltage VR25 is applied to a gate, and a drain thereof are commonly connected to the eleventh and twelfth NMOS transistors NM411 and NM412. The NMOS413 is connected to the source, the internal ground voltage QVSS is applied to the source and the bulk, and the set voltage VR1 is applied to the gate, and the external power supply voltage VEXT is applied to the source and the bulk. Applied, the gate The drain of the tenth PMOS transistor PM410 and the eleventh NMOS transistor NM411 is connected to a gate of the twelfth NMOS transistor NM412, and the level of the power supply voltage VDD is increased. And a twelfth PMOS transistor PM412 for driving.

FIG. 8 is a circuit diagram illustrating a differential type input buffer according to the present invention. As shown therein, an internal power supply voltage QVDD is applied to a source, a gate is commonly connected, and an internal power supply voltage QVDD is applied to a bulk. A first PMOS transistor PM51 and a second PMOS transistor PM52 having a gate and a drain connected in common, and a drain connected to the drains of the first and second PMOS transistors PM51 and PM52, respectively. Are commonly connected, the internal ground voltage QVSS is applied to the bulk, and the first and second NMOS transistors NM51 and NM52 to which the external input signal EXTIN and the internal reference voltage VREF are respectively applied to the gate. In order to stabilize the internal reference voltage VREF applied to the gate of the second NMOS transistor NM52, a drain, a source, and a bulk are commonly connected to an internal ground voltage QVSS, and a gate is connected to the second NMOS transistor NM52. MOS transistor A fourth NMOS transistor NM54 connected to the gate of NM52 and a drain are connected to a common connected source of the first and second NMOS transistors NM51 and NM52, and an internal ground voltage is applied to the drain and the bulk. QVSS is applied and the enable signal EN is applied to the gate of the third NMOS transistor NM53 and the drain connected in common with the first PMOS transistor PM51 and the first NMOS transistor NM51. And a first inverter INV51 for inverting the output of the level shift unit LS2 and outputting the output signal OUT.

The configuration of the level shift unit LS2 is the same as that of the level shift unit LS1 used in the CMOS inverter type input buffer shown in FIG.

The operation of the semiconductor memory device using the differential type input buffer configured as described above is as follows.

The power supply voltage VDD used in the general circuit is generated in the same manner as conventionally used as shown in FIG.

Accordingly, as shown in FIG. 9, when the external power supply voltage VEXT increases in the normal mode, the power supply voltage VDD also increases, and when the power supply voltage VDD reaches 2.5 V, the control voltage VR25. To maintain the 2.5 level. Subsequently, when the external power supply voltage VEXT continues to increase to 4.3 V, the power supply voltage VDD also increases as the external power supply voltage VEXT increases. Here, even if the external power supply voltage VEXT continues to increase depending on the device, the power supply voltage VDD may be continuously maintained at a 2.5 V level.

In the burn-in mode, as the external power supply voltage VEXT increases, the power supply voltage VDD also increases.

Meanwhile, as shown in FIG. 9, the internal power supply voltage QVDD and the internal reference voltage VREF are constant when the external power supply voltage VEXT is increased in the normal mode and the burn-in mode to reach a predetermined level (2.5 V). It is generated by a circuit as shown in Figs. 7A and 7B to maintain the level and to maintain a constant level even when the external power supply voltage VEXT continues to increase.

As described above, the present invention prevents an error of incorrectly recognizing an external LVTTL level by preventing the minimum voltage VIH for recognizing a high level from rising even when the external power supply voltage VEXT continues to rise. There is.

In addition, a preferred embodiment of the present invention is for the purpose of illustration, those skilled in the art will be able to various modifications, changes, substitutions and additions through the spirit and scope of the appended claims, such modifications and changes are the following claims It should be seen as belonging to a range.

Claims (15)

In a semiconductor memory device including an input buffer, The input buffer includes a level shift means driven by a first internal power supply voltage used in an internal circuit and a second internal power supply voltage used in the input buffer. First internal voltage generating means for generating a first internal power supply voltage used in the internal circuit; A second internal power supply voltage generating means for generating a second internal power supply voltage used in the input buffer, And a constant voltage even though an external voltage increases in the burn-in mode of the second internal power supply voltage and the internal reference voltage. In the semiconductor memory device of claim 1, The first internal voltage generating means for generating the first internal power supply voltage, Reference voltage generating means for generating a reference voltage by an external power supply voltage; Level shift means for generating a set voltage shifted from the reference voltage; A first multiplexer configured to generate a control voltage for generating the first internal power supply voltage by dividing the set voltage into a burn-in control signal of a burn-in level detecting means; And a power supply voltage driver configured to output a first internal power supply voltage maintained at a predetermined level by the control voltage. In the semiconductor memory device of claim 2, The reference voltage generating means, The first NMOS transistor is connected to the gate with an external power supply voltage, the source, the drain, and the bulk are connected in common, the drain is connected to the common source and the drain of the first NMOS transistor, and the internal ground voltage is applied to the source and the bulk. A second NMOS transistor applied to the gate and an external power supply voltage is applied to the gate; a node connected to the gate of which the drain and the drain of the second NMOS transistor are commonly connected; And a third NMOS transistor configured to apply an internal ground voltage to the drain to output a reference voltage at the drain. In the semiconductor memory device of claim 2, The level shift means An external power supply voltage is applied to the source and the bulk, a gate is commonly connected, and a gate is commonly connected to a drain, and a drain is connected to drains of the first and second PMOS transistors. A fourth NMOS transistor connected to each other, a gate connected in common, an internal ground voltage applied to a bulk, and a fifth NMOS transistor connected to an internal ground voltage applied to a source, and a gate connected to a drain in common; A semiconductor comprising an input buffer including a resistor connected between a drain of the MOS transistor and an internal ground voltage, wherein a set voltage is output from a common connected drain of the second PMOS transistor and the fifth NMOS transistor. Memory device. In the semiconductor memory device of claim 2, The multiplexer An external power supply voltage is applied to the source and the bulk, and a third PMOS transistor having a gate connected in common, a fourth PMOS transistor having a gate connected in common to a drain, and a drain connected to drains of the third and fourth PMOS transistors, respectively. And a sixth NMOS transistor and a seventh NMOS transistor to which an internal ground voltage is applied to a bulk, a source is commonly connected, and the set voltage is applied to a gate, and a drain of the sixth and seventh NMOS transistors An eighth NMOS transistor connected to a commonly connected source, an internal ground voltage applied to the source and the bulk, a set voltage applied to a gate, and a gate and a drain connected to the gate of the seventh NMOS transistor And a ninth NMOS transistor to which an internal ground voltage is applied to the source and the bulk, and between an external power supply voltage and an internal ground voltage. A fifth PMOS transistor, a bulk and a source are connected in series, a gate and a drain are connected in series, an external power supply voltage is applied to the bulk, and a gate is connected to a common connected drain of the third and sixth NMOS transistors. An internal ground voltage is applied to the sixth PMOS transistor and the source and the bulk connected to the gate of the seventh NMOS transistor, and the gate of the drain and the source of the sixth PMOS transistor And a tenth NMOS transistor connected to a commonly connected node such that the voltage at the node where the drain of the fifth PMOS transistor, the source of the sixth PMOS transistor, and the gate of the tenth NMOS transistor are commonly connected to each other is controlled. A semiconductor memory device comprising an input buffer, characterized in that output. In the semiconductor memory device of claim 2, The power supply voltage driver An external power supply voltage is applied to the source and the bulk, a tenth PMOS transistor having a gate connected in common, an eleventh PMOS transistor having a gate connected to a drain, and a drain connected to drains of the tenth and eleventh PMOS transistors, respectively. The 11th NMOS transistor and the 12th NMOS transistor, wherein the internal ground voltage is applied to the bulk, the source is commonly connected, and the control voltage is applied to the gate, and the drain of the 11th and 12th A thirteenth NMOS transistor connected to a commonly connected source, an internal ground voltage applied to the source and the bulk, a set voltage applied to a gate, an external power supply voltage applied to the source and the bulk, and a gate of the tenth A drain connected to a common connected drain of the MOS transistor and the eleventh NMOS transistor, and the drain of the twelfth NMOS transistor And a twelfth PMOS transistor coupled to a gate of the twelfth PMOS transistor to drive a level of a power supply voltage. In the semiconductor memory device of claim 1, Second internal power supply voltage generating means for generating the second internal power supply voltage, Reference voltage generating means for generating a reference voltage by an external power supply voltage; Level shift means for generating a set voltage shifted from the reference voltage; A second multiplexer for outputting a control voltage for maintaining a constant level even if an external power supply voltage increases in a burn-in control signal of the set voltage and the burn-in level detecting means; And a power supply voltage driver configured to output a second internal power supply voltage maintained at a predetermined level by the power supply voltage driver by the control voltage. In the semiconductor memory device of claim 7, The multiplexer An external power supply voltage is applied to the source and the bulk, and a third PMOS transistor having a gate connected in common, a fourth PMOS transistor having a gate connected in common to a drain, and a drain connected to drains of the third and fourth PMOS transistors, respectively. And a sixth NMOS transistor and a seventh NMOS transistor to which an internal ground voltage is applied to a bulk, a source is commonly connected, and the set voltage is applied to a gate, and a drain of the sixth and seventh NMOS transistors An eighth NMOS transistor connected to a commonly connected source, an internal ground voltage applied to the source and the bulk, a set voltage applied to a gate, and a gate and a drain connected to the gate of the seventh NMOS transistor And a ninth NMOS transistor to which an internal ground voltage is applied to the source and the bulk, and between an external power supply voltage and an internal ground voltage. A fifth PMOS transistor, a bulk and a source are connected in series, a gate and a drain are connected in series, an external power supply voltage is applied to the bulk, and a gate is connected to a common connected drain of the third and sixth NMOS transistors. An internal ground voltage is applied to the sixth PMOS transistor and the source and the bulk connected to the gate of the seventh NMOS transistor, and the gate of the drain and the source of the sixth PMOS transistor And a tenth NMOS transistor connected to a commonly connected node such that the voltage at the node where the drain of the fifth PMOS transistor, the source of the sixth PMOS transistor, and the gate of the tenth NMOS transistor are commonly connected to each other is controlled. A semiconductor memory device comprising an input buffer, characterized in that output. In the semiconductor memory device of claim 1, The input buffer is a semiconductor memory device including an input buffer, characterized in that using a CMOS inverter type input buffer or a differential type input buffer. In the semiconductor memory device of claim 9, The CMOS inverter type input buffer First and second inverters for sequentially inverting an enable signal, and a first P that is connected in series between an internal power supply voltage and an internal ground voltage, and has a gate connected in common to apply an internal power supply voltage to a bulk to which an external input signal is applied. A first NMOS transistor, to which an internal ground voltage is applied to a MOS transistor and a bulk, a second NMOS transistor, to which an output of the second inverter is applied to a gate, and an internal ground voltage to a bulk, and an internal power supply voltage to a source. A second PMOS transistor applied to and controlled by the output of the second inverter being applied to a gate to pull up a voltage of a common connected drain of the first PMOS transistor and the first NMOS transistor; Level shift means for shifting a voltage of a common connected drain of the first NMOS transistor; A semiconductor memory device comprising the input buffer, characterized in that the force reversal configured by including a third inverter for outputting the output signal. In the semiconductor memory device of claim 10, The level shifting means is connected in series between an internal power supply voltage and an internal ground voltage to invert a voltage of a common connected drain of the first PMOS transistor and the first NMOS transistor, so that a bulk may have an internal power supply voltage and an internal ground voltage. A third PMOS transistor and a third NMOS transistor connected to a common gate thereof, a power supply voltage is applied to the source and the bulk 2, and fourth and fifth PMOS transistors having a gate connected to the drains of each other, and a drain Respectively connected to a drain of the fourth and fifth PMOS transistors, a ground voltage is applied to a source, and a gate is commonly connected to the first PMOS transistor and the first NMOS transistor, respectively, and the fourth PMOS transistor And fourth and fifth NMOS transistors connected to a common connected drain of the fourth NMOS transistor. And an input buffer for outputting a voltage of a drain connected in common between the fifth PMOS transistor and the fifth NMOS transistor. In the semiconductor memory device of claim 9, The differential type input buffer A first PMOS transistor to which an internal power supply voltage is applied to a source, a gate is commonly connected, and an internal power supply voltage is applied to a bulk, a second PMOS transistor having a gate and a drain connected in common, and a drain to the first and second First and second NMOS transistors connected to the drain of the PMOS transistor, the source is commonly connected, an internal ground voltage applied to the bulk, and an external input signal and an internal reference voltage applied to the gate, respectively, A third NMOS transistor connected to a common source of the first and second NMOS transistors, an internal ground voltage applied to a drain and a bulk, and an enable signal applied to a gate; Level shifting means for shifting the voltage of the common-connected drain of the first NMOS transistor and the output of the level shifting means is inverted. The semiconductor memory device includes an input buffer, characterized in that configured to include a third inverter for outputting the output signal. In the semiconductor memory device of claim 12, The level shift means In order to invert the voltage of the common connected drain of the first PMOS transistor and the first NMOS transistor, the bulk is connected between an internal power supply voltage and an internal ground voltage so that an internal power supply voltage and an internal ground voltage are applied, respectively, and a gate A third PMOS transistor and a third NMOS transistor commonly connected to each other, a power source voltage is applied to the source and the bulk 2, and the fourth and fifth PMOS transistors having gates connected to drains of each other, and the drains of the fourth and fifth PMOS transistors; 5 is connected to the drain of the 5 PMOS transistor, a ground voltage is applied to the source, and a gate is commonly connected to the drain of the first PMOS transistor and the first NMOS transistor, and the fourth PMOS transistor and the fourth NMOS, respectively. The fifth PMOS transistor includes fourth and fifth NMOS transistors connected to a common connected drain of the transistor. A semiconductor memory device comprising the input buffer, characterized in that the register in the fifth en which the output voltage of the common connected drains of the MOS transistors. The semiconductor memory device of claim 1 or 12, wherein Internal reference voltage generating means for generating the internal reference voltage, Reference voltage generating means for generating a reference voltage by an external power supply voltage; Level shift means for generating a set voltage shifted from the reference voltage; A multiplexer for outputting a control voltage for maintaining a constant level of the burn-in control signal of the set voltage and the burn-in level detecting means even when the external power supply voltage increases in the normal operation and the burn-in mode; And a power supply voltage driver configured to output an internal reference voltage maintaining a constant level by the power supply voltage driver by the control voltage. In the semiconductor memory device of claim 14, The multiplexer An external power supply voltage is applied to the source and the bulk, and a third PMOS transistor having a gate connected in common, a fourth PMOS transistor having a gate connected in common to a drain, and a drain connected to drains of the third and fourth PMOS transistors, respectively. And a sixth NMOS transistor and a seventh NMOS transistor to which an internal ground voltage is applied to a bulk, a source is commonly connected, and the set voltage is applied to a gate, and a drain of the sixth and seventh NMOS transistors An eighth NMOS transistor connected to a commonly connected source, an internal ground voltage applied to the source and the bulk, a set voltage applied to a gate, and a gate and a drain connected to the gate of the seventh NMOS transistor And a ninth NMOS transistor to which an internal ground voltage is applied to the source and the bulk, and between an external power supply voltage and an internal ground voltage. A fifth PMOS transistor, a bulk and a source are connected in series, a gate and a drain are connected in series, an external power supply voltage is applied to the bulk, and a gate is connected to a common connected drain of the third and sixth NMOS transistors. An internal ground voltage is applied to the sixth PMOS transistor and the source and the bulk connected to the gate of the seventh NMOS transistor, and the gate of the drain and the source of the sixth PMOS transistor And a tenth NMOS transistor connected to a commonly connected node such that the voltage at the node where the drain of the fifth PMOS transistor, the source of the sixth PMOS transistor, and the gate of the tenth NMOS transistor are commonly connected to each other is controlled. A semiconductor memory device comprising an input buffer, characterized in that output.