TW201638948A - Semiconductor memory device for driving sub word lines - Google Patents

Abstract

The semiconductor device incorporates a selected sub word line driver and a voltage switching circuit. The selected sub word line driver has an input node connected to a selected main word line, an output node connected to a selected sub word line, and a power node. The voltage switching circuit selectively supplies a first power voltage, a second power voltage, or the common reference voltage to the power node. In an active mode, the voltage switching circuit supplies the first power voltage to pull the selected sub word line to a logic high level. In a precharge mode, the voltage switching circuit supplies the common reference voltage and then supplies the second power voltage, thereby pulling the selected sub word line to a logic low level.

Description

Semiconductor memory component that drives sub-word lines

The present invention relates to a semiconductor memory device including a sub-word line driver.

The first figure shows a circuit diagram of a conventional word line driver 100. The word line driver 100 includes a main word line driver 10 and a plurality of sub-word line drivers 12 and 14. Each of the sub-word line drivers 12 and 14 includes a PMOS transistor P1 and an NMOS transistor N1.

The sub-word line drivers 12 and 14 are controlled by a main word line MWL. When a memory device operates in an active mode, the main word line MWL is selected to be a logic 0 level, and a boost voltage VH is supplied to the source of the PMOS transistor P1. Therefore, the PMOS transistor P1 is turned on and the NMOS transistor N1 is turned off, thereby increasing the primary word line SWL to the logic 1 level (VH potential).

When the memory element operates in a precharge mode, the main word line MWL is selected to be a logic 1 level, and a ground voltage GND is supplied to the source of the PMOS transistor P1. Therefore, the PMOS The transistor P1 will be turned off and the NMOS transistor N1 will be turned on, by pulling the sub-word line SWL to the logic 0 level. Under this condition, the PMOS transistor P1 experiences a large gate-to-source potential difference, and a Gate Induced Drain Leakage (GIDL) phenomenon occurs during this period. When the memory device operates in a precharge mode or a standby mode, the GIDL phenomenon affects low power semiconductor components.

A semiconductor memory device according to an embodiment of the invention includes a first word line driver and a first voltage switching circuit. The first word line driver has an input coupled to a selected main word line, an output coupled to a selected sub-word line, and a reference biased to a ground voltage End and a power supply. The first voltage switching circuit is configured to select one of a first supply power source, a second supply power source, and the ground voltage to the power supply end of the first time word line driver. In an active mode, the first voltage switching circuit outputs the first supply power to the power terminal of the first word line driver, and pulls the selected sub-word line to a logic high level. In a precharge mode, the first voltage switching circuit outputs the ground voltage to the power terminal of the first word line driver, and then outputs the second power source to the power source of the first word line driver End, pull the selected sub-word line to a logical low level. The potential of the second supply source is between the potential of the first supply source and the potential of the ground voltage.

100‧‧‧word line driver

10‧‧‧Main word line driver

12,14‧‧‧ character line driver

200‧‧‧word line driver

20‧‧‧ instruction decoder

21‧‧‧Main word line driver

23‧‧‧second character line driver

24‧‧‧First set of sub-character line drivers

26‧‧‧Second set of sub-character line drivers

28‧‧‧Voltage switching unit

42,42', 42"‧‧‧ source voltage generator

422,422',422"‧‧‧ delay circuit

424,424’,424”‧‧‧OR gate

44,44’,44”‧‧‧Decoder

46,46’,46”‧‧ ‧ position shifter

M1-M10‧‧‧O crystal

M11, M11', M11"‧‧‧O crystal

M12, M12', M12"‧‧‧O crystal

MWL0, MWL1‧‧‧ main character line

P1‧‧‧O crystal

N1‧‧‧O crystal

SC_0-SC_7‧‧‧ voltage switching circuit

SD_0-SD_15‧‧‧ character line driver

SWL0-SWL15‧‧‧ character line

The first figure shows a circuit diagram of a conventional word line driver.

The second figure shows a block diagram of a semiconductor memory device having a sub-word line driver in accordance with an embodiment of the present invention.

The third figure shows a block diagram of the voltage switching unit in accordance with an embodiment of the present invention.

The fourth figure shows a detailed circuit diagram of the voltage switching circuit shown in the third figure.

The fifth graph shows the waveform of the sub-line driver when it is operating.

The sixth figure shows a detailed circuit diagram of the voltage switching circuit shown in the third figure.

Figure 7 shows the waveform of the sub-line driver when it is operating.

The eighth figure shows a detailed circuit diagram of the sub-word line driver shown in the second figure.

The ninth diagram shows waveform diagrams of the sub-word line drivers and the voltage switching circuits shown in the eighth diagram.

Certain terms are used throughout the description and following claims to refer to particular elements. It should be understood by those of ordinary skill in the art that manufacturers may refer to the same elements by different nouns. The scope of this specification and the subsequent patent application do not use the difference of the names as the means for distinguishing the elements, but the difference in function of the elements as the criterion for distinguishing. The term "including" as used throughout the specification and subsequent claims is an open term and should be interpreted as "including but not limited to". In addition, the term "coupled" is used herein to include any direct and indirect electrical connection. Therefore, if a first device is coupled to a second device, it means that the first device can be directly electrically connected to the second device or indirectly electrically connected to the second device through other devices or connection means.

The second figure shows a block diagram of a semiconductor memory device having a sub-word line driver in accordance with an embodiment of the present invention. Referring to the second figure, a word line driver 200 includes an instruction decoder 20, a main word line driver 21, a primary word line driver 23, a first set of sub-word line drivers 24, and a second set of sub-words. The line driver 26 and a voltage switching unit 28.

Referring to the second figure, the instruction decoder 20 is configured to decode an instruction CMD and generate different output results according to the instruction CMD. For example, when the command CMD represents an active mode command, the command decoder 20 generates an active signal ACT; when the command CMD represents a precharge mode command, the command decoder 20 generates a precharge signal. PRE.

The main word line driver 21 is operative to drive 128 main word lines in response to eight higher column address signals ADDR (3-10) in active mode. The main character lines contain main character lines MWL0 and MWL1. Referring to the second figure, the main word line MWL0 is coupled to the sub-word lines SWL0 to SWL7 of the memory cell (not shown). The main word line MWL1 is correspondingly coupled to the sub-character lines SWL8 to SWL15 of the memory unit cell (not shown).

Referring to the second figure, the first set of sub-word line drivers 24 includes eight sub-word line drivers SD_0 through SD_7. The sub-character line driver SD_0 has an input coupled to the main word line MWL0, an output coupled to the primary word line SWL0, a reference terminal biased to a ground voltage GND, and configured to receive A power supply terminal of a supply voltage SWH0 from the voltage switching unit 28. The other sub-word line drivers SD_1 to SD_7 have a configuration similar to that of the sub-word line driver SD_0.

Referring to the second figure, the second set of sub-word line drivers 26 includes eight sub-word line drivers SD_8 through SD_15. The sub-character line driver SD_8 has an input coupled to the main word line MWL1, an output coupled to the primary word line SWL8, a reference terminal biased to the ground voltage GND, and configured to receive A power supply terminal of the supply voltage SWH0 from the voltage switching unit 28. The other sub-word line drivers SD_9 to SD_15 have a configuration similar to that of the sub-word line driver SD_8.

The third figure shows a block diagram of the voltage switching unit 28 in conjunction with an embodiment of the present invention. Referring to the third diagram, the voltage switching unit 28 includes a plurality of voltage switching circuits SC_0 to SC_7 that receive the precharge signal PRE and three lower column address signals ADDR(0-2). Please refer to the second figure and the third figure at the same time, the circuit SC_0 is used to provide the output voltage SWDH0 to the sub-word line driver SD_0 and the second group sub-word line driver in the first group of sub-word line drivers 24. Secondary character line driver SD_8 in 26. The circuit SC_7 is configured to provide the output voltage SWDH7 to the sub-word line in the first set of sub-character line drivers 24. The driver SD_7 and the second word line driver SD_15 in the second group of sub-word line drivers 26. The voltage switching circuits SC_0 to SC_7 have similar circuit configurations.

The fourth figure shows a detailed circuit diagram of the circuit SC_0 shown in the third figure. Referring to the fourth figure, the circuit SC_0 includes a source voltage generator 42, a decoder 44, a one-bit shifter 46, a PMOS transistor M11, and an NMOS transistor M12. The decoder 44 generates a signal S1 by decoding the lower column address signal ADDR (0-2). The level shifter 46 is for converting the low voltage potential of the input stage S1 to the high voltage potential S2. The source voltage generator 42 is configured to generate a bias voltage VA applied to the NMOS transistor M12.

Referring to the fourth diagram, the source voltage generator 42 includes a delay circuit 422 and an OR gate 424. The delay circuit 422 is configured to receive the precharge signal PRE and delay the precharge signal PRE for a time interval. The OR gate circuit 44 is configured to receive a delay signal SDLY from the circuit 42 and an input signal /S1 (the input signal /S1 is an inverted signal of the signal S1) to generate the bias applied to the NMOS transistor M12. Voltage VA.

Referring now to the second figure, the sub-word lines SWL0 to SWL15 are respectively driven by the sub-word line drivers SD_0 to SD_15. Each of the sub-word line drivers SD_0 to SD_15 is an output signal from one of the main word lines MWL0 and MWL1 and a plurality of sub-primary characters from the sub-word line driver 23 The line enable signals SE0 to SE7 are controlled by one of them. In an embodiment of the invention, the main character is operated when the active mode is operating. The line driver 21 first selects to drive the main word line MWL0 according to the higher column address signal ADDR(3-10), and the sub word line driver 23 first selects the driving according to the lower column address signal ADDR(0-2). The character line SWL0. The operation of the sub-word line driver SD_0 will be described below with reference to the waveform diagrams of the fifth diagram and the circuit diagrams of the second and fourth diagrams.

Referring now to the fifth diagram, at time t0, the memory element operates in an active mode. Therefore, the precharge signal PRE is not enabled and is at the logic 0 level. The decoder 44 generates a signal S1 having a logic 0 level, and the level shifter 46 generates a drive signal S2 having a GND potential. Therefore, the NMOS transistor M12 is turned off and the PMOS transistor M11 is turned on. In this manner, the circuit SC_0 supplies a power supply voltage VH to the sub-word line driver SD_0 to pull the sub-word line SWL0 to a logic 1 level.

As shown in the fifth figure, at time t1, the semiconductor element enters a precharge mode. Therefore, all main character lines are not driven and fall to the logic 1 level. The precharge signal PRE is enabled and is at a logic 1 level. After receiving the precharge signal PRE from the instruction decoder 20 of the second figure, the delay circuit 422 of the fourth figure delays the precharge signal PRE for a time interval td. In this embodiment, the time interval td is a bank precharge to bank active time interval (tRP). After this time interval td, the delay signal SDLY will transition to a logic 1 level. Therefore, the potential of the bias voltage VA generated by the source voltage generator 42 is quickly turned from the ground voltage GND to the power supply voltage VCC.

Referring to the fourth and fifth figures, in the precharge mode, the level shifter 46 outputs a driving signal S2 having a potential of the power supply voltage VH, which turns on the NMOS transistor M12 and turns off the PMOS transistor M11. Therefore, the circuit SC_0 supplies the bias voltage VA to the sub-word line driver SD_0. By changing the potential of the bias voltage VA supplied to the transistor M12, the circuit SC_0 supplies the ground voltage GND as a driving voltage to the sub-word line driver SD_0 before time t2. The circuit SC_0 supplies the power supply voltage VCC as a driving voltage to the sub-word line driver SD_0 after time t2.

In this embodiment, the potential of the power supply voltage VCC is lower than the potential of the power supply voltage VH, and the potential of the power supply voltage VCC is higher than the potential of the ground voltage GND. As described above, after the memory element enters the precharge mode, the circuit SC_0 supplies a lower potential driving voltage to the sub word line driver SD_0, and then supplies a higher potential driving voltage to the sub word line driver SD_0. Therefore, the falling speed of the character line SWL0 is increased. After time t2, the circuit SC_0 maintains the output voltage at the potential of the power supply voltage VCC. In this manner, since the PMOS transistor M1 in the sub-word line driver SD_0 is in the off state in the precharge mode, the GIDL current can be effectively reduced.

The fourth and fifth figures show circuit diagrams and waveform diagrams of the sub-word line driver SD_0 and the voltage switching circuit SC_0 when the main bit line MWL0 and the sub-bit line SWL0 are selected to be driven in the active mode. Referring now to the second figure, for the sub-word line driver SD_7, the corresponding main bit line MWL0 is selected, and the sub-bit line SWL7 is not selected to be driven. In this condition Next, the circuit SC_7 in the voltage switching unit 28 in the third figure provides an output voltage SWDH7 to the sub-word line driver SD_7. The operation of the sub-word line driver SD_7 will be described below with reference to the waveform diagrams of the seventh diagram and the circuit diagrams of the second and sixth diagrams.

At time t0, the memory element operates in an active mode. Therefore, the precharge signal PRE is not enabled and is at the logic 0 level. The decoder 44' generates a signal S1' having a logic 1 level by decoding the column address signal ADDR such that the NMOS transistor M12' is turned on to turn off the PMOS transistor M11'. Therefore, the circuit SC_7 supplies a power supply voltage VA' to the sub-word line driver SD_0. In the active mode, the source voltage generator 42 generates the bias voltage VA' having a potential of the ground voltage GND.

At time t1, the semiconductor component enters a precharge mode. Therefore, all main character lines are not driven and fall to the logic 1 level. The precharge signal PRE is enabled and is at a logic 1 level. After receiving the precharge signal PRE from the instruction decoder 20 of the second figure, the delay circuit 422' of the fourth figure delays the precharge signal PRE for a time interval td. After this time interval td, the delay signal SDLY' will transition to a logic 1 level. Therefore, the potential of the bias voltage VA' generated by the source voltage generator 42' is quickly turned from the ground voltage GND to the power supply voltage VCC.

In addition, in the precharge mode, the sub-word line driver 23 of the second figure outputs the sub-primary word line enable signals SE0 to SE7 having a logic 1 level, which pulls down the corresponding sub-word line to the ground. The potential of the voltage GND. When When the memory element enters the active mode from the precharge mode, the secondary main word line enable signals SE1 to SE7 maintain a logic 1 level, and the secondary main word line enable signal SE0 is enabled before the secondary word line SWL0 is enabled. It will pull down to the potential of the ground voltage GND.

Referring to the sixth and seventh figures, in the precharge mode, the level shifter 46' outputs a drive signal S2' having a logic 1 level, which turns the NMOS transistor M12' on and causes the PMOS transistor M11' is turned off, therefore, the circuit SC_7 supplies the bias voltage VA' to the sub-word line driver SD_7. The potential of the bias voltage VA' is maintained at the power supply voltage VCC after time t2. Therefore, the GIDL current generated by the transistor M3 in the precharge mode can be lowered by this bias.

As described above, the fourth to seventh figures show circuit diagrams and waveform diagrams of the sub-word line drivers SD_0, SD_7 and the voltage switching circuits SC_0, SC_7 if the main bit line MWL0 is selected in the active mode. . Referring now to the second figure, in another embodiment of the present invention, another main bit line MWL1 is not selectively driven at this time. Since the voltage switching unit 28 supplies power to the sub-word line driver according to the lower column address signal ADDR(0-2) instead of the higher column address signal ADDR(3-10). The supply voltage SWDH0 of the sub-word line driver SD_8 is the supply voltage SWDH0 of the sub-word line driver SD_0, and the supply voltage SWDH7 of the sub-word line driver SD_15 is the supply voltage SWDH7 of the sub-word line driver SD_7.

The eighth diagram shows a detailed circuit diagram of the sub-word line drivers SD_8 to SD_15 shown in the second figure. The sub-word line driver SD_8 to The SD_15 receives the supply voltages SWDH0 to SWDH7 from the voltage switching unit 28, respectively. The ninth diagram shows waveform diagrams of the sub-word line drivers SD_8 and SD_15 and the voltage switching circuits SC_0 and SC_7 shown in the eighth diagram. The main bit line MWL1 is not selected in the eighth and ninth figures.

Referring to the eighth and ninth diagrams, for the PMOS transistor M6 in the sub-word line driver SD_8, the source is biased to the potential of the power supply voltage VCC between time t2 and time t3, and The gate is biased to the potential of the supply voltage VH. Therefore, the GIDL current of the PMOS transistor M6 can be lowered during this period. For the PMOS transistor M9 in the sub-word line driver SD_15, between time t2 and time t3, its source is biased to the potential of the power supply voltage VCC, and its gate is biased to the power supply voltage VH. Potential. Therefore, the GIDL current of the PMOS transistor M9 can be lowered during this period.

The technical and technical features of the present invention have been disclosed as above, and those skilled in the art can still make various substitutions and modifications without departing from the spirit and scope of the invention. Therefore, the scope of the invention should be construed as not limited by the scope of the invention, and the invention is intended to be

42‧‧‧Source voltage generator

422‧‧‧Delay circuit

424‧‧‧OR gate

44‧‧‧Decoder

46‧‧‧ position shifter

M1, M2‧‧‧ transistor

M11, M12‧‧‧ transistor

MWL0‧‧‧ main character line

SC_0‧‧‧ voltage switching circuit

SD_0‧‧‧ character line driver

SWL0‧‧‧ character line

Claims (10)

A semiconductor memory device comprising: a first word line driver having an input coupled to a selected main word line, an output coupled to a selected sub-word line, a reference terminal and a power supply terminal biased to a ground voltage; and a first voltage switching circuit for selectively outputting one of the first supply power, the second supply power, and the ground voltage to the first The power terminal of the sub-character line driver; wherein, in an active mode, the first voltage switching circuit outputs the first power supply to the power terminal of the first-time word line driver, and pulls the selected one a second word line to a logic high level; wherein, in a precharge mode, the first voltage switching circuit outputs the ground voltage to the power terminal of the first word line driver, and then outputs the second power source Up to the power supply end of the first word line driver, pulling the selected sub-word line to a logic low level; and wherein the potential of the second supply power source is between the potential of the first supply power source and Grounding Among potential. The semiconductor memory device of claim 1, wherein the first word line driver comprises: a PMOS transistor coupled to the power terminal of the first word line driver in the active mode The selected sub-character line; An NMOS transistor coupled to the ground voltage of the first word line driver in the precharge mode to the ground voltage. The semiconductor memory device of claim 1, further comprising: a second word line driver having an input coupled to the selected main word line, coupled to a first unselected An output terminal of the sub-character line, a reference terminal biased to the ground voltage, and a power supply terminal; and a second voltage switching circuit for selectively outputting the first supply power, the second supply power, and the One of the ground voltages to the power terminal of the second word line driver; wherein, in the active mode, the second voltage switching circuit outputs the ground voltage to the power source of the second word line driver And wherein, in the pre-charging mode, the second voltage switching circuit outputs the ground voltage to the power terminal of the second-order word line driver, and then outputs the second supply power to the second character The power supply end of the line driver. The semiconductor memory device of claim 3, wherein the second word line driver comprises: a PMOS transistor coupled to the power terminal of the second word line driver in the active mode a first unselected sub-word line; and an NMOS transistor coupled to the first unselected sub-word line to the ground voltage in the pre-charge mode. According to the semiconductor memory component of claim 1 of the patent scope, the method further includes: a third word line driver having an input coupled to an unselected main word line, an output coupled to a second unselected sub-word line, biased to the ground voltage a reference terminal and a power terminal; wherein, in the active mode, the first voltage switching circuit outputs the first supply power to the power terminal of the third sub-line driver; and wherein, in the pre-charging In the mode, the first voltage switching circuit outputs the ground voltage to the power terminal of the third word line driver, and then outputs the second power source to the power terminal of the third word line driver. The semiconductor memory device of claim 5, wherein the third word line driver comprises: a first NMOS transistor, wherein the second unselected word line is coupled to the ground in the active mode And a second NMOS transistor coupled to the second unselected sub-word line to the ground voltage in the pre-charge mode. The semiconductor memory device of claim 6 further comprising: a fourth word line driver having an input coupled to the unselected main word line, coupled to a third unselected An output terminal of the sub-character line, a reference terminal biased to the ground voltage, and a power supply terminal; wherein, in the active mode, the second voltage switching circuit outputs the ground voltage to the fourth character The power terminal of the line driver; and The second voltage switching circuit outputs the ground voltage to the power terminal of the fourth character line driver, and then outputs the second power supply to the fourth character line driver. The power terminal. The semiconductor memory device of claim 7, wherein the fourth word line driver comprises: a third NMOS transistor, wherein the third unselected word line is coupled to the ground in the active mode And a fourth NMOS transistor coupled to the ground voltage by the third unselected sub-word line in the pre-charge mode. The semiconductor memory device of claim 1, wherein the first voltage switching circuit comprises: a delay circuit for generating a first time interval when the semiconductor memory device enters the precharge mode by the active mode a PMOS transistor coupled to the first supply power source to the power supply terminal of the first word line driver in the active mode; and an NMOS transistor at the first time interval in the precharge mode The ground voltage is coupled to the power terminal of the first word line driver, and the second power source is coupled to the first word line driver at a second time interval after the first time interval The power end. The semiconductor memory device of claim 3, wherein the second voltage switching circuit comprises: a delay circuit for generating a first time interval when the semiconductor memory device enters the precharge mode by the active mode; and an NMOS transistor coupled to the ground voltage to the second time in the active mode The power terminal of the word line driver, in the pre-charging mode, coupling the ground voltage to the power terminal of the second character line driver in the first time interval, and after the first time interval The second supply time is coupled to the power supply end of the second sub-line line driver.