JPH03125397A - Memory for logic definition - Google Patents

Abstract

PURPOSE:To securely write and read data with simple constitution by adjusting the gate voltage of an FET between storage parts and varying the mutual conductance values of a couple of data lines as required. CONSTITUTION:When Q=1 and Q=0 are written in nodes Q=0 and Q=1 of the FF3 of a storage part, a data line D and data line, the inverse of D are held at high and low potentials respectively. The output of a decoder 7 is 0 and a read/write signal R/W is 0; and a transistor(TR) P4 turns off and a driver 4 is connected to only a power source VDD and a TRP3. Then the gate voltage amplitudes of FETsN3 and N4 between the FF and a data line increase in the ON direction through a word line W and the mutual conductance values of the FETsN3 and N4 increase to perform secure writing operation without making the constitution complex. When the storage contents of the FF3 are read out to a logic block L, the mutual conductance values of the FETsN3 and N4 decrease similarly and sure reading operation is performed without being affected by the data line.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a logic definition memory for defining the state of a predetermined logic block, and in particular, to a logic definition memory for defining the state of a predetermined logic block, and in particular, to a logic definition memory for defining the state of a predetermined logic block. Even if
This is to prevent malfunctions from occurring in the logic blocks.

[Conventional technology]

As a logic definition memory, for example, Nikkei Electronics, 1986. No. 403, pages 246-248 (Nikkei McGraw-Hill), a device using static RAM is known.

FIG. 2 is a circuit diagram showing an example of a logic definition memory M using a static RAM, in which a pair of data lines are arranged parallel to each other, and between them are a PMOS transistor P and an NMO3I transistor. - C consisting of transistors N,
A flip-flop 3 is provided as a storage section, which is configured by cross-linking a MOS inverter 1 and a CMOS inverter 2 consisting of a PMO transistor P2 and an NMOS transistor Nt.

The output side of one CMOS inverter 1 is connected to the data line via an NMO3I-transistor N, which is an MO3 type field effect transistor, and the output side of the other CMOS inverter 2 is similarly connected to the data line via an NMOS transistor N4. Furthermore, the gates of NMOS transistors N and N4 are connected to word line W.

With such a configuration, as is well known, when the power is turned on, the flip-flop 3 has a node Q=l (u=0) or a node Q=0 ('C=1). Can store 1 bit data.

One node Q of the flip-flop 3 is supplied to the gate of a switching transistor S interposed between the input terminal A and the output terminal 8 of the logic block.

Therefore, the data stored in the flip-flop 3 has a logic value of "1".
(i.e., the node Q is at a high potential), the switching transistor S is turned on and the terminals A and B are connected, and the data stored in the flip-flop 3 becomes the logical value "0" (i.e., the node Q is at a high potential). (low potential), the switching transistor S is turned off and terminals A and B are disconnected.

[Problem to be solved by the invention]

However, in the conventional logic definition memory M mentioned above, especially in the process of developing a program using the logic block L, the storage contents of the logic definition memory M are read out in order to know the state of the logic block. If you do so, the following problems will occur.

That is, when reading the data stored in the flip-flop 3 using the data line U, first precharge the data line U and set them to the power supply voltage (for example,
5V), it is necessary to bring the word line W to a high potential (for example, 5V), turn on the NMOS transistors N and N4, and bring the flip-flop 3 and the data line U into conduction. .

Therefore, for example, if the internal state of the flip-flop 3 is node Q = 1 (for example, 5■ which is the power supply voltage) and node times = 0 (for example, OV which is the ground voltage),
A current (2) as shown by the chain line arrow in FIG. 2 flows from the data line (2) through the NMOS transistors N4 and N2.

Then, a voltage drop occurs in transistors N4 and N2, which act as normal electrical resistance (<NMO3), so CMO
The potential of the node which is the output of the S inverter 2 rises from 0■, a change also occurs in the CMOS inverter 1 to which the node voltage is supplied, and the potential of the node Q falls.

Furthermore, even if the node Q is O, current flows from the data line through the NMO3) transistor N and NI, so the potential of the node Q rises and the potential of the node It goes down.

As a result, the switching transistor S of the logic block L to which the node Q is supplied is likely to malfunction, which will hinder the program development work.

Such a problem occurs when the precharged data line
Node Q when conducting U to flip-flop 3,
This problem can be solved by minimizing the change in the potential of Q.

In other words, in the example shown in FIG. 2, the voltage drop in NMOS transistors N and N4 is made larger than the voltage drop in NMOS transistors N1 and Nt. The drain current characteristics relative to the gate voltage may be made smaller than those of the NMOS transistors N and Nt.

However, if the mutual conductance of NMO3) transistors N and N4 is simply made small, the above-mentioned problem when reading data from the flip-flop 3 to the data line and U can be solved, but Even when writing data to flip-flop 3, NMO3
) transistor N.

And because the voltage drop at N4 becomes large,
There are cases where it becomes impossible to invert the node Q, ■.

The present invention has been made focusing on the problems that need to be solved with the conventional technology, and an object of the present invention is to provide a logic definition memory that can eliminate problems both when reading data and when writing data. It is said that

[Means to solve the problem]

In order to achieve the above object, the invention according to claim (1) includes a storage section disposed between a pair of data lines, and a MOS electric field that controls the conduction state between the pair of data lines and the storage section. and a logic definition memory for supplying data stored in the storage section to a predetermined logic block, the mutual conductance of the MOS type field effect transistor is determined from the data line to the storage section. A mutual conductance control means is provided to increase the mutual conductance when writing and to decrease it when reading data from the storage section to the data line.

Further, the invention according to claim (2) is the invention according to claim (1), wherein the mutual conductance control means controls the amplitude of the gate voltage of the MOS type field effect transistor in the conduction direction to the data line. When data is written from the storage section to the data line, it is made large, and when data is read from the storage section to the data line, it is made small.

[Effect]

According to the invention set forth in claim (1), when writing data from the data line to the storage section, the mutual conductance control means controls the mutual conductance of the MOS field effect transistors that control the conduction state between the pair of data lines and the storage section. Since the conductance is increased, the voltage drop in the MOS field effect transistor is small, so data can be written to the memory section reliably, and when reading data from the memory section to the data line, the mutual conductance control means Since the mutual conductance of the MOS type field effect transistor is reduced, the voltage drop in the MOS type field effect transistor becomes large, and as a result, changes in internal nodes of the storage section can be made small.

Further, according to the invention described in claim (2), when writing data from the data line to the storage section, the mutual conductance control means controls the amplitude of the gate voltage of the MOS field effect transistor in the conduction direction (for example, the amplitude of the gate voltage of the MOS field effect transistor). If the effect transistor is an N-channel, the amplitude from Ov to 5V,
For P channel, increase the amplitude (from 5■ to 0■)
(For example, if it is an N channel, it is set to 5■, and if it is a P channel, it is set to Ov). Therefore, the mutual conductance of the MOS type field effect transistor becomes large, and when reading data from the storage section to the data line, the mutual conductance control is Since the means reduces the amplitude (for example, to about 2.5 square meters for both N and P channels), the mutual conductance of the MOS field effect transistor becomes small.

〔Example〕

Embodiments of the present invention will be described below based on the drawings.

FIG. 1 is a circuit diagram showing an embodiment of the present invention, and this is a logic definition memory M using static RAM as in FIG. 2. Note that the same parts as in FIG. 2 are denoted by the same reference numerals, and redundant explanation thereof will be omitted.

First, the configuration will be explained.

That is, in this embodiment, a power supply switching circuit 5 as mutual conductance control means is provided on the power supply VCC side of the driver 4 that drives the word line W.

The power supply switching circuit 5 is supplied with a read/write signal R/W which has a logical value "1" when reading from the logic definition memory M and has a logical value "0" when writing.

The read/write signal R/W is directly supplied to the PMOS transistor P4.
is supplied via an inverter 6.

Therefore, when the read/write signal R/W at the time of reading has a logical value "1", the PMOS transistor P,
is off, PMO3) transistor P4 is on, and the read/write signal R/PMO3 is on.
When W is the logical value "0", PMO3) transistor P3 is in the on state and PMOSMOS transistor P
It becomes a blank state.

The low voltage sides of the PMO3) transistors P3 and P4 are connected to the high voltage side of the driver 4, and between the PMO3) transistor P4 and the power supply there are three stages of PMOS transistors Ps, Pb and P, which act as ordinary diodes. , and furthermore, the input side of the driver 4 has a logical value "0" or "1" depending on whether the word line W is selected or not.
A decoder circuit 7 that outputs a signal is connected.

Next, the operation of the above embodiment will be explained.

Now node Q=0. Assuming that we write data such as nodes Q=1 and Q=0 into the flip-flop 3 where Q=1 via the data line U, first, we set the data line to a high potential (for example, 5V) and , the data line ■ is set to a low potential (for example, 0■).

Then, since the word line W is selected by the decoder circuit 7 (the output of the decoder circuit 7 becomes O), the word line W and the power supply switching circuit 5 are connected via the driver 4.

At this time, since the read/write signal R/W has the logical value "0", the PMO3) transistor P3 is in the on state, and the PMO3) transistor P4 is in the off state.
Driver 4 and power supply VCC are PMO3) transistor P,
Connected only through.

Therefore, the voltage on the word line W is a relatively high voltage (for example, 5
V), the amplitude of the gate voltages of NMO3) transistors N and N4 in the conduction direction becomes relatively large, and N
MO3) The mutual conductance of transistors N3 and N4 increases.

Then, Q=0. Q=1 and data line D=1
．． Since U=0, current flows from the data line through the NMOS transistors N and N to the ground side, and
From power supply VDD to PMO3) transistor P2 and NMO3
) Current flows through transistor N4 to data line ■, but NMO3) Since the mutual conductance of transistors N and N4 is large, the voltage drop across them is small, and as a result, the potential of node Q is certain. The potential of the node rises to be approximately equal to the potential of the data line, and the potential of the node falls reliably to become approximately equal to the potential of the data line.

Therefore, a reversal occurs at node 91, Q=1 and summer=0
This means that new data has been written to the flip-flop 3.

Then, when the output of the decoder circuit 7 is set to a logical value "L" and the driver 4 is turned off, the word line W becomes the ground voltage, so the NMO3) transistors N and N4 are turned off, and the flip-flops 3 and There is no conduction between the data line and U.

This completes the write operation to the logic definition memory M.

Next, a case will be described in which the data stored in the flip-flop 3, ie, the states of the nodes Q and Q are read out. However, the current state is node Q=I, Q=O.

First, the data lines and U are precharged to a high potential (for example, 5V), and then, as in the case of writing, the word line W is selected by the decoder circuit 7 (the output of the decoder circuit 7 is from the word line W
and a power supply switching circuit 5 are connected via a driver 4.

At this time, since the read/write signal R/W has a logical value of "1", the PMO3 transistor P3 is turned off and the PMO3 transistor P4 is turned on.
The driver 4 and the power supply V CC are connected through three stages of PMOS transistors P, ~P, which function as diodes, and a PMO3I-transistor P4, which functions as a switch.

Therefore, the power supply voltage is PMO3I-transistor P4~
Since the word line W is supplied to the driver 4 after a large voltage drop through P, the voltage of the word line W is a relatively low value (for example,
2.5■).

Therefore, since the amplitude of the gate voltages of NMOS transistors N3 and N4 in the conduction direction becomes relatively small, the NMOS transistors
S) The mutual conductance of transistors N3 and N4 becomes smaller.

Since Bean = 0, current flows from the data line ■ to the ground side via the NMOS transistors N4 and N2, but since the mutual conductance of the NMOS transistor N4 is small, the voltage drop in the NMOS transistor N4 becomes large, and the relative (NMO3) Since the voltage drop in the transistor N2 becomes smaller, the change in the node q can be suppressed to a smaller value.

As a result, malfunctions are less likely to occur in the switching transistors S of the logic block L to which the data stored in the logic definition memory M is supplied.

Here, according to the simulation conducted by the inventor,
Three PMOS transistors P, -P serving as diodes are inserted between the driver 4 and the power supply V, c (5V) (each PMO3), and the voltage drop in the transistors P, -P7 is about 0.7V. ) and flip-flop 3
It has been confirmed that the voltage displacement of internal nodes Q and Q when reading data within can be suppressed to about 0.35 V, which is sufficiently smaller than the threshold voltage of a normal NMO3I-transistor.

In other words, in the above embodiment to which the present invention is applied, the node Q when reading the data stored in the flip-flop 3,
Changes in summer can be kept to a minimum, and as a result, even if data is read while logic block L is being driven, the state of the logic block will not change, making program development and debugging more efficient. can do well.

Moreover, with the configuration of the above embodiment, the mutual conductance of the NMO3) transistors N and N4 is adjusted by the simple means of switching the drive voltage of the word line W using the read/write signal R/W. The structure is simplified and there is no need for a significant increase in cost.

In the above embodiment, an N-channel MOS transistor N is used as the MO3 type field effect transistor that controls the conduction state between the flip-flop 3 and the data line U.
, and N4 have been described, but this may also be a P-channel MO3 type field effect transistor.

However, the P-channel MO3 field effect transistor is
Since it has a characteristic opposite to that of an N-channel, when making the flip-flop 3 and the data line U non-conductive, the word line W is set to a high voltage (for example, 5V), and the data line is connected to the flip-flop 3. When writing, the word line W is set to a low voltage (for example, OV) so that the amplitude of the gate voltage in the conduction direction becomes large, and when reading data from the flip-flop 3, the gate voltage is set to a low voltage in the conduction direction. The voltage of the word line W is set to an intermediate value (for example, about 2.5V) so that the amplitude is small.

Further, in the above embodiment, a case was explained in which a flip-flop 3 consisting of a pair of CMOS inverters 1 and 2 connected cross-wise was applied as a storage unit.
It is not limited to this, and other structures (for example, P
A structure in which an electric resistance is used in place of the MOSMOS transistor PPt, etc.) may also be used.

〔Effect of the invention〕

As explained above, according to the invention set forth in claim (1), the mutual conductance of the MO3 field effect transistor that controls the conduction state between the data line and the storage section is changed when writing data from the data line to the storage section. By making it large and making it smaller when reading data from the storage section to the data line, data can be written reliably and fluctuations in data stored in the storage section can be kept to an extremely small level even when reading data. There is an effect that it can be done.

Further, according to the invention described in claim (2), the magnitude of the mutual conductance is changed by adjusting the amplitude of the gate voltage of the MO3 field effect transistor in the conduction direction, so that the structure of the device is simplified. This has the effect of not causing a significant increase in costs.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing an embodiment of the present invention, and FIG. 2 is a circuit diagram showing a conventional example. 1.2...CMOS inverter, 3...Flip-flop (storage unit), 4...Driver, 5...Power supply switching circuit (mutual conductance control means), D, U...
Data line, L...logic block, M...memory for logic definition, N, ~N4...NMO3) transistor, N,
. N4...MO3 type field effect transistor, PI-P. ...PMOS transistor

Claims (2)

[Claims] (1) A memory section disposed between a pair of data lines, and an M that controls the conduction state between the pair of data lines and the memory section.
a logic definition memory that supplies data stored in the storage section to a predetermined logic block; 1. A memory for logic definition, comprising mutual conductance control means that increases the mutual conductance when writing data to the memory section and decreases the mutual conductance when reading data from the storage section to the data line. (2) The mutual conductance control means includes the MOS
The amplitude of the gate voltage of the field effect transistor in the conduction direction is increased when writing data from the data line to the storage section, and is decreased when reading data from the storage section to the data line. Memory for logical definition.