JPH0734311B2 - Memory cell - Google Patents

Description

The present invention relates to a static memory cell, and more particularly to a memory cell used in a semiconductor memory device having a multiport function.

[Technical Background of the Invention and Problems Thereof] With the recent development of semiconductor technology, semiconductor memory devices having various functions have been developed. For example, a so-called multi-port type memory cell in which a plurality of word lines and data lines are connected to one memory cell is provided, and reading or writing operation is independently performed in parallel to the plurality of memory cells. There is a storage device to do.

The multi-port type storage device is becoming more and more useful for improving the performance of the microcomputer as a storage device of a microcomputer which is used for a wide range of applications and is widely spread.

FIG. 4 is a circuit diagram showing a 1-bit memory cell of a 2-port storage device.

In the write operation in this memory cell, the high-level or low-level voltage information given to each bit line BL1, ▲ ▼ and the low-level or high-level inversion voltage information whose logic is the reverse of this voltage information are written in the word line. Transfer gate whose conduction is controlled by the potential of WL1
It is performed by being stored in the bistable circuit 9 including the inverter circuits 5 and 7 whose input and output terminals are connected to each other via 1 and 3. In addition, each bit line BL2, ▲ ▼
The voltage information and inversion voltage information given to the word line WL
It is stored in the bistable circuit 9 via the transfer gates 11 and 13 whose conduction is controlled by the potential of 2.

Further, in the read operation in this memory cell, the voltage information and the inversion voltage information stored in the bistable circuit 9 are
Each bit line BL via transfer gates 1, 3
1, sent to ▲ ▼ and performed. Alternatively, the voltage information and the inverted voltage information stored in the bistable circuit 9 are sent to the respective bit lines BL2, ▲ ▼ via the transfer gates 11 and 13 for the purpose.

In this way, by connecting two word lines and four bit lines to one memory cell, a write operation or a read operation is performed in parallel with respect to two arbitrary memory cells arranged in a matrix. And independently. However, in the memory cell having such a configuration, 2
A pair of bit lines is required, and the area occupied by the memory cells with respect to the entire storage device is increased, which is an obstacle to high integration.

The memory cell shown in FIG. 5 is configured so that the number of bit lines in the memory cell shown in FIG. 4 is reduced by one and three bit lines function as three ports (write-only port 1, read-only port 2). It is the one.

In this memory cell, the voltage information stored in the bistable circuit 9 is transmitted to the bit line BL2 via the transfer gate 15 whose conduction is controlled by the potential of the word line WL2, or conducted at the potential of the word line WL3. The data is sent to the bit line BL3 via the controlled transfer gate 17 and the read operation is performed. Further, this memory cell is adapted to perform the write operation using only one bit line BL1.

As described above, in order to surely store the voltage information in the bistable circuit 9 with one bit line BL1, the driving capability of the inverter circuit 19 that constitutes the bistable circuit 9 is made larger than that of the inverter circuit 21. There is a need. Therefore, the inverter circuit 19, the inverter circuit 21 and the transfer gate 1
It is difficult to determine the ratio between the and, which makes it difficult to design the memory cell. Further, since the inverter circuit 19 and the inverter circuit 21 are asymmetrical, the occupied area of the memory cell that requires the highest density in the memory device is increased, and the word line and the bit line are read and written exclusively. It is necessary to prepare, and it has been difficult to achieve high integration even in the memory cell having such a configuration.

The memory cell shown in FIG. 6 is written to the memory cell shown in FIG. 5 by using two bit lines BL1 and BL2 with the inverter circuits 23 and 25 constituting the bistable circuit 9 having the same size. The operation is performed and the read operation is performed using the bit line BL2 or the bit line BL3.

In the memory cell having such a configuration, the voltage information stored in the bistable circuit 9 is transferred to the transfer gate 15 and
When simultaneously sent to the respective bit lines BL2 and BL3 via 17, the potentials at the point A of the bistable circuit 9 are set to a low level state (eg 0V) while the bit lines BL2 and BL3 are in a high level state (eg 5V). If there is, there are two bit lines BL2 and BL3
Simultaneously flows into the point A, and the potential at the point A rises. Therefore, in the worst case, the inverter circuit 25 performs the inversion operation, the potential at the point B becomes the low level state, the potential at the point A becomes the high level state, and the voltage information stored in the bistable circuit 9 is rewritten. There is a risk that

Further, when the voltage information stored in the bistable circuit 9 is sent to the two bit lines BL2 and BL3 at the same time, compared with the case where the voltage information is sent to one of the bit lines, the inverter circuit 23 Since the load of 2 is doubled, there is a problem that the read time becomes long.

[Object of the Invention] The present invention has been made in view of the above, and an object of the present invention is to enable stable and reliable storage operation in a multi-port system without increasing the size of the configuration. Providing a memory cell.

[Summary of the Invention] In order to achieve the above object, according to the present invention, a storage means for storing binary information in a nonvolatile manner and one of the binary information as a first bit based on a potential of a first word line. The first sending means composed of a transistor of the first conductivity type for reading on a line and the storage means and the second bit line are formed on the basis of the potential of the second word line without forming a current path between them. One of the binary information is read to the second bit line, and the second transmission means includes a second conductivity type transistor having a conductivity type different from that of the first conductivity type transistor. To do.

EFFECTS OF THE INVENTION According to the present invention, one piece of information stored in the storage means can be read out to each bit line by the sending means composed of transistors of conductivity types different from each other, and to one bit line. Since it is performed without forming a current path between the storage means and the bit line, the same stored information can be simultaneously and reliably read out to different bit lines without increasing the size of the configuration. It will be possible. As a result, it is possible to provide a memory cell for a multi-port memory that can be accessed at high speed and is easy to design.

Embodiments of the Invention Embodiments of the present invention will be described below with reference to the drawings.

1 to 3 are block diagrams of a memory cell for 1 bit according to the first to third embodiments of the present invention. Each memory cell uses three bit lines and has a three-port function ( (3 ports can be simultaneously read at the time of reading, and 1 port can be simultaneously read at the time of writing).

In the memory cell shown in FIG. 1, the bistable circuit 9 has a fourth
Similar to the memory cell shown in the figure, it is composed of inverter circuits 5 and 7 whose input / output terminals are connected to each other. The bistable circuit 9 has its input / output terminal A connected to the bit line BL1 through an N-channel MOS transistor (hereinafter abbreviated as “NMOS”) 27 whose gate terminal is connected to the word line WL1. The input / output terminal B is connected to the bit line BL2 via the NMOS 29 whose gate terminal is connected to the word line WL2.

Further, the input / output terminal B of the bistable circuit 9 is a P channel MO.
It is connected to the gate terminal of an S-type transistor (hereinafter abbreviated as “POMOS”) 31. The source terminal of the PMOS 31 is connected to the voltage source, and the drain terminal is connected to the source terminal of the PMOS 33. The gate terminal of the PMOS 33 is connected to the word line WL3, and the drain terminal thereof is connected to the bit line BL3 used only when reading voltage information.

Next, a write operation and a read operation of the memory cell thus configured will be described.

First, the write operation will be described. In the write operation, the potentials of the word lines WL1 and WL2 are set to the high level state to bring the NMOSs 27 and 29 into the conductive state. And
The voltage information is applied to the bit line BL1 and the inverted voltage information whose logic level is opposite to this voltage information is applied to the bit line BL1.
Given to BL2. Therefore, the voltage information is given to the input / output terminal A of the bistable circuit 9 via the NMOS 27, and the inverted voltage information is given to the input / output terminal B of the bistable circuit 9 via the NMOS 29 to obtain the voltage information and the inverted voltage. Information is written and stored in the bistable circuit 9.

That is, in the write operation, the two bit lines BL1,
The voltage information is differentially written in the bistable circuit 9 by using BL2. Therefore, the voltage information is stably and surely written without making the inverter circuits 5 and 7 forming the bistable circuit 9 asymmetric.

Next, the read operation will be described. In the memory cell shown in FIG. 1, the voltage information at the input / output terminal B of the bistable circuit 9 is sent to the bit line BL2 to be read out, and the inverted voltage information whose logic level is opposite to this voltage information It is designed to be sent to the bit line BL3 and read.

Before the read operation is started, the bit line BL2 is precharged to a high level state (for example, 5V) and the bit line BL3 is predischarged to a low level state (for example, 0V). In this situation,
For example, when the input / output terminal B of the bistable circuit 9 is in the low level state, the word line WL2 is set to the high level state to bring the NMOS 29 into the conductive state and the word line WL3.
When the PMOS 33 becomes conductive by bringing the bistable circuit 9 into the low level state, the bistable circuit 9 is transferred from the bit line BL2 through the NMOS 29.
A current flows into the input / output terminal B of the. Because of this, the bit line
BL2 becomes a low level state, and the voltage information written in the input / output terminal B of the bistable circuit 9 is read out from the output circuit (not shown) connected to the bit line BL2.

Further, since the input / output terminal B is in the low level state, the PMOS31
Becomes conductive, and a current flows from the voltage source to the bit line BL3 via the PMOS31 and PMOS33. Therefore, the bit line BL3 is in a high level state, and the inverted voltage information whose logic level is opposite to the voltage information written in the input / output terminal B is output circuit (not shown) connected to the bit line BL3. ) Will be read from.

When the input / output terminal B of the bistable circuit 9 is in the high level state, the PMOS 31 is in the non-conducting state and the voltage information of the bit line BL2 precharged to the high level state and
Bit line BL pre-discharged to low level
The voltage information of 3 will be read.

Thus, in the case of reading low level voltage information from the input / output terminal B, the memory cell shown in FIG. 1 forms a current path between the input / output terminal B and the bit line BL2 via the NMOS 29. The low level voltage information to the bit line BL2
I am trying to read through. On the other hand, the low-level voltage information is received by the gate terminal of the PMOS 31, and the PMOS 31 is made conductive so that the voltage source supplies the bit line BL via the PMOS 33.
I / O terminal B and bit line BL3
High-level voltage information is read out via the bit line BL3 without forming a current path between and.

Therefore, even if the potential of the input / output terminal B rises somewhat due to the current flowing from the bit line BL2 to the input / output terminal B, the threshold voltage of the normal PMOS is set to a potential near the power supply potential, and therefore the PMOS31 When the low-level voltage information is sent to the bit line BL3, the gate potential of the PMOS does not become higher than the threshold voltage, and the PMOS 31 does not become non-conductive. Therefore, the low-level voltage information written in the input / output terminal B does not have a possibility of malfunction even if the read operation is simultaneously performed via the respective bit lines BL2 and BL3.

Furthermore, when the voltage information is sent from the input / output terminal B of the bistable circuit 9 to the respective bit lines BL2.BL3 at the same time,
The load of the inverter circuit 5 is one bit line BL1 and P
Only the gate capacitance of MOS31. Therefore, compared with the memory cell shown in FIG. 6, the load of the inverter circuit is considerably reduced, and the voltage information is simultaneously sent to each bit line BL without increasing the size of the inverter circuit 5.
2, Read operation to BL3 can be performed at high speed.

Further, when the inverter circuits 5 and 7 are composed of CMOS (complementary MOS), the number of PMOS and NMOS forming the memory cell is the same. As a result, in the circuit layout in the CMOS process, the occupied area of the PMOS formation region and the occupied area of the NMOS formation region are balanced. Therefore, the increase of the occupied area due to the imbalance of the numbers of PMOS and NMOS is avoided, and the occupied area is not increased as compared with the conventional case.

FIG. 2 is a block diagram of a 1-bit memory cell according to the second embodiment of the present invention. This memory cell is similar to the memory cell shown in FIG. B
Is read out via the bit line BL2, and further, via the bit line BL3, the voltage information having a logic level opposite to that of the voltage information is read out.

The feature of this memory cell is that the voltage information written to the input / output terminal B is controlled to be conductive by the word line WL1.
This is to read through the bit line BL2 that has been pre-discharged to the low level state through the MOS35.

Further, the drain terminal connects the high-level voltage information written in the input / output terminal B and the low-level voltage information whose logic level is opposite to that of the drain terminal to the word line WL3, and connects the drain terminal to the bit line BL3. NMOS39 connected to the source terminal of the connected NMOS37 and the source terminal to ground
Is made conductive and a current is caused to flow from the bit line BL3 precharged to the high level state to the ground through the NMOSs 37 and 39, thereby reading out via the bit line BL3. That is, the current path is not formed between the input / output terminal B of the bistable circuit 9 and the bit line BL3, and the voltage information is sent from the input / output terminal B to the bit line BL3.

Therefore, even with such a configuration, the same effect as that of the first embodiment can be obtained. Incidentally. Those having the same reference numerals as those in FIG. 1 are the same and their explanations are omitted.

FIG. 3 is a block diagram of a 1-bit memory cell according to the third embodiment of the present invention. Similar to the memory cell shown in FIGS. 1 and 2, this memory cell performs a write operation and a read operation. The feature of this memory cell lies in the input / output terminal B of the bistable circuit 9. The voltage information whose logic level is opposite to that of the voltage information written in is controlled by the potential of the word line WL3, the input terminal is connected to the input / output terminal B of the bistable circuit 9, and the output terminal is the bit line. BL
It is to be given to the bit line BL3 via the clocked inverter circuit 41 connected to 3 and read.

With such a configuration, not only the same effect as in the first embodiment can be obtained, but also the bit lines BL1 and BL2 are operated in a synchronous manner and the bit line BL3 is in an asynchronous manner, depending on the system requirements. It also enables irregular movements such as those that are performed with. The same reference numerals as those in FIG. 1 designate the same components, and the description thereof is omitted. Further, instead of the clocked inverter circuit 41, the configuration in which the voltage information at the point B is input to the inverter and the output thereof is given to the bit line via the transfer gate, the same effect can be obtained.

[Brief description of drawings]

1 is a block diagram of a memory cell according to a first embodiment of the present invention, FIG. 2 is a block diagram of a memory cell according to a second embodiment of the present invention, and FIG. 3 is a third view of the present invention. FIG. 4 is a configuration diagram of a memory cell according to the embodiment, and FIGS. 4 to 6 are configuration diagrams showing a conventional example of the memory cell. (Explanation of the symbols indicating the main parts of the figure) 5,7 ...... Inverter circuit 9 ...... Bistable circuit 27,29 ...... N channel MOS type transistor 31,33 ...... P channel MOS type transistor 41 ...... Clocked circuit inverter

Claims (7)

[Claims] 1. A storage means for storing binary information in a nonvolatile manner, and a first conductivity type transistor for reading one of the binary information to a first bit line based on a potential of a first word line. A transistor and a second word line which are composed of a first transmitting means, a second conductivity type of a conductivity type different from the conductivity type of the first conductivity type transistor, and which receives at the gate terminal one of the second value information. Second supply means for reading out information obtained by inverting one of the binary information to the second bit line by applying a power supply potential to the second bit line via a transistor which receives the potential of the above at its gate terminal. A memory cell characterized by. 2. The memory cell according to claim 1, wherein the storage means is composed of a bistable circuit including an inverter circuit having input / output terminals connected to each other. 3. The first sending means is a P-channel FET
2. The memory cell according to claim 1, wherein the memory cell comprises a (field effect transistor), and the second sending means is an N-channel FET. 4. The memory cell according to claim 1, wherein the first sending means is an N-channel FET, and the second sending means is a P-channel FET. 5. In the second sending means, a P channel FET whose conduction is controlled by one of the binary information and a P channel FET whose conduction is controlled by the potential of the second word line are in a power supply low level state. The second precharged to
The memory cell according to claim 1, wherein the memory cell is inserted in series between the memory cell and the bit line. 6. The second sending means includes an N-channel FET whose conduction is controlled by one of the binary information and an N-channel FET whose conduction is controlled by the potential of the second word line, which are grounded power sources. The memory cell according to claim 1, wherein the memory cell is inserted in series with the second bit line precharged to a high level state. 7. A storage means for storing binary information in a non-volatile manner, and a transistor of a first conductivity type for reading one of the binary information to a first bit line based on a potential of a first word line. The binary information is inverted based on the potential of the second word line and its inversion potential, which is composed of a first sending means and a second conductivity type of a conductivity type different from the conductivity type of the first conductivity type transistor. A clocked inverter for reading out information to the second bit line.