JPH07153277A - Static random access memory - Google Patents

Abstract

PURPOSE:To increase the degree of freedom of reading and writing characteristics and to stably operate even if low voltage power supply is used by providing further a transfer gate arranged between a pair of bit lines and a node in a conventional SRAM constitution. CONSTITUTION:Pre-charge is performed so that bit lines NT105, NF106 are both made H state. Successively, a word line N115 is made H state, N type transfer gates 103, 104 are made a selecting state. A word line P116 is also made H state, P type transfer gates 117, 118 are made non-selecting state. L is stored in a node 109 and H is stored in a node 110. Electric charges previously charged in the line NT105 are discharged through the gate 103 and a transistor 111. Next, the node 109 is assumed H state and the node 110 is assumed L state, when these states are written in inverse logic, the line NT105 and a bit line 119 are previously charged to an L state, the line NT106 and a bit line PF120 are previously charged to H state. The line 115 is made H state and the gates 103, 104 are made a selecting state, successively the line P116 is made L state and the P type transfer gates 117, 118 are made a selecting state.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a static random access memory (hereinafter abbreviated as "SRAM"), and particularly, an SRAM that operates even when the power supply voltage is about 1 volt.
Regarding

The present invention is particularly useful when preferably incorporated into a microcomputer.

[0003]

2. Description of the Related Art A typical circuit configuration of a conventional SRAM is shown in FIG. As shown in the figure, the memory cell of the SRAM is composed of two logic inversion gates 401 and 402 and two N-type transfer gates 403 and 404. The logic inversion gates 401 and 402 have their inputs and outputs. Connected to each other. Node 409 is connected to bit line NT405 via N-type transfer gate 403, and node 510 is connected to bit line NF406 via N-type transfer gate 404. The gates of the N-type transfer gates 403 and 404 are word lines N
It is connected to 415.

Next, the operation of the SRAM will be described with reference to FIGS. First, the write operation will be described. The logical value “H” is given to the node 409, and the node 410
It is assumed that the logical value "L" is stored in. At this time, the P-type MOS transistor 412 and the N-type MOS transistor 413 are in the conductive state, and the P-type MOS transistor 414 and the N-type MOS transistor 411 are in the non-conductive state.

From this state, the logical value "L" is given to the node 409.
The case of writing is described below. Generally, in the SRAM, the storage content is changed by setting the node 409 or 410 to the logical value “L”. In this case, the bit line NT405 is precharged to the logical value "L" and the bit line NF406 is precharged to the logical value "H".

Next, the word line N415 is set to the logical value "H", and the N-type transfer gates 403 and 404 are brought into the selected state. At this time, in the power supply line 407, the P-type MOS transistor 412, the N-type transfer gate 403, and the bit line NT405, since the bit line NT405 is set to the logical value “L”, it is at the ground potential and the node 4
As for the potential of 09, the potential difference between the power supply potential and the ground potential is a P-type MO.
S-transistor 412 and N-type transfer gate 40
The potential is resistance-divided by the equivalent resistance of 3. Where MOS
The equivalent resistance of a transistor is represented by, for example, on-resistance in a conductive state.

The write operation will be described with reference to FIG. Line 504 in FIG. 5 is the logic inversion gates 401, 4
The power supply voltage fluctuation of the logic threshold value 02 is plotted. Here, the logic threshold value is the logic inversion gate 40.
It represents the input voltage of nodes 409 and 410 at which the outputs of 1,402 are inverted.

When the gate threshold voltage of the P-type MOS transistors 414, 412 (hereinafter referred to as "threshold voltage") is V _TP and the threshold voltage of the N-type MOS transistors 413, 411 is V _TN , the power supply voltage is Is higher than | V _TP | + V _TN , the logic threshold is the logic inverting gate 402,
The logical value of the output of 401 represents the input voltage at which it is inverted, and is normally 0.5 VDD (input voltage = output voltage) which is the middle of the power supply voltage VDD.

When the power supply voltage is lower than | V _TP | + V _TN , for example, when the voltage of the node 409 is in the middle of the power supply voltage, both the P-type MOS transistor 414 and the N-type MOS transistor 413 are non-conductive. The logical threshold value is V _TN when the node 409 changes from the logical value “L” to “H”, and the logical value “H” to “L”.
When it changes to .vertline., The voltage becomes | _VTP | lower than the power supply voltage VDD.

In FIG. 5, lines 501, 502, 5
03 shows the relationship between the power supply voltage and the voltage of the node 409 when the relative ratio of the equivalent resistances of the P-type MOS transistor 412 and the N-type transfer gate 403 is changed. The channel length of the transfer gate 403 is shortened, and the voltage of the node 409 decreases in this order. In addition, line 5
In 01, 502, and 503, the channel width of the N-type transfer gate 403 is fixed.

When the logical value "L" is written in the node 409, the potential of the node 409 needs to exist in the region below the line 504 in order for the write operation to be performed correctly. In the write operation, node 4
The potential of 09 is as shown by the line 502 in FIG. 5, for example. In line 502, the lowest operating voltage (power supply voltage) at which the write operation is performed correctly is the intersection 507 between line 502 and logic threshold 504.

From FIG. 5, it is understood that the line 503 is preferable to the line 502 as a characteristic of the N-type transfer gate 403 to be designed in order to further reduce the minimum operating voltage. The lowest operating voltage on line 503 is given at the intersection 506 with the logic threshold 504, which either shortens the channel length of the N-type transfer gate 403 or lengthens the channel length of the P-type MOS transistor 412. Correspond. In addition,
In a typical SRAM, the power supply voltage corresponding to the intersection 506 is about 1.0 volt.

Next, the read operation will be described. It is assumed that the logical value “L” is stored in the node 409 and the logical value “H” is stored in the node 410. Bit line NT40
5. Precharge both the bit line NF406 and the logic value "H".

Then, the word line N415 is set to the logical value "H".
And The N-type transfer gates 403 and 404 are in the selected state, and the charge on the bit line NT405 is discharged through the transfer gate 403 and the N-type MOS transistor 411. And bit line NT40
The stored contents are read by detecting the change in the potential of 5 with a sense amplifier (not shown).

During the read operation, when the charge of the bit line NT405 is discharged through the N-type transfer gate 403 and the N-type MOS transistor 411, the voltage of the node 409 becomes a certain finite voltage. This finite voltage changes the potential difference between the precharged bit NT405 and the ground potential into the N-type transfer gate 403 and the N-type MOS.
The voltage is resistance-divided by the equivalent resistance of the transistor 411, and this voltage is required to be lower than the logic threshold value 504 of FIG. 5 for a given power supply voltage. This is to prevent writing from occurring during the read operation.

In a read operation, line 50 of FIG.
The voltage of the node 409 becomes lower in the order of 1,502,503, which increases the channel length of the N-type transfer gate 403 in this order.

From FIG. 5, the lowest power supply voltage at which reading can be performed without writing occurs at the intersection 507 of the logical thresholds 504 and 502 on the line 502.
A line 503 is a preferable characteristic to be designed for lowering the minimum operating voltage, which increases the channel length of the N-type transfer gate 403.

[0018]

In FIG. 5, arrow 5 indicates
05, the threshold voltage V _TP of the P-type MOS transistors, when the threshold voltage V _TN of the N-type MOS transistor, the source voltage | V _TP | + V _TN and shows equal points. Below this power supply voltage, the logic inversion gate 4
In 01 and 402, P-type MOS transistors 412 and
There is no case where both 414 and the N-type MOS transistors 411 and 413 become conductive. The power supply voltage indicated by the arrow 505 in FIG. 5 is typically about 1.5 volts.

Therefore, the input transfer characteristics of the logic inverting gates 401 and 402 are as shown by the line 608 in FIG. 6 at the power supply voltage shown by the arrow 508, for example. Also,
In FIG. 6, a line 609 indicates the input / output transfer characteristics of the logic inversion gates 401 and 402 at the normal power supply voltage (> | V _TP | + V _TN ) indicated by the arrow 509.

As shown in FIG. 6, the input / output transfer characteristic of the line 608 at a low power supply voltage is different from that of the line 609. That is, when the power supply voltage is lower than | V _TP | + V _TN , the SRA is
The voltage of the M nodes 409 and 410 is the P-type M shown in FIG.
If both the OS semiconductor device and the N-type MOS semiconductor device are in the non-conductive region, the logic inversion gates 401 and 402 shown in FIG.
The operation of the latch composed of may become unstable and correct operation may not be performed.

In a conventional SRAM, when it is desired to operate at a lower voltage in a write operation and at the same time a lower voltage in a read operation, an N-type MOS forming N-type transfer gates 403 and 404 is formed.
The characteristics required for the channel length and channel width of the transistor are contradictory, which makes the design complicated,
In particular, there has been a problem that a sufficient power supply margin cannot be obtained with a low power supply voltage.

Therefore, an object of the present invention is to solve the above problems and to provide an SRAM which increases the degree of freedom in designing read and write characteristics and operates stably even with a low voltage power supply.

[0023]

In order to achieve the above object, the present invention provides two logic inverting gates having one or a plurality of inputs, and the inputs and outputs of the two logic inverting gates are mutually connected. Two storage nodes, a first switch means pair arranged between the storage node and the first bit line pair and controlled to be turned on / off by a first selection signal line, the storage node and the second A second switch means pair which is arranged between the bit line pair and is controlled to be turned on / off by the second selection signal line.

In the SRAM according to the present invention, in the write operation, a new transistor for improving only the write characteristic in addition to the read characteristic and a selecting means therefor are provided, and the read characteristic is improved in terms of read speed. It is characterized in that a transistor and a selection means therefor are provided.

[0025]

Embodiments of the present invention will be described below with reference to the drawings.

[0026]

First Embodiment FIG. 1 is a circuit diagram of an SRAM according to a first embodiment of the present invention. As shown in FIG.
The inputs and outputs of 102 are interconnected and node 109
Are connected to the bit line NT105 via the N-type transfer gate 103 and to the bit line PT119 via the P-type transfer gate 117, respectively. The node 110 connects the P-type transfer gate 11 to the bit line NF 106 via the N-type transfer gate 104.
8 are connected to the bit lines PF 120 respectively.

N-type transfer gates 103 and 104
Of the P-type transfer gates 117 and 118 are connected to the word line N115.
It is connected to 116. Logic inversion gates 101 and 10
2 is a P-type MOS transistor 112, 114 and an N-type MO
It is composed of S transistors 111 and 113.

The read operation of the SRAM according to this embodiment will be described. Bit line NT105, bit line NF1
Both 06 are precharged so as to have a logical value "H". Then, the word line N115 is set to the logical value "H", and N
The mold transfer gates 103 and 104 are brought into a selected state. The word line P116 is also set to the logical value "H" to bring the P-type transfer gates 117 and 118 into the non-selected state.

The logical value "L" is given to the node 109, and the node 11
It is assumed that the logical value “H” is stored in 0. Bit line N
The charges precharged in T105 are discharged through the N-type transfer gate 103 and the N-type MOS transistor 111. At this time, the characteristics of the N-type transfer gate 103 (likewise 104) can be designed to optimize the reading characteristics. That is, the equivalent resistance of the N-type transfer gate 103 and the N-type MOS transistor 11
Channel length so that the relative ratio of the equivalent resistance of 1 becomes large,
The channel width is designed. In this embodiment, the bit line PT119 and the bit line PF120 are not used in the read operation.

Next, the write operation will be described. It is assumed that the node 109 has a logical value “H” and the node 110 has a logical value “L”. In this case, the operation of writing the logical value “L” to the node 109 and the logical value “H” to the node 110 will be described.

Bit line NT105, bit line PT119
To the logical value "L", and the bit line NF106 and the bit line PF
120 is precharged to the logical value "H". The word line N115 is set to the logical value "H" to bring the N-type transfer gates 103 and 104 into the selected state, and then the word line P116 is brought to the logical value "L" to bring the P-type transfer gates 117 and 118 into the selected state.

The potential of the node 109 becomes a value obtained by resistance-dividing the power supply voltage by the equivalent resistance of the P-type MOS transistor 112 and the N-type transfer gate 103, and the node 11
The potential of 0 is the P-type transfer gate 118 and the N-type M.
The power supply voltage is divided by the equivalent resistance of the OS transistor 113.

In this embodiment, even in the input / output transfer characteristic 608 shown in FIG. 6, since the write operation is performed on both the nodes 109 and 110, the latch formed by the logic inversion gates 101 and 102 is different from the conventional SRAM. Works quickly and writing becomes easy. In this case, the P-type transfer gates 117 and 118 can be designed so that only the write characteristics are optimized.

As described above, the SRAM of this embodiment has an advantage that the read characteristic and the write characteristic can be designed separately.

Further, in FIG. 1, the bit line NT105
And PT119 and the bit lines NF106 and PF120 are provided separately, the parasitic capacitances added to the P-type MOS transistors 117 and 118 in the read operation are read bit lines NT105 and N105.
Since it is not added to F106, it contributes to speeding up the read operation. The bit lines NT105 and PT119 or the bit lines NF106 and PF120 may be used at the same potential, that is, connected to each other.

[0036]

Second Embodiment An SRAM according to another embodiment of the present invention will be described with reference to FIG. As shown in FIG. 2, in this embodiment, in addition to the circuit configuration of the first embodiment shown in FIG. 1, a word line R223, a bit line R224, and N-type MOS transistors 221 and 222 connected in series. And the drain of the N-type MOS transistor 222 is connected to the bit line R2.
24, and the gate is connected to the word line R223. The drain of the N-type MOS transistor 221 is N
The type MOS transistor 222 is connected to the source, the source is grounded, and the gate is connected to the node 210.

Next, the operation of the SRAM of this embodiment will be described. The write operation is the same as that of the first embodiment shown in FIG. That is, the node 209
Is a logical value “H”, the node 210 is a logical value “L”, and when the logical value “L” is written to the node 209 and the logical value “H” is written to the node 210, the bit line NT205 and the bit line PT219 are set to the logical value. "L", bit line NF206,
The bit line PF220 is precharged to the logical value "H". Next, the word line N215 is set to the logical value "H" to bring the N-type transfer gates 203 and 204 into the selected state, and then the word line P216 is brought to the logical value "L" to bring the P-type transfer gates 217 and 218 into the selected state.

In this embodiment, N-type transfer gates 203 and 204 and P-type transfer gates 217 and 2 are used.
Both 18 can have their channel lengths and widths designed to be optimized so that the write characteristics can be optimized.

Next, the read operation will be described.
It is assumed that the logical value "L" is stored in the node 209 and the logical value "H" is stored in the node 210. Therefore, the N-type MOS transistor 221 is conductive. Bit line R224
Is precharged to the logic value "H", then the word line R2
23 is set to a logical value "H".

The N-type MOS transistor 222 becomes conductive, the charge on the bit line R224 is discharged through the N-type MOS transistors 221 and 222, and the change in the potential is detected by a sense amplifier (not shown), whereby the stored contents are stored. Reading is performed.

A logical value "H" is given to the node 209, and a node 21
If the logical value “L” is stored in 0, then N
Type MOS transistor 221 is non-conductive,
Bit line R224 is precharged and word line R22
Even if 3 is set to the logical value "H", the bit line R224 is not discharged and is maintained at the precharged potential, and the detection is performed by detecting this by the sense amplifier.

Therefore, in the present embodiment, the read operation is performed via the bit line R224, and the N-type transfer gates 203 and 204 are not used for the read operation but are used only for the write operation, and therefore are shown in FIG. Compared with the first embodiment, the degree of freedom in designing the writing characteristic is increased, and the writing characteristic can be further improved.

Further, in the present embodiment, the read characteristic can be designed completely independently of the write characteristic, which is advantageous in terms of read speed.

In this embodiment also, the bit line NT
205 and PT219, and bit lines NF206 and PF2
20 can also be connected and used.

[0045]

[Third Embodiment] Next, still another embodiment of the present invention will be described with reference to FIG. The configuration of this embodiment is similar to that of the first embodiment shown in FIG. 1 except that the P-type transfer gates 117 and 118 are replaced by the N-type transfer gate 31.
It was changed to 7,318.

In this embodiment, the read operation is performed using the bit line NT305 and the bit line NF306, and the read operation is the same as that of the first embodiment.

Next, the write operation in this embodiment will be described. Node 309 has logical value “H”, node 31
When 0 is the logical value “L”, the logical value “L” is written in the node 309 and the logical value “H” is written in the node 310.
The bit line PT319 is set to the logical value "L" and the bit line PF3 is set.
20 is precharged to the logical value "H". Next, the word line P316 is set to the logical value "H" to bring the N-type transfer gates 317 and 318 into the selected state.

In this embodiment, since reading and writing are performed via transfer gates and bit lines different from each other, the N-type transfer gate 303,
304 can be optimized only for read characteristics, and N-type transfer gates 317 and 318 are
It can be optimized only for the writing characteristics. Therefore, the N-type transfer gates 303 and 304 and the N-type transfer gates 317 and 318 have channel lengths of
The channel width is different.

SR using the memory cell shown in this embodiment
If an AM memory array is configured, the bit line PT31
9. A write circuit (not shown) on the bit line PF320
Only connected, no read circuit (not shown),
Further, only the read circuit is connected to the bit line NT305 and the bit line NF306, and no write circuit is provided.

As described above, the present invention provides an SRAM.
Since the characteristics of the read operation and the write operation can be designed independently of each other, there is an advantage that an optimum design can be made in each.

As described in detail in the conventional example, the SRAM
The design of the read characteristics and the write characteristics of the two are contradictory. In particular, in order to operate at a power supply voltage of about 1 volt, the threshold value of the MOS transistor is set to the temperature characteristic of the subthreshold characteristic (especially increase of leak current at high temperature) and the threshold value of the MOS transistor. Considering the temperature characteristics of (increase of threshold value especially at low temperature), the median value is ±
It is about 0.55 volts. In addition,
0.1 volt and the low temperature of the above-mentioned threshold (about -20
The maximum value of the threshold value of the MOS transistor becomes 0.75 volt by adding +0.1 volt of increase in (° C.). Since the operating voltage required on the market is 0.9 V, the difference is 0.15 V.

In the prior art, it is attempted to optimize the read characteristic and the write characteristic with the same transistor within the range of 0.15 V, and the stable operation is achieved even with a slight drop in the power supply voltage. It is actually quite difficult to design so that it is possible. On the contrary,
According to the present invention, the read characteristic and the write characteristic can be independently optimized, and the operation of the SRAM under a low voltage is improved.

Although the present invention has been described with reference to various embodiments, the present invention is not limited to the embodiments described above, but includes various embodiments according to the principle of the present invention. For example, in the SRAM of the above embodiment, the logic inverting gate is composed of a complementary MOS inverter circuit, but it goes without saying that the present invention includes a high resistance load type memory cell.

[0054]

As described above, according to the present invention, a transfer gate arranged between a bit line pair and a node is further provided in the structure of the conventional SRAM, and the characteristics of the read operation and the write operation of the SRAM are designed independently. By doing so, it is possible to design optimally for read operation and write operation, and to realize SR under low voltage.
It significantly improves the operation of the AM.

The effects of the present invention will be described in more detail below. The design of the read characteristic and the write characteristic of the SRAM are contradictory to each other, and in order to operate at a power supply voltage of about 1 volt, the threshold value of the MOS transistor depends on the temperature characteristic of the subthreshold characteristic (especially leakage at high temperature). In consideration of the increase in current) and the temperature characteristic of the threshold value of the MOS transistor (in particular, increase in threshold value at low temperature), the median value is about ± 0.55 V, and the manufacturing variation is ± 0.1 Volts and low temperature (about -2
The maximum value of the threshold value of the MOS transistor is 0.75 by adding +0.1 volt of the increase of the threshold value at 0 ° C).
It becomes a bolt.

Since the operating voltage required on the market is 0.9 volt, the difference is 0.15 volt. Under the prior art, in the range of 0.15 V, it is attempted to optimize the read characteristic and the write characteristic with the same transistor, and further, it is possible to operate stably even with a slight decrease in the power supply voltage. It is actually quite difficult to design. The present invention seeks to optimize both the read characteristic and the write characteristic with the same transistor in such a small design margin range, and further, is designed so that stable operation is possible even with a slight decrease in the power supply voltage. This makes it possible to improve the operating characteristics of the SRAM.

Further, according to the present invention, writing is simultaneously performed to the two memory nodes in the selected memory cell, and the writing operation of the SRAM is speeded up. The present invention further speeds up the writing operation by writing preferably via two bit lines and a transfer gate.

Further, according to the present invention, since the bit line used for the read operation is different from the bit line used for the write operation, the increase of the parasitic capacitance added to the bit line is suppressed and the read operation is performed. It has realized the speedup of.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a configuration of a first exemplary embodiment of the present invention.

FIG. 2 is a circuit diagram showing a configuration of a second exemplary embodiment of the present invention.

FIG. 3 is a circuit diagram showing a configuration of a third exemplary embodiment of the present invention.

FIG. 4 is a circuit diagram showing a configuration of a conventional SRAM.

FIG. 5 is a diagram showing a power supply voltage and a voltage characteristic of a configuration of a conventional SRAM.

FIG. 6 is a DC transfer characteristic diagram of a logic inverting gate.

[Explanation of symbols]

101, 102, 201, 202 Logic inversion gate 103, 104, 203, 204 N-type transfer gate 105, 105 Bit line NT 106, 206 Bit line NF 107, 207 Power supply line 108, 208 Ground line 109, 110, 209, 210 Nodes 111, 113, 211, 213 N-type MOS transistors 112, 114, 212, 214 P-type MOS transistors 115, 215 Word lines N 116, 216 Word lines P 117, 118, 217, 218 P-type transfer gates 119, 219 bits Line PT 120,220 Bit line PF 221,222 N-type MOS transistor

Continuation of the front page (51) Int.Cl. ⁶ Identification code Office reference number FI technical display location H01L 27/11 7210-4M H01L 27/10 381

Claims (10)

[Claims] 1. A logic inversion gate having one or a plurality of inputs, two storage nodes formed by mutually connecting the inputs and outputs of the two logic inversion gates, the storage node and a first bit. A first switch means pair which is arranged between the line pair and whose ON / OFF is controlled by the first selection signal line;
A second bit line arranged between the storage node and the second bit line pair;
And a second switch means pair whose ON / OFF is controlled by the selection signal line of. 2. The static random access memory according to claim 1, wherein the first pair of switch means and the second pair of switch means are MOS type semiconductor devices. 3. The static random access memory according to claim 1, wherein said switch means has one end connected to said storage node and the other end connected to the same bit line. 4. The static random access memory according to claim 1, wherein said first switch means pair and said second switch means pair are MOS type semiconductor devices of different conductivity types. 5. The pair of first switch means and the pair of second switch means are MOS semiconductor devices of the same conductivity type, and the electrical characteristics of the pair of first switch means and the second switch means. The static random access memory according to claim 1, which has electrical characteristics different from each other. 6. An MO forming the first pair of switch means.
6. The static random access memory according to claim 5, wherein the channel length and / or the channel width of the S-type semiconductor device are different from the channel length and / or the channel width of the MOS-type semiconductor device forming the second switch means pair. 7. A third switch means whose ON / OFF is determined by receiving a stored value of one storage node, and an ON / OFF state of the third switch means and the third switch means is output to the outside. 4. The static random access memory according to claim 1, further comprising a fourth switch means which is arranged between the output line for output and a switch for controlling ON / OFF by a third selection signal line. 8. The first bit line pair and the first switch means pair are used for reading, and the first and second bit line pairs and the first and second switch means pairs are used for writing. The static random access memory according to claim 1, wherein 9. The first bit line pair and the first switch means pair are used at the time of reading, and the second bit line pair and the second switch means pair are used at the time of writing. Item 1. A static random access memory according to item 1. 10. The static random access memory according to claim 1, wherein said logic inversion gate is composed of a CMOS inverter circuit or a high resistance load type inverter circuit.