JPH02265097A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To improve the operation margin and the information holding characteristic by setting an access transistor whose threshold value is lower than that of a driver transistor (TR) to a lower impedance at the time of write than at the time of read-out. CONSTITUTION:A static RAM is formed by a memory cell 10 of a matrix array, the cell 10 has driver TRs 1, 2 of n-TR, and the cell 10 is selected by access TRs 3, 4 of nTR driven by a word line driving circuit 13. A threshold value of these TRs 3, 4 is lower than a threshold value of the TRs 1, 2 and a write voltage can be made high. On the other hand, when the TRs 3, 4 are driven through a word line so that the readout time becomes a higher impedance than the write time, a mutual conductance ratio betaR of conductance of Trs 1, 2/conductance of TRs 3, 4 becomes large and an operation margin becomes high, and the operation margin and the information holding characteristic are enhanced.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an SRAM (static RAM) type semiconductor memory device in which a memory cell has a pair of driver transistors and a pair of access transistors having seven word lines as gates.

[Summary of the invention]

The present invention provides a semiconductor memory device in which a memory cell includes a pair of driver transistors and a pair of access transistors, in which the threshold voltage of the driver (ransistor) is made higher than the threshold voltage of the access transistor, and the impedance of the access transistor is changed during writing and reading. By making it lower, the information retention characteristics of the memory cell are improved.

[Conventional technology]

The SRAM has memory cells arranged in a matrix, and transistors are arranged in each memory cell to form a flip-flop.

FIG. 5 shows the main part of a typical SRAM, and is an example of a load resistance type memory cell. Each memory cell has a pair of driver transistors 51.52 whose sources are grounded and whose gates and drains are connected to each other, each of which has a load resistor 53.54 connected to the power supply voltage Vcc. Ru. Furthermore, access transistors 55 and 56 are connected to each bit line 57 and 58, respectively, to each drain. The gates of the access transistors 55 and 56 are connected to the word line 59, and the gates of the access transistors 55 and 56 are connected to a pair of bit lines 57 and 5.
A bit line load 60.61 is connected to the power supply voltage Vcc at the end of 8.
It is established between. Write and read operations are
The selected word line 59 goes high, turning on the access transistor 55.56, and the storage of information is done by keeping one of the nodes 62,63 high and the other low. be exposed.

[Problems to be Solved by the Invention] In such an SRAM, the specifications of the standby current are kept low, so the resistance values of the load resistors 53 and 54 are set high. Therefore, a high write potential (
In order to store information, it is necessary to maintain the potential of one side of F'62.63), and in order to ensure the operating margin of the memory cell, the junction leakage current and the driver transistor voltage threshold current are reduced. things are being done.

A known method for reducing this subthreshold current is to increase the threshold voltage V of the driver transistors 51 and 52. However, normally, the driver transistor 5152 is connected to the access transistors 55 and 56.
The driver transistor 5 is formed from the same process as the driver transistor 5.
When the threshold voltage of 1.52 is increased, the threshold voltage of the access transistor also increases, and the write potential given by power supply voltage Vcc - threshold voltage Vth (access transistor) also decreases. For this,
It has become difficult to obtain a high operating margin for memory cells.

SUMMARY OF THE INVENTION In view of these two technical problems, it is an object of the present invention to provide a semiconductor memory device with excellent information retention characteristics using memory cells with a high operating margin.

[Failure to solve the problem]

In order to achieve the above object, a semiconductor memory device of the present invention has memory cells arranged in a matrix, for example, and each memory cell includes a pair of driver transistors;
A pair of access transistors are formed which are selected by the word line. Here, the gates and drains of the pair of driver transistors are connected to each other to form a flip-flop. Each access transistor is connected between a bit line provided substantially perpendicular to the word line and the drain of the driver transistor.

In the semiconductor memory device of the present invention, the threshold voltage of the driver transistor is set higher than the threshold voltage of the access transistor, and the word line is driven such that the access transistor has a lower impedance during writing than during reading. It is characterized by being

As an example of a method for driving this word line, the power supply voltage Vcc may be used during writing, and an intermediate voltage obtained by subtracting a voltage approximately equal to the threshold voltage Vth from the power supply voltage VCC may be used during reading.

[Effect]

By making the threshold voltage of the driver transistor higher than the threshold voltage of the access transistor, the write voltage can be increased. However, when the threshold voltage of the access transistor is low, when a normal word line voltage (for example, power supply voltage Vcc) is applied to the gate of the access transistor when reading data, the current value of the access transistor increases and the memory cell The β7 ratio (transconductance ratio - conductance of driver transistor/conductance of access transistor) decreases. Therefore, in the semiconductor memory device of the present invention, the impedance of the access transistor when reading the potential of the word line is higher than when writing. Thereby, it is possible to prevent the β8 ratio from decreasing, and it is possible to secure the operating margin of the memory cell.

〔Example〕 Preferred embodiments of the present invention will be described with reference to the drawings.

This example is an SRAM having memory cells in a matrix.
It is. Figure 1 shows the circuit configuration.

The memory cells 10 are arranged in a matrix, and each memory cell 10 has driver transistors 1 and 2 consisting of a pair of nMO3) transistors. These driver transistors 1 and 2 have their sources supplied with ground voltage GND, and each gate connected to the drain of the other driver transistor. One end of a high-resistance load resistor 56 is connected to each drain, and each of the load resistors 5, 6
A power supply voltage Vcc is supplied to the other end. These load resistors 5.6 and driver transistors 1 and 2 form a pair of inverters whose inputs and outputs are connected to each other, thereby forming a flip-flop. The threshold voltage of the driver transistors 1 and 2 is set to a value that suppresses the threshold current to a negligible level in practical use, for example, 0.8 to 0.
It is set to about 9V high.

Each memory cell 10 is provided with a respective access transistor 3.4 between the respective drain of the respective driver transistor 1, 2 and the respective bit line 11, 12. These access transistors 3 and 4 have their gates connected to word lines x, .
χ, 43. ..., and the word line X i+
On/off is controlled from the potential of X i+1+ . Word lines Xi, Xi, I, . . . select memory cells in the − row, and the selection operation is performed by the word line drive circuit 13. The access transistors 3 and 4 are nMO
3) It consists of a transistor, and in particular, its threshold voltage is set to be low. This is to obtain a high write potential, and the threshold voltage Vth is set to be low, for example, about 0.5 to 0.6V.

This threshold voltage can be adjusted by adding an ion implantation step.

The word lines X, , Xi. 1. The bit lines 11 and 12, which are provided substantially perpendicular to the bit lines 11 and 12, are used as a pair to read or write information in the memory cell via the access transistors 3 and 4. Each bit line 11.1
A bit line load 14 consisting of 9 MO3) transistors is formed at the terminal end of the bit line 2.

A power supply voltage cc is supplied to the source side of the bit line load 14. Further, although not shown, column selection transistors for selecting a bit line pair are formed in these bit lines 11 and 12, and a common data line is formed continuously from the column selection transistor, and the common data A sense amplifier, a write circuit, etc. are connected to the line.

In the SRAM of this embodiment having such a circuit configuration, the access transistor 34 is set to the intermediate potential ■ during reading.
4, the impedance is higher than when it is selected using the power supply voltage Vcc. This increases the operating margin of the memory cell, as described below.

FIG. 2 shows an example of a word line drive circuit for applying such an intermediate potential ``H''. This word line drive circuit generates signals with different levels during writing and reading based on the timing of the original word line selection signal WL.

This word line drive circuit has a path including a PMOS transistor 21 and a path including PMOS transistors 22 and 23 so as to configure two current paths that are switched in response to a write enable signal WE. The 9MO3) transistor 21 constituting one path has its source supplied with the power supply voltage Vcc, and its gate supplied with a signal obtained by inverting the write enable signal WE from the inverter 24. The drain of this pMO3l- transistor 21 is connected to the source of a 9MO3) transistor 25 constituting an inverter.

For the other path, 9 is connected to the power supply voltage Vcc.
MO3) The transistor 22 functions as a diode, and its 9MO3) pMO is connected in series to the transistor 22.
A write enable signal WE is supplied to the gate of the 3+- range disk 23. The drain of this 9MO3) transistor 23 is connected to the source of a pMO3+- transistor 25 constituting an inharter.

The pMOS transistor 25 and the nMOS transistor 26 constitute an inverter. The original word line selection signal WL is supplied to the commonly connected gates,
A word line selection signal WL whose potential changes during reading and writing is output from the commonly connected drains.

FIG. 3 is a waveform diagram for explaining the operation of the circuit shown in FIG. The pMOS transistor to which the signal is supplied via is turned on. Then, the potential of the source of the pMOS transistor 25 rises to the power supply voltage Vcc, and the word line selection signal WL is set to the ground voltage GND in accordance with the original word line selection signal WL.
and the power supply voltage Vcc.

On the other hand, during reading, the write enable full signal W
E is set to low level (#GND). Then, pMO3
The +- transistor 21 is turned off and the pMO3l- transistor 23 is turned on. This changes the current path from that during writing, and current flows to the source of the pMO3+- transistor 25 via the pMOS transistors 22 and 23. In this case, pMO3) transistor 22 is gate 1---
Since the transistors 1147 and 1147 are connected, it functions as a diode, and the potential at the source of the pMO3+ transistor 23 decreases by an amount equal to its threshold voltage. Therefore, pMO3+
- The source potential of the transistor 25 is also an intermediate potential (i) obtained by subtracting the threshold voltage Vth from the power supply voltage (cc), and the word line selection signal WL is at an intermediate potential (i) between the ground voltage GND and the ground voltage GND. It will swing between.

Using such a word line drive circuit, the word lines X, ,
, , , , . . . , when writing, the potential of the selected word line becomes the power supply voltage ■cc, and the impedance of the access transistor 3.4 having a threshold voltage Vvh set to a low value increases. is low. Therefore, the write potential, which is the gate-drain potential of the driver transistors 1 and 2, increases.

At the time of reading, the potential of the selected word line is set to the intermediate potential ■ by the word line drive circuit 13 mentioned above. It is said that Therefore, the impedance of access transistor 3.4 is higher than that during writing.

As a result, during reading, the voltage drop due to the access transistor 34 becomes large, and the boosted bit line 11
．． Due to the influence of 12, data 1 to 2 of driver transistors 1 and 2
This prevents data from being reversed or destroyed due to potential changes. That is, the β8 ratio becomes larger, the operating margin becomes larger, and the soft error resistance becomes stronger.

As mentioned above, in the SRAM of this embodiment, the threshold voltage of the access transistor 34 is
is low, and the threshold voltage of driver transistor 1.2 ■t
Since h is high, the write voltage can be increased. Further, the high threshold voltage V1. of the driver transistors 1 and 2. The subthreshold current is also reduced from h, and low standby current can also be achieved.

Figure 4 shows conventional S
FIG. 3 is a diagram comparing the operating margins of a RAM memory cell and a memory cell according to this embodiment.

In this figure, the broken line T indicates a conventional SRAM as a comparative example.
The potentials V, , V, and solid line U of the cross-coupled contact portion in the memory cell of FIG.

In the broken line T of the comparative example, since the threshold voltage of the access transistor is high, the write potential, that is, the potential of the cross-coupled contact portion V, , V.

is lower overall, Δ in the figure. The operating margin of the memory cell is also small. On the other hand, in this embodiment, as shown by the solid line U, the threshold voltage of the access transistor 34 is set small, so the write voltage becomes high, and the overall potential V, Vo of the cross-coupled contact portion increases. has a large amplitude, and the operating margin of the memory cell (not indicated by Δ1 in the figure) also becomes large.

At the time of reading, the potential of the selected word line is set to the intermediate potential VM by the word line drive circuit 13 described above. Therefore, the impedance of the access transistors 3 and 4 becomes higher than that during writing, and the βR ratio increases, resulting in a high operating margin of the memory cell.

[Effects of the Invention] In the semiconductor memory device of the present invention, the threshold voltage of the access transistor is lower than that of the driver 1 to the transistor. Therefore, the write voltage can be increased. Further, during reading, the access transistor has a higher impedance than during writing, and the β8 ratio becomes larger. Therefore, the write voltage becomes high and β
, ratio becomes large, the operating margin of the memory cell becomes sufficiently high, and low standby current and soft error resistance are also improved.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of a main part showing the circuit configuration of an example of a semiconductor memory device of the present invention, FIG. 2 is a circuit diagram of an example of a word line driving circuit of the example, and FIG. 3 is a circuit diagram of an example of a word line driving circuit of the example. A waveform diagram for explaining the operation of the circuit, and FIG. 4 shows a part of each cross-coupled contact 1 for explaining the difference in operating margin between each memory cell of the semiconductor memory device of the present invention and the conventional semiconductor memory device. FIG. 5 is a circuit diagram of the main part of a general conventional SRAM. 1.2... Driver l-run raster 3.4... Access transistor 5.6... Load resistor 10... Memory cell 11.12... Bit line 13... Word line drive circuit patent application Person Sony Corporation Patent Attorney Akira Koike (and 2 others)

Claims (1)

[Scope of Claims] A semiconductor memory device comprising a memory cell having a pair of access transistors selected by a word line and a pair of driver transistors, wherein a threshold voltage of the driver transistor is a threshold voltage of the access transistor. , and the word line is driven such that the access transistor has a lower impedance during writing than during reading.