JP2893708B2 - Semiconductor memory device - Google Patents

Description

The present invention relates to an SRAM (static RAM) type semiconductor memory device in which a memory cell has a pair of driver transistors and a pair of access transistors having a word line as a gate.

SUMMARY OF THE INVENTION The present invention provides a semiconductor memory device in which a memory cell has a pair of driver transistors and a pair of access transistors, the threshold voltage of the driver transistor being higher than the threshold voltage of the access transistor, and the voltage applied to the word line. Is set to a lower voltage at the time of reading than at the time of writing, thereby improving the information retention characteristics of the memory cell.

[Conventional technology]

The SRAM has memory cells arranged in a matrix, and a transistor is arranged in each memory cell so as to form a flip-flop.

FIG. 5 shows a main part of a typical SRAM, which is an example of a load resistance type memory cell. Each memory cell has a pair of driver transistors 51, 52 whose sources are grounded and whose gates and drains are connected to each other, and each drain of which is connected to a load resistor 53, 54 between the power supply voltage Vcc. You. further,
Each drain has an access transistor 55, 56
Are connected to the respective bit lines 57 and 58. The gates of the access transistors 55 and 56 are connected to the word line 59,
Bit line loads 60, 61 are provided at the ends of the pair of bit lines 57, 58 between the power supply voltage Vcc. The write or read operation is performed with the selected word line 59 at a high level and the access transistors 55 and 56 turned on, and information is stored at one of the nodes 62 and 63 at a high level and the other at a low level. It is held on a level.

[Problems to be solved by the invention]

In such an SRAM, the resistance values of the load resistors 53 and 54 are set high because the specification of the standby current is kept small. Therefore, a high write potential (node
It is necessary to maintain information (e.g., one of the potentials 62 and 63) in order to accumulate information, and it is necessary to reduce the junction leakage current and the sub-threshold current of the driver transistor in order to secure the operation margin of the memory cell. Have been done.

As a method for reducing the subthreshold current, there is known a method for increasing the threshold voltage _Vth of the driver transistors 51 and 52. However, usually, the driver transistors 51 and 52 are formed from the same process as the access transistors 55 and 56, when you have a high threshold voltage V _th of the driver transistor 51 and 52, it is also increased the threshold voltage V _th of access transistors simultaneously, Power supply voltage Vcc-threshold voltage _Vth
The write potential given by the (access transistor) also decreases. For this reason, it is difficult to obtain a high operation margin of the memory cell.

In view of the above technical problems, an object of the present invention is to provide a semiconductor memory device having a high operation margin and excellent information retention characteristics.

[Means for solving the problem]

In order to achieve the above object, a semiconductor memory device of the present invention has, for example, memory cells arranged in a matrix, each memory cell having a pair of driver transistors and a pair of access lines selected by a word line. A transistor is formed. Here, the gate and the drain of the pair of driver transistors are connected to each other to form a flip-flop. Each access transistor is connected between a bit line provided substantially orthogonal to a word line and a drain of the driver transistor.

In the semiconductor memory device of the present invention, the threshold voltage of the driver transistor is set higher than the threshold voltage of the access transistor, and the voltage applied to the word line is set to be lower at the time of reading than at the time of writing. It is characterized by. As an example of the word line driving method, the power supply voltage Vcc can be used during writing, and the intermediate voltage obtained by subtracting a voltage of about the threshold voltage _Vth from the power supply voltage Vcc during reading can be used.

[Operation] By setting the threshold voltage of the driver transistor higher than the threshold voltage of the access transistor, the write voltage can be increased. However, when the threshold voltage of the access transistor is low, when a normal word line voltage (for example, power supply voltage Vcc) is applied to the gate of the access transistor during data reading, the current value of the access transistor increases, and ( _R) (transconductance ratio = conductance of driver transistor / conductance of access transistor) indicating the operation margin of (1) decreases. Therefore, in the semiconductor memory device of the present invention, the potential of the word line is set such that the access transistor at the time of reading has a higher impedance than at the time of writing. Thus, it is possible to prevent a decrease in beta _R ratio, it is possible to secure the operation margin of the memory cell.

〔Example〕

Preferred embodiments of the present invention will be described with reference to the drawings.

This embodiment is an SRAM having matrix-shaped memory cells. FIG. 1 shows the circuit configuration. Its memory cell 10
Are arranged in a matrix, and each memory cell 10 is a pair of
It has driver transistors 1 and 2 composed of nMOS transistors. Each of the driver transistors 1 and 2 has a source supplied with the ground voltage GND and a gate connected to the drain of another driver transistor. One end of each of the high-resistance load resistors 5 and 6 is connected to each drain, and the other end of each of the load resistors 5 and 6 is supplied with the power supply voltage Vcc. The load resistors 5 and 6 and the driver transistors 1 and 2 constitute a pair of inverters connected to each other for input and output, thereby constituting a flip-flop. This driver transistor
The threshold voltages _{Vth of} 1 and 2 are set to values that suppress the subthreshold current to a practically negligible value, for example, 0.8 to 0.9.
Set to about V higher.

In each memory cell 10, each access transistor 3, 4 is provided between each drain of each driver transistor 1, 2 and each bit line 11, 12. The access transistors 3 and 4 has a gate word line X _i, X _{i + 1,} is connected to ..., word line X _i, X _{i + 1,} is ... on and off from the potential is controlled. The word lines X _i , X _{i + 1} ,... Select one row of memory cells, and the selection operation is performed by the word line drive circuit 13. Each of the access transistors 3 and 4 is formed of an nMOS transistor, and in particular, its threshold voltage _Vth is set lower. This is to obtain a high writing potential, and the threshold voltage _Vth is set lower, for example, by about 0.5 to 0.6 V. The adjustment of the threshold voltage _Vth can be performed by adding an ion implantation step.

Bit lines 11, 12 provided substantially orthogonal to the word lines X _i , X _{i + 1} ,... Are paired to read or write information of a memory cell via the access transistors 3, 4. Used. A bit line load 14 composed of a pMOS transistor is formed at the end of each of the bit lines 11 and 12. The power supply voltage Vcc is supplied to the source side of the bit line load 14. Further, although not shown, these bit lines 11, 12
, A column selection transistor for selecting a bit line pair is formed, a common data line is formed continuously with the column selection transistor, and a sense amplifier, a write circuit, and the like are connected to the common data line.

SRAM of the present embodiment having such a circuit configuration, therefore the read time of the access transistors 3 and 4 is selected using the intermediate voltage V _M, high impedance as compared with a case that is selected by the power supply voltage Vcc Become. Thereby, the operation margin of the memory cell is increased as described below.

Figure 2 is an example of a word line drive circuit for providing such an intermediate potential V _M. This word line drive circuit generates signals having different levels at the time of writing and at the time of reading based on the timing of the original word line selection signal ▲ ▼. This word line drive circuit uses the write enable signal WE
The path of the pMOS transistor 21 and the pMOS transistor
There is a route consisting of 22,23. PMOS that constitutes one path
The transistor 21 has a source supplied with the power supply voltage Vcc,
The inverted signal of the write enable signal WE is the inverter
From 24 is supplied to its gate. This pMOS transistor
The drain of 21 is connected to the source of a pMOS transistor 25 constituting the inverter. On the other path, the pMOS transistor 22 connected to the power supply voltage Vcc functions as a diode, and the write enable signal WE is supplied to the gate of the pMOS transistor 23 connected in series to the pMOS transistor 22. The drain of the pMOS transistor 23 is connected to the source of the pMOS transistor 25 forming the inverter.

Then, the pMOS transistor 25 and the nMOS transistor 26 constitute an inverter. An original word line selection signal ▼ is supplied to the commonly connected gates, and a word line selection signal WL whose potential changes between reading and writing is output from the commonly connected drains.

FIG. 3 is a waveform diagram for explaining the operation of the circuit of FIG. 2. First, at the time of writing, the write enable signal WE is set to a high level (≒ Vcc), the pMOS transistor 23 is turned off, and the inverter 24 is turned off. Signal is supplied via
The pMOS transistor turns on. Then, the potential of the source of the pMOS transistor 25 rises to the power supply voltage Vcc, and the word line selection signal WL swings between the ground voltage GND and the power supply voltage Vcc according to the original word line selection signal ▲.

On the other hand, at the time of reading, the write enable signal
WE is low (低 GND). Then, the pMOS transistor 21 is turned off and the pMOS transistor 23 is turned on. When writing, the current path changes and the pMOS
A current flows to the source of the pMOS transistor 25 via the transistors 22 and 23. In this case, since the gate and drain are connected to each other, the pMOS transistor 22 functions as a diode, and the potential of the source of the pMOS transistor 23 decreases by the threshold voltage _Vth . Therefore, the intermediate potential V _M, and the word line selection signal WL to the source potential is also obtained by subtracting the threshold voltage V _th from the power supply voltage Vcc of the pMOS transistor 25 is to swing between the ground voltage GND and the intermediate voltage V _M.

Using such a word line driving circuit, word lines X _i , X
_{When i + 1} ... are selected, at the time of writing, the potential of the selected word line becomes the power supply voltage Vcc, and the access transistors 3 and 4 having the lower threshold voltage _Vth are set.
Has low impedance. Therefore, the write potential, which is the potential between the gate and drain of the driver transistors 1 and 2, rises.

At the time of reading, the word line driving circuit 13 described above, the potential of the word line according to the selection is an intermediate potential V _M. Therefore, the access transistor 3,
The impedance of 4 is higher than that at the time of writing. As a result, at the time of reading, the voltage drop due to the access transistors 3 and 4 increases, and the driver transistors 1 and 2 are affected by the boosted bit lines 11 and 12.
Is prevented from being inverted or destroyed. That is, the β _R ratio increases, the operation margin increases, and the soft error resistance increases.

As described above, in the SRAM of the present embodiment, at the time of writing, the threshold voltage V _th of access transistors 3 and 4 is low, due to the high threshold voltage V _th of the driver transistors 1 and 2, increasing the write voltage be able to. Also,
The subthreshold current is also reduced from the high threshold voltage _Vth of the driver transistors 1 and 2, and a low standby current and the like can be realized.

FIG. 4 shows conventional inverters each operating an inverter.
FIG. 9 is a diagram comparing the operation margins of the SRAM memory cell and the memory cell according to the present embodiment. In this figure, the dashed line T
The potential V _P of the cross-coupled contact portion in the memory cell of the conventional SRAM as a comparative example, V _Q, the solid line U is potential V _P of the cross-coupled contact portion in the memory cell of the SRAM according to the present embodiment, V _Q Are respectively shown.

In the dashed line T of the comparative example, since the threshold voltage V _th of the access transistor is high, the write potential, that is, the potentials V _P and V _{Q of the} cross-coupled contact portion are reduced as a whole,
Operation margin of the memory cell shown in the figure delta ₀ is small. On the other hand, in the present embodiment, as shown by the solid line U, since the threshold voltage V _th of the access transistors 3 and 4 is set small, the write voltage increases, and the potentials V _P and V _{Q of the} cross-coupled contact portion increase. There have large amplitude generally, the greater the operating margin of the memory cell shown in the figure delta _1.

At the time of reading, the word line driving circuit 13 described above, the potential of the word line according to the selection is an intermediate potential V _M. Therefore, the access transistor 3,
4 impedance, compared to the time of writing becomes high impedance, beta _R ratio is increased, so that high operating margin of the memory cell is obtained.

〔The invention's effect〕

In the semiconductor memory device of the present invention, the threshold voltage of the access transistor is set lower than that of the driver transistor. Therefore, the write voltage can be increased. Further, at the time of reading, the access transistor is a high impedance than the time of writing, beta _R ratio increases. Thus, the higher the write voltage, and β from _{the R} ratio increases, the operation margin of the memory cell becomes sufficiently high, the low standby current or soft error resistance is improved.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a main part circuit diagram showing an example of a circuit configuration of a semiconductor memory device of the present invention, FIG. 2 is a circuit diagram of an example of a word line drive circuit of the example, and FIG. FIG. 4 is a waveform diagram for explaining the operation of the word line drive circuit, and FIG. 4 is a cross-coupled diagram for explaining a difference in operation margin between each memory cell of the semiconductor memory device of the present invention and a conventional semiconductor memory device. FIG. 5 is a characteristic diagram showing a potential at a contact portion, and FIG. 5 is a main part circuit diagram of a general conventional SRAM. 1,2 ... Driver transistor 3,4 ... Access transistor 5,6 ... Load resistance 10 ... Memory cell 11,12 ... Bit line 13 ... Word line drive circuit

Claims (1)

(57) [Claims] In a semiconductor memory device having a memory cell having a pair of access transistors selected by a word line and a pair of driver transistors, a threshold voltage of the driver transistor is higher than a threshold voltage of the access transistor. Wherein the voltage applied to the word line is lower during reading than during writing.