CN1956098A - Semiconductor storage device - Google Patents

Abstract

A level shift element adjusting a voltage level at the time of selection of a word line according to fluctuations in threshold voltage of a memory cell transistor is arranged for each word line. This level shift element lowers a driver power supply voltage, and transmits the level-shifted voltage onto a selected word line. The level shift element can be replaced with a pull-down element for pulling down the word line voltage according to the threshold voltage level of the memory cell transistor. In either case, the selected word line voltage level can be adjusted according to the fluctuations in threshold voltage of the memory cell transistor without using another power supply system. Thus, the power supply circuitry is not complicated, and it is possible to achieve a semiconductor memory device that can stably read and write data even with a low power supply voltage.

Description

Semiconductor storage

Technical field

The present invention relates to semiconductor storage, even particularly under the low voltage operating condition, also can stably carry out the structure of the static semiconductor memory device that writes and read of data.

Background technology

Follow the miniaturization Progress in technique, after the transistor unit miniaturization, from the reliability of element and the viewpoint of power consumption, need be corresponding to the voltage scaling of miniaturization.But, being accompanied by this miniaturization, the influence of Fabrication parameter change becomes big, and (insulated-gate type field effect transistor: the discrete change of threshold voltage MOS transistor) is big, and its operation margin reduces for the transistor of formation memory cell.Consequently, though in semiconductor storage, under low supply voltage, stably carry out data write and read also very difficult.

Even under above-mentioned low supply voltage, also proposed stably to carry out the various schemes that write/read as purpose of data.

At document 1 (K.Zhanget al., " A3-GHz 70Mb SRAM in 65nm CMOS Technologywith Integrated Column Based Dynamic Power Supply; " ISSCC 2005, Digest ofTechnical Papers, Feb.2005 has illustrated in pp.474-475): the structure that the level of reading and write fashionable memory cell supply voltage by switch data improves static noise margin SNM and writes tolerance limit.

In the document 1, with the memory cell unit of classifying as control store unit supply voltage, write fashionable in data, to select the memory cell supply voltage of row to be set at low-voltage VCC-LO, high equally a little voltage VCC-HI when the unit supply voltage of non-selection row is set at and reads, improve the static noise margin when reading thus, and guarantee to write tolerance limit.

Document 2 (M.Yamaoka et al., " Low-Power Embedded SRAM Modules withExpanded Margins for writing; " ISSCC 2005, Digest of Technical Papers, Feb.2005, pp.480-481) be illustrated in data and write the fashionable memory cell power lead of row of will selecting and be set at quick condition, make the memory cell power lead maintain the structure of prescribed voltage level equally for residual non-selection row with when reading.In this non-patent literature 2, use illusory (dummy) bit line in addition, according to this dummy current potential, generate word line deactivation timing signal WOFF, as inactive state, and will to select word line to drive be nonselection mode with word line driver.

In the structure shown in the document 2, in addition, discharge transistor and word line transistors that dividing on each word line is arranged is set at ground voltage level.The transistor of this discharge usefulness is kept off-state when stand-by state, in the time will selecting word line to drive to inactive state, with its bigger current driving capability the word line high-speed driving is arrived nonselection mode.After word line is driven into nonselection mode, the power supply of this word line driver of sever supply, corresponding therewith, discharge becomes the L level with transistorized grid potential corresponding to drive electric source voltage, and discharge becomes off state with transistor.

In addition, prior art document 1 (spy opens the 2005-038557 communique) illustrates: in word line driver, use level-conversion circuit, with the structure of selecting word line to drive with the amplitude different with the memory cell supply voltage.Select the current potential of word line by change, thereby even when the threshold voltage dispersion of memory cell transistor, also can realize writing and reading the improvement of tolerance limit.

In the structure shown in the document 1, come the level of switching controls memory cell supply voltage with the memory cell unit of classifying as.Therefore,, need two kinds of voltages, cause power circuit to become complicated in order to realize dual power source structure as the memory cell supply voltage.

In addition, though switchable memory unit supply voltage, its switching voltage levels is the set potential of power circuit generation internally.Therefore, the threshold voltage of memory cell transistor, even produce under the discrete situation in change owing to processing parameter, the variation that also do not link of its voltage level, guarantee comparatively difficulty of variations in threshold voltage, when the electrical specification of memory cell transistors such as threshold voltage changes, be difficult to guarantee reliably the tolerance limit that writes/read.

In addition, in the structure shown in the document 2, when writing data, the memory cell power lead of selecting row as quick condition, is sought to reduce the supply voltage of writing the memory cell of falling in lines, guarantee to write tolerance limit.But, in the document 2, improved the fact that writes tolerance limit and reduced power consumption though illustrate, do not consider about under the situation of the threshold voltage dispersion of memory cell transistor, improving the method for reading tolerance limit.

In prior art document 1 shown structure, memory cell transistor is made of thin film transistor (TFT) (TFT), even take place under the discrete situation at its threshold voltage, select the potential amplitude of word line by using the level-conversion circuit change, can realize writing and reading the improvement of tolerance limit.Specifically, in the prior art document 1, when data are write fashionable, be the potential level also higher with selecting word line to drive than memory cell power supply potential, make the current driving capability of the access transistor (access transistor) of memory cell become big, carry out high speed and write, seek to guarantee to write tolerance limit.In addition, when data are read, be the low voltage level of high side supply voltage by selecting word line to drive than memory cell, reduce the grid potential of the access transistor of memory cell, its current driving ability is reduced, seek to guarantee static noise margin, prevent the data corruption when data are read.

But, in the structure shown in the prior art document 1, the action power voltage of level-conversion circuit is supplied with from the system different with the memory cell supply voltage, and the voltage level after its level moves is the fixing voltage level that not influenced by the threshold voltage of memory cell.Even in patent documentation 1, also need in the system different, the power supply that level moves usefulness be set with the memory cell power supply, it is complicated that the structure of this power-supply system becomes.In addition, it selects the current potential of word line to fix, and can not tackle threshold voltage discrete of memory cell transistor neatly.

In addition, write fashionablely in data,, do not add any consideration write the fashionable data stability that is connected to the non-selection memory unit of selecting row in data with selecting word line to be driven into the level of the current potential higher than memory cell power supply.

Summary of the invention

The object of the present invention is to provide a kind of semiconductor storage, even under low supply voltage, also can stably carry out writing and reading of data with simple circuit configuration.

Another object of the present invention is to provide a kind of semiconductor storage, can follow the dispersing of threshold voltage of memory cell transistor neatly and adjust the selection word line potential, even under low supply voltage, also can guarantee to write and read tolerance limit.

Relate to the semiconductor storage of first viewpoint of the present invention, comprising: a plurality of static type memory cells that become rectangular arrangement; Corresponding to the configuration of each column of memory cells, connected a plurality of word lines of the memory cell of corresponding row respectively; A plurality of word line drivers configuration corresponding, that according to word line selection signal corresponding word lines is driven into selection mode with each word line.Each word line driver has the level moving meter that the voltage level of actuator electrical source node is moved to the voltage level lower than the voltage level of actuator electrical source node.Each word line driver when corresponding word lines is selected, is driven into corresponding word lines by this level moving meter and has moved voltage level behind the voltage level of actuator electrical source node.

Relate to the semiconductor storage of second viewpoint of the present invention, comprising: a plurality of static type memory cells that become rectangular arrangement; Corresponding to the configuration of each column of memory cells, connected a plurality of word lines of the memory cell of corresponding row respectively; A plurality of word line drivers configuration corresponding, that according to word line selection signal corresponding word lines is driven into selection mode with each word line; A plurality of drop down element corresponding to voltage level reduction each word line setting, when making corresponding word lines selected.

Relate to the semiconductor storage of the 3rd viewpoint of the present invention, comprising: become rectangular arrangement, comprise a plurality of static type memory cells of driving transistors of access transistor and storage data respectively; Corresponding to the configuration of each column of memory cells, and connected a plurality of word lines of access transistor of the memory cell of corresponding row respectively; Configuration corresponding with each word line, corresponding word lines is driven into a plurality of word line drivers of selection mode according to word line selection signal respectively; Disconnected from each other and along the memory cell column direction extend continuously and and each word line dispose across and and each word line in a plurality of active regions of cross section electrical couplings; With respect to each active region a plurality of grids that duplicate with spacing identical and layout configurations on the memory cell column direction with the grid of access transistor.These are a plurality of duplicate that grid is expert at and column direction on the adjusting to a line configuration, and each word line is coupled with corresponding active region in first side of the column direction that respectively duplicates grid.

The semiconductor storage that relates to the 3rd viewpoint of the present invention, further comprise: a plurality of control signal wires, with respectively duplicate grid across along column direction continuously configuration and also with respective column duplicate the grid electrical couplings, duplicate the grid transmission of control signals to respective column respectively; And a plurality of unit ground wire, electrical couplings is on second side and transmit ground voltage respectively, and this second side is faced mutually with first side of the column direction that respectively duplicates grid of each active region.

Relate to the semiconductor storage of the present invention's the 4th viewpoint, comprising: a plurality of static type memory cells that become rectangular arrangement; Corresponding to the configuration of each column of memory cells, connected a plurality of word lines of the memory cell of corresponding row respectively; A plurality of word line drivers configuration corresponding, that according to word line selection signal corresponding word lines is driven into selection mode with each word line; Dispose respectively corresponding to each memory cell columns, respectively with a plurality of unit power lead of the unit power supply node coupling of the memory cell of respective column; Corresponding to the configuration of each memory cell columns, when data are read, maintain ground voltage level, write the fashionable a plurality of draw power lines that become quick condition in data; With will corresponding to the configuration of each unit power lead, stop to unit power lead feed unit supply voltage that selecting row, a plurality of auxiliary elements that write that will be coupled with the draw power line of respective column at least corresponding to the unit power lead of selecting the row configuration simultaneously according to writing the indicator signal of falling in lines.

Relate to the semiconductor storage of the present invention's the 5th viewpoint, comprising: a plurality of static type memory cells that become rectangular arrangement; Corresponding to the configuration of each column of memory cells, connected a plurality of word lines of the memory cell of corresponding row respectively; Corresponding a plurality of word line drivers that be provided with, that when having specified the address, this corresponding word lines is driven into selection mode with each word line to corresponding word lines; The word line group that corresponds respectively to the defined amount of a plurality of word lines disposes, supplies with to the word line driver of corresponding word lines group a plurality of driver pre-charge circuits of first voltage level when selecting the word line of corresponding word lines group; The voltage of corresponding first level that be provided with, that respectively corresponding driver pre-charge circuit is exported with each driver pre-charge circuit moves to a plurality of level shift circuits than its low voltage level.

In the semiconductor storage that relates to first viewpoint, use the level moving meter be included in the word line driver that the drive electric source voltage level is moved and to selecting the word line transmission.Therefore, the selection word line potential when reading is reduced, the electricity of the access transistor of memory cell is led and is diminished, and can improve the static noise margin when reading, and stably carries out reading of data.

In addition, only use the level moving meter, the power supply that does not need level translation to use can make power supply architecture simplify.In addition, be not used for the level-conversion circuit that the voltage of word line is selected in conversion, can suppress the increase of the layout area of word line driver.

In the semiconductor storage that relates to second viewpoint, on each word line, connected drop down element, can will select the current potential of word line to be reduced to also lower than the supply voltage of word line driver.Therefore and the semiconductor storage of first viewpoint same, can improve the static noise margin of the memory cell when reading.

In addition, only use drop down element, the power supply that does not need to select the voltage transformation of word line to use can make power supply architecture simplify.

In addition, only on each word line, connect drop down element simply, do not needed to be used for the level-conversion circuit that the voltage level of word line is selected in conversion, can suppress the increase of the layout area of word line driver.

In the semiconductor storage that relates to the 3rd viewpoint, the drop down element that is connected on each word line disposes with the gate pitch identical with the access transistor of memory cell.Drop-down usefulness is transistorized duplicates that electrode follows and column direction adjusting to a line configuration.Therefore, than the structure of use dummy cell (dummy cell), can dispose the drop-down transistor unit of using more effectively.In addition, become conducting state with transistor unit, can will select word line potential to be set at optimized level, and can improve the static noise margin when reading reliably, can stably carry out reading of data by making the drop-down of required number.

In addition, in the semiconductor storage that relates to the 4th viewpoint, use the input auxiliary element, make unit power lead and the draw power line electrical couplings of selecting row, by its level is reduced, thereby the driving force of the load transistor of memory cell diminishes, but the driving force of access transistor is identical and do not change when reading, so can not lose and read tolerance limit and increase and write tolerance limit, realize writing at a high speed.In addition, be electrically connected unit power lead and draw power line, because electric charge moves, the voltage level of unit power lead changes at a high speed.In addition, the voltage level of unit power lead is cut apart by electric capacity and to be set at intermediate voltage level, can make to write the tolerance limit optimization.

In the semiconductor storage that relates to the 5th viewpoint, be used on the drive power supply line of word line driver transmission voltage, having connected the drop-down level shift circuit of using, can reduce the current potential of selecting word line by word line driver.Therefore and to relate to the semiconductor storage of first viewpoint same, can improve the static noise margin of the memory cell when reading.

In addition, only carry out supply voltage drop-down of word line driver, the power supply that does not need to select the voltage transformation of word line to use can make power supply architecture simplify.In addition, dispose level shift circuit jointly for a plurality of word line drivers, can reduce level and move the number of using element, and can suppress the increase of array area.

Above-mentioned and other purpose, feature, aspect and advantage of the present invention will be clearer and more definite from engage the of the present invention following detailed description that accompanying drawing understands.

Description of drawings

Fig. 1 is the integrally-built figure of the summary semiconductor storage of representing first example according to the present invention.

Fig. 2 is the figure of the electrical equivalent circuit of expression memory cell shown in Figure 1.

Fig. 3 is the figure of the word line driver structure shown in the summary table diagrammatic sketch 1.

Fig. 4 A and Fig. 4 B are the figure of the static noise margin of the action of expression word line driver shown in Figure 3 and memory cell.

Fig. 5 A and Fig. 5 B are depicted as the variation of the static noise margin of the voltage of selecting word line under the situation that the absolute value at the threshold voltage of memory cell transistor diminishes and memory cell.

Fig. 6 is the figure of expression modification of the word line driver of first example according to the present invention.

Fig. 7 is the integrally-built figure of the summary semiconductor storage of representing second example according to the present invention.

Fig. 8 is the figure of a routine structure of expression word line driver shown in Figure 7 and drop down element.

Fig. 9 is the figure that is illustrated in the electrical equivalent circuit when selecting word line in the present invention's second example.

Figure 10 A and 10B are the figure that selection word line voltage level under the bigger situation of the absolute value of the threshold voltage of memory cell transistor in pattern ground expression the present invention second example and static noise margin change.

Figure 11 A and 11B are the figure of the improvement of selection word line voltage under the less situation of the absolute value of the threshold voltage of memory cell transistor in pattern ground expression the present invention second example and static noise margin.

Figure 12 is the signal waveforms of the change in voltage of the main node of semiconductor storage in expression the present invention second example.

Figure 13 is the figure of level moving meter structure of the modification of expression the present invention second example.

Figure 14 is the figure of the allocation position effect of the drop down element in expression the present invention second example.

Figure 15 is the figure that summary is represented the modification of the drop down element in the present invention's second example.

Figure 16 is the figure that summary is represented the plane figure of drop down element in the present invention's second example and memory cell.

Figure 17 is the figure that summary is represented the structure of the word line driver of the 3rd example according to the present invention and drop down element.

Figure 18 is the signal waveforms of the action of expression word line driver shown in Figure 17 and drop down element.

Figure 19 is the figure of the structure of the summary memory cell array unit of representing the 4th example according to the present invention.

Figure 20 is the figure of a routine structure of expression word line driver shown in Figure 19 and drop down element.

Figure 21 is the signal waveforms of the action of expression word line driver shown in Figure 20 and drop down element.

Figure 22 is the figure of modification of the drop down element of expression the present invention the 5th example.

Figure 23 is the figure of voltage level change of the selection word line of the expression threshold voltage variation that depends on drop down element shown in Figure 22.

Figure 24 is the figure of the drop down element structure of expression the present invention the 5th example.

Figure 25 is the figure of the plane figure of the drop down element shown in the summary table diagrammatic sketch 24.

Figure 26 is the figure of plane figure of the drop down element of summary second modification of representing the present invention's the 5th example.

Figure 27 is the figure of the electrical equivalent circuit of expression drop down element shown in Figure 26.

Figure 28 is that summary is represented the array element of the semiconductor storage of the 6th example according to the present invention and the figure of word line selected cell structure.

Figure 29 is the figure of a routine structure of expression level shifter shown in Figure 28.

Figure 30 is the signal waveforms of the action of the word line of expression structure shown in Figure 28 when selecting.

Figure 31 is the figure of the array element structure of the summary modification of representing the present invention's the 6th example.

Figure 32 is the array element of summary second modification of representing the present invention's the 6th example and the figure of word line driving unit structure.

Figure 33 is the figure that expression word line voltage shown in Figure 32 is adjusted the structure of circuit.

Figure 34 is the figure of the word line driver structure shown in the summary table diagrammatic sketch 32.

Figure 35 is the plane figure that expression word line voltage shown in Figure 33 is adjusted circuit.

Figure 36 is the distributing figure on the upper strata of expression plane figure shown in Figure 35.

Figure 37 is the distributing figure on expression plane figure shown in Figure 36 upper strata.

Figure 38 is the integrally-built figure of the summary semiconductor storage of representing the 7th example according to the present invention.

Figure 39 A and 39B are the figure of concrete structure of the drop down element of expression semiconductor storage shown in Figure 38.

Figure 40 is the figure of the pith structure of expression semiconductor storage shown in Figure 38.

Figure 41 is the signal waveforms of the action of expression semiconductor storage shown in Figure 38.

Figure 42 is the figure that amplifies expression regional 1 signal waveform shown in Figure 41.

Figure 43 is the figure of a routine structure of the part of expression generation control signal shown in Figure 40.

Figure 44 is the figure of the plane figure of the active region of memory cell of expression the present invention the 7th example and first metal line.

Figure 45 is the layout of second metal line on the upper strata of expression distributing shown in Figure 40.

Figure 46 is the layout of the 3rd metal line on the upper strata of expression plane figure shown in Figure 45.

Figure 47 is the layout of the 4th metal line on the upper strata of expression distributing shown in Figure 46.

Figure 48 is the figure of expression Figure 44 to the electrical equivalent circuit of the memory cell of distributing shown in Figure 47.

Figure 49 is the figure of the plane figure of the active region of drop down element of expression the present invention the 7th example and first metal line.

Figure 50 is the plane figure of second metal line on expression distributing upper strata shown in Figure 49.

Figure 51 is the plane figure of the 3rd metal line on expression plane figure upper strata shown in Figure 50.

Figure 52 is the plane figure of the 4th metal line on the plane figure upper strata shown in expression Figure 51.

Figure 53 is the figure of expression Figure 49 to the electrical equivalent circuit of the drop down element of distributing shown in Figure 52.

Figure 54 is the structural drawing of expression pith of the semiconductor storage of the 8th example according to the present invention.

Figure 55 A and 55B are the figure that represents the concrete structure of the level shifter shown in Figure 54 respectively.

Figure 56 is the figure of the electrical equivalent circuit of the word line driver power supply unit the when data of semiconductor storage are read shown in expression Figure 54.

Embodiment

[first example]

Fig. 1 is the integrally-built figure of the summary semiconductor storage of representing first example according to the present invention.In Fig. 1, semiconductor storage comprises the memory cell array 1 with rectangular arrangement memory cell MC.In memory cell array 1, memory cell MC is arranged in (n+1) row (m+1) row.

With the corresponding word line WL0-WLn that is provided with of each row of memory cell MC, memory cell MC is connected respectively to the word line of corresponding row.In addition, with memory cell MC each row be provided with accordingly bit line to BL0 ,/BL0-BLm ,/BLm.The back will describe in detail, and memory cell MC is the static type memory cell, to complementary bit lines to BLi ,/the complementary data of BLi (i=0-m) transmission.

With bit line BL0 ,/BL0-BLm ,/BLm is to being provided with bit-line load (BL load) BQ respectively accordingly.This bit-line load BQ, when data are read, on draw the current potential of corresponding bit lines, in addition, the row electric current when supplying with memory cell data and reading.

In order in memory cell array 1, to have specified the word line of address to be driven into selection mode, be provided with according to the row decoder 2 of row address selection signal RA generation row selection signal with according to the word line driving circuit 3 that selected word line is driven into selection mode from the row selection signal of row decoder 2.Row decoder 2 is accepted laggard action with supply voltage VDD as action power voltage and is done, and generates row selection signal behind the decoding inner row address signal RA.

Word line driving circuit 3 corresponds respectively to word line WL0-WLn and is provided with, and comprises according to the word line driver WDR0-WDRn that corresponding word lines is driven into selection mode from the row selection signal of row decoder 2.Word line driver WDR0-WDRn accepts supply voltage VDD respectively as action power voltage, when selecting corresponding word lines, the level that carries out supply voltage VDD moves (reduction voltage), and uploads the voltage of transmission of electricity translation after moving to corresponding word lines.The action effect back of selecting the level of voltage to reduce about this word line will describe in detail.

Semiconductor storage and then comprise: select and select the right column select circuit 4 of row corresponding bit lines according to internal column address signal CA, to transmission being write the write circuit 5 of data with column select circuit 4 selected row corresponding bit lines, when reading, data detect from the right data of column select circuit 4 selected row corresponding bit line and amplify the sensing circuit 6 that the back generates sense data, according to the address signal AD that comes from the outside with write indicator signal WE and chip enable signal CE generates inner row address signal RA, internal column address signal CA and the main control circuit 7 of needed control signal of respectively moving.Main control circuit 7 generates word line activate timing signal, column selection timing signal, and the action of regulation row decoder 2 and column select circuit 4 timing and sequence of movement.

Write circuit 5 comprises input buffer and write driver circuits, and data are write fashionable, generates internal data according to the data DI that writes that comes from the outside.Sensing circuit 6 comprises reads amplifying circuit and output buffer, when data are read, by output buffer the content-data after detecting, amplify by the sensor amplifying circuit is carried out buffered, and generates outside sense data DO.

Write circuit 5 and sensing circuit 6, the data that can carry out a plurality of bit wides respectively write and read, in addition, also can constitute: memory cell array 1 is corresponding to 1 inputoutput data, and write circuit 5 and sensing circuit 6 carry out the input and the output of 1 bit data respectively.The writing of long numeric data/when reading, memory cell array 1 shown in Figure 1, write circuit 5 and sensing circuit 6 are configured corresponding to each data bit when carrying out.

In addition, supply to the high side power supply node of memory cell MC by unit power lead PVL from the array power supply voltage of array power circuit 8.This unit power lead PVL, in Fig. 1, for cutting apart setting according to each memory cell columns, but also can supply with array power supply voltage jointly to these unit power lead PVL from array power circuit 8, that is unit power lead PVL also can have and is arranged in line direction and the interconnective netted structure of column direction.

From the array power supply voltage of array power circuit 8, in this example and following example, be set at and the identical voltage level of supply voltage VDD of supplying with word line driver WDR.But, even array power supply voltage and the different voltage level of supply voltage of supplying with word line driving circuit also can use the present invention.In addition, array power circuit 8 and also can dispose respectively to the circuit of the peripheral circuit supply line voltage of word line driving circuit 3 etc.

Fig. 2 is the figure of the routine structure of expression memory cell MC shown in Figure 1.In Fig. 2, memory cell MC has the structure of whole CMOS single port sram cell.In Fig. 2, memory cell MC comprises: be connected between high side power supply node VH and the memory node ND1 and its grid is connected P channel MOS transistor (insulated-gate type field effect transistor) PQ1 of memory node ND2, be connected between memory node ND1 and the downside power supply node VL and its grid is connected the N-channel MOS transistor NQ1 of memory node ND2, be connected between high side power supply node VH and the memory node ND2 and its grid is connected the P channel MOS transistor PQ2 of memory node ND1, be connected between memory node ND2 and the downside power supply node VL and its grid is connected the N-channel MOS transistor NQ2 of memory node ND1, with according to the voltage on the word line WL respectively with memory node ND1 and ND2 and bit line BL and/ N-channel MOS transistor NQ3 and NQ4 that BL is coupled.

Word line WL is any one among the word line WL0-WLn shown in Figure 1, bit line BL and/BL be bit line BL0 shown in Figure 1 and/BL0-BLm and/among the BLm any one.

In the structure of memory cell MC shown in Figure 2, MOS transistor PQ1 and NQ1 constitute the CMOS phase inverter, and in addition, MOS transistor PQ2 and NQ2 constitute the CMOS phase inverter, the input of these phase inverters and output cross-couplings constitute anti-phase latch (trigger).On memory node ND1 and ND2, preserve data complimentary to one another.According to the data confining force of this anti-phase latch, determination data writes/tolerance limit when reading.

Fig. 3 is the figure of the routine structure of expression word line driver WDR0-WDRn shown in Figure 1.Word line driver WDR0-WDRn is because have identical structure, so in Fig. 3, these word line drivers are represented typically with word line driver WDR.

In Fig. 3, word line driver WDR comprises: accept from word line selection signal (decoded signal) WS of row decoder 2 phase inverter 10, according to the output signal of phase inverter 10 word line WL is driven and to be the word line driving stage 12 of selection mode.Phase inverter 10 is accepted supply voltage VDD as action power voltage, and counter-rotating word line selection signal WS.

Word line driving stage 12 comprises: the P channel MOS transistor PQ10 that connects a conducting node (source node) on the node of accepting supply voltage VDD, be connected between MOS transistor PQ10 and the word line WL and its grid accept the output signal of phase inverter 10 P channel MOS transistor PQ11, be connected word line WL and reference potential node (earthing potential level; To call the ground connection node in the following text) between and its grid accept the N-channel MOS transistor NQ10 of the output signal of phase inverter 10.

Grid and the drain electrode of MOS transistor PQ10 interconnect, and as diode action, and make supply voltage VDD reduce the quantity of the absolute value Vthp of its threshold voltage.The threshold voltage according of the MOS transistor by reducing one-level, even for example be low to moderate 1, under the situation of 2V, supply voltage VDD also can make word line driver 12 actions, and the selection word line voltage is reduced reliably, in addition, prevent from reduce to surpass needed selection word line voltage level, the access transistor of memory cell is maintained conducting state, thereby carry out reading and writing of data reliably.

The threshold voltage of MOS transistor PQ10, has the identical threshold voltage characteristic of P raceway groove load mos transistor (PQ1 and PQ2) with memory cell, link with the threshold voltage change of the load transistor (P channel MOS transistor PQ1 and PQ2) of memory cell MC, its threshold voltage changes.Word line WL is driven to voltage VDD-Vthp level during selection, the threshold voltage change of the voltage level that it is actual and the load transistor of memory cell changes in linkage.

Fig. 4 A is the figure that selects the voltage level of word line WL under the bigger situation of the absolute value Vthp of threshold voltage of load transistor (P channel MOS transistor PQ1, PQ2) of expression memory cell.In Fig. 4 A, supply voltage VDD represents the signal waveform of the word line WL under the situation of 1.2V.

Fig. 4 B represents that the absolute value Vthp of threshold voltage of the load transistor of memory cell is the transport property of the memory cell under the situation of bigger Vthp1.This transport property is the input and output transport property that constitutes two CMOS phase inverters of memory cell.In Fig. 4 B, memory node ND1 when curve N D1 that represents with solid line and ND2 represent to select the voltage level of word line WL to be supply voltage VDD level respectively and the transport property of ND2.Static noise margin SNM represents with the foursquare diagonal line of the solid line between curve N D1 and the ND2.

That is, if the load transistor (PQ1 of memory cell, it is big that the absolute value Vthp1 of threshold voltage PQ2) becomes, then the higher direction of input logic threshold value to the phase inverter of memory cell moves, and in addition, the current driving capability of load transistor diminishes, by access transistor (NQ3, NQ4) current driving capability carries out the discharge of the output node of a phase inverter more strongly, and the possibility that causes destroying the data of preservation increases.Therefore, data retention characteristics worsens, and transmission curve ND1 that this solid line is represented and the width of ND2 that is static noise margin SNM diminish.

In this case, in word line driver WDR, the absolute value of threshold voltage that level moves the P channel MOS transistor PQ10 of usefulness also becomes big corresponding to the absolute value Vthp1 of the threshold voltage of memory cell load transistor, select the voltage level of word line WL also to reduce (representing with voltage VDD-Vthp1) in Fig. 4 A.Therefore, in this case, the electricity of access transistor is led and is diminished, the rising of the L level voltage of the memory node of inhibition memory cell, in addition, in Fig. 4 B, such shown in dashed curve ND2A and ND1A, compare with block curve ND1 and ND2, transfer curve is the underside area broadening left.Correspondingly, like that, it is big that static noise margin SNM becomes, and improved and read tolerance limit shown in the diagonal line of dashed square.

For the write diagnostics of data, be under the situation of bigger Vthp1 at the absolute value Vthp of the threshold voltage of memory cell load transistor, the data retention characteristics of memory cell stable less, write diagnostics is improved.Therefore, writing fashionablely,,,, realizing writing at a high speed so also can suppress influence for write diagnostics because it is big to write tolerance limit even will select the voltage level of word line WL to be set at the voltage level lower than voltage VDD.

Fig. 5 A is illustrated in the potential change of the selection word line under the less situation of the absolute value of threshold voltage of memory cell load transistor, and Fig. 5 B is the figure of the input and output transport property under the less situation of the absolute value of threshold voltage of load transistor of this memory cell of expression.

In Fig. 5 A, consider that the absolute value of threshold voltage of the load transistor of memory cell is Vthp2, than the little state of the absolute value Vthp1 of previous threshold voltage.In this case, even in word line driver, the threshold voltage vt hp of the MOS transistor PQ10 that the reduction level of diode connection (diode-connected) is used becomes the value corresponding with voltage Vthp2 too, and the voltage level of the selection mode of word line WL becomes the voltage level corresponding with voltage VDD-Vthp2.

Shown in Fig. 5 B, under the lower situation of the absolute value of the load transistor threshold voltage of memory cell, shown in its solid line curve N D1 and ND2 like that, even be driven at word line WL under the situation of voltage VDD level, static noise margin SNM is also fully big, can guarantee to read tolerance limit.This be because: the current supply ability of load transistor improves, L level by access transistor is suppressed to the charging of the H of memory node level, in addition, in memory cell, because the driving transistors (NQ1 that the current potential of memory node come-up causes, NQ2) discharge compensates by load transistor, can stably preserve data in the anti-phase latch of memory cell.

In this state, low under the situation of voltage VDD-Vthp2 at the voltage level of selecting word line WL, the electricity of access transistor is led a little and is reduced, shown in the dashed curve ND2B and ND1B of Fig. 5 B, transfer curve broadening in the territory, lateral areas, lower-left of block curve ND1 and ND2 has improved static noise margin SNM a little.

Therefore, in word line driver, if constituting the threshold voltage of the load transistor of the threshold voltage of the P channel MOS transistor PQ10 that this diode is connected and memory cell changes in linkage, then when under the situation of the higher deviation in driction of the absolute value Vthp of the load transistor threshold voltage of memory cell, select the voltage level of word line to move to the lower direction of value, otherwise, if, then select the voltage level of word line to move to the higher direction of value to the lower deviation in driction of absolute value of the threshold voltage of the load transistor of this memory cell.Therefore, under deviation in driction that the absolute value to the load transistor threshold voltage of memory cell uprises causes situation that static noise margin SNM diminishes, select corresponding reduction of voltage level of word line, it is big that its reduction amplitude becomes, and improves static noise margin SNM.In addition, when under the situation of the lower deviation in driction of the absolute value Vthp of the threshold voltage of the load transistor of memory cell, it is fully big that static noise margin SNM becomes, and do not need to improve the static noise margin that surpasses needs.In this case, select the reduction amount less (voltage Vthp2) of the voltage level of word line, select the voltage level of word line WL to rest on the degree that reduces a little than supply voltage VDD.

Under the lower situation of the absolute value Vthp of the threshold voltage of the load transistor of memory cell, it is big that the data retention characteristics of memory cell becomes, and has data to write to become the tendency of difficulty.But, in this case, select the voltage level of word line because be set at the higher voltage level, so the current driving capability of access transistor becomes greatly, write tolerance limit and improve.

Therefore, select the voltage level of word line and automatically to adjust corresponding to the threshold voltage change of the load transistor of memory cell.That is, reading under the less situation of tolerance limit, reduce the voltage level of selecting word line, improve static noise margin.On the other hand, reading under the bigger situation of tolerance limit,, making and select the voltage level of word line not reduce, can set the voltage level of selecting word line writing on the direction that tolerance limit increases surpassing when needing.Thus, discrete for the threshold voltage of memory cell load transistor automatically selected the correction of word line voltage level, can realize the static semiconductor memory device that can more stably move.

The load transistor PQ1 of memory cell and the level of PQ2 and word line driver move the MOS transistor of usefulness, and its threshold voltage characteristic has linkage each other and gets final product, and special requirement are not identical.

Fig. 6 is that level that expression is included in the word line driving stage 12 in the word line driver moves the figure with the routine structure of transistor PQ10.In Fig. 6, level moves to comprise with transistor PQ10 and is connected in parallel with each other and a plurality of P of unit channel MOS transistor PU0-PUk that diode connects.The MOS transistor PU0-PUk of these units have respectively be included in memory cell MC in load transistor PQ1 and identical or same threshold voltage (Vth) characteristic of PQ2.That is the size of unit transistor PU0-PUk (the ratio W/L of channel width and channel length) is respectively load transistor PQ1 and PQ2 about 0.5 times to 5 times.Be preferably set to size ratio with 0.8 times to 2 times.More satisfactory ground, (grid width is identical to be preferably set to same size; The situation that grid length is identical).If size has 1 difference, think that then the linkage (threshold voltage change linkage) of electrical specification that load transistor and level move the unit transistor of usefulness departs from, select the influence that the transistorized threshold voltage of reflected load correctly changes in the voltage of word line.But, if between the transistor of 0.5 times to 5 times size ratio, then the electrical specification of MOS transistor can link substantially, in the P of unit channel MOS transistor, can correctly reflect the threshold voltage change of the load transistor of memory cell MC, accordingly, in moving with the threshold voltage of MOS transistor PQ10, level can reflect the threshold voltage change of memory cell load transistor.

Unit transistor to the size of load transistor than preferred the reasons are as follows in 0.8 times to 2 times scope: usually, in manufacturing process, consider the discrete of Fabrication parameter and mask contraposition etc., allow maximum about 10% discrete.Therefore, than (grid width when grid length is identical), consider to be 0.9 times sometimes, and then estimated margin is 10% that lower limit is set at 0.8 times as size.In addition, compare with the situation of grid width broad, the bigger tendency of change that under the narrower situation of grid width, has threshold voltage, though also rely on the grid width of load transistor, if but grid width (size) is above 2 times, think that then the linkage to the change of the threshold voltage of load transistor diminishes, so preferred size is smaller or equal to 2 times.

Because set the amount of drive current of word line driving stage 12, so the number of the P of unit channel MOS transistor that constitutes level moving meter PQ10 is corresponding to desired word line amount of drive current and be defined as suitable value corresponding to the actuating speed of word line.

In addition, phantom order bit transistor PU0-PUk is identical with load transistor PQ1 and PQ2 pattern layout, and in addition, the impurity injection condition is also identical.Thus, can further improve level and move linkage with the threshold voltage characteristic of the load transistor PQ1 of the threshold voltage characteristic of MOS transistor PQ10 and memory cell and PQ2, can correctly adjust level corresponding to the change of the threshold voltage of load transistor PQ1 and PQ2 and move selection word line voltage level, and can be correctly change and revise the selection word line voltage level corresponding to the threshold voltage of load transistor with MOS transistor PQ10.Thus, can in broad scope, improve operation margin corresponding to supply voltage, temperature conditions and process deviation.

Move transistor PQ10 as this level, owing to use a plurality of P of unit channel MOS tube PU0-PUk, so may be subjected to that the edge shape of in each element impurity concentration instability or layout is discrete to wait the influence of dispersing at random, but form level and move transistor by a plurality of being connected in parallel, thereby it is can equalization this discrete at random, can correspondingly eliminate discrete at random, by using the transistor with the load transistor PQ1 of memory cell MC and the size of PQ2 same degree (can preferably adopt size to realize identical electrical specification) from same size (0.8 times) to about 2 times (sizes from 0.5 times to 5 times in the scope also can), even thereby use the little transistor of size, the discrete equalization of characteristic that also can the P of the unit of making channel MOS tube PU0-PUk, more exactly, can correctly revise the selection voltage level of word line WL corresponding to the load transistor PQ1 of memory cell MC and the threshold voltage dispersion of PQ2.

As mentioned above,, use the level moving meter to reduce the voltage level of selecting word line,, can stably keep and read characteristic and write diagnostics for the threshold voltage dispersion of the load transistor of memory cell according to first example of the present invention.Particularly,, have the transistor of the threshold voltage characteristic identical, can correctly reflect the discrete of memory cell load transistor, and revise automatically and select word line voltage level with the memory cell load transistor by use as this level moving meter.

In addition, only use the level moving meter that drive electric source voltage generation level is moved, and to selecting the word line transmission, power-supply system can prevent that with existing identical the structure of power circuit from becoming complicated.

In structure shown in Figure 3, on each word line driver WDR, be provided with the P channel MOS transistor PQ10 that level moves the diode connection of usefulness, but this level moves the P channel MOS transistor PQ10 that the diode of usefulness connects also can public setting on word line driver WDR0-WDRn.

[second example]

Fig. 7 is the integrally-built figure of the summary semiconductor storage of representing second example according to the present invention.At the semiconductor storage shown in this Fig. 7, the structure with semiconductor storage shown in Figure 1 is different in the following areas.

That is, in Fig. 3, in word line driving circuit 3, with word line WL0-WLn word line driver WDV is set accordingly respectively.This word line driver WDV does not have the level locomotive function.Supply voltage VDD is accepted as action power voltage, and according to the word line selection signal from row decoder 2, it is supply voltage VDD level that word line WL0-WLn is driven when selecting.

For word line WL0-WLn, drop down element PD is set respectively.This drop down element PD constitutes the charging that comprised among the word line driver WDV that will be hereinafter describes with reference to Fig. 8 with P channel MOS transistor (PQ15) and resistor voltage divider circuit, cuts apart the voltage level that will select word line by resistance and is set at voltage level between supply voltage VDD level and the ground voltage level.

Other structures of the semiconductor storage that this is shown in Figure 7, identical with the structure of semiconductor storage shown in Figure 1, give identical cross reference number for corresponding part, omit its detailed description.

In second example of the present invention, selecting the voltage level of word line is the branch voltage level that supply voltage VDD is carried out electric resistance partial pressure, its voltage level becomes the voltage level lower than supply voltage VDD, identical with first example, can how to change regardless of the threshold voltage of memory cell transistor all to keep and read tolerance limit and write tolerance limit.

Fig. 8 is the figure of the routine structure of expression word line driver WDV shown in Figure 7 and drop down element PD.In Fig. 8, word line driver WDV comprises: receive the phase inverter 10 from the word line selection signal WS of row decoder 2, formation is carried out the CMOS phase inverter of anti-phase and driving word line WL to the output signal of phase inverter 10 P channel MOS transistor PQ15 and NQ15.

When word line WL was selected, word line selection signal was the H level, and correspondingly, the output signal of phase inverter 10 becomes the L level, and P channel MOS transistor PQ15 conducting is to the supply voltage VDD of word line WL transmission from power supply node.

Drop down element PD comprises the N-channel MOS transistor NQ20 with the resistance mode action.That is the grid of MOS transistor NQ20 and drain electrode are connected to word line WL, and its source electrode for example is coupled with the ground connection node.

Therefore, when selecting word line WL, constitute resistor voltage divider circuit by the conducting resistance of MOS transistor PQ15 and the conducting resistance of MOS transistor NQ20, word line WL is set to the voltage level corresponding with its intrinsic standoff ratio.

Pull-down transistor NQ20 is configured in the memory cell array, have the threshold voltage characteristic same with driving transistors NQ1, the NQ2 of memory cell, if the threshold voltage of memory cell driving transistors NQ1, NQ2 reduces, then the threshold voltage of pull-down transistor NQ20 reduces too, its amount of drive current increases, and conducting resistance reduces equivalently.In this case, select the voltage level of word line correspondingly to reduce.

Fig. 9 is the figure that is illustrated in the electrical equivalent circuit of word line driver WDV when selecting word line WL and drop down element PD.When selecting word line WL, the conducting resistance Rp of MOS transistor PQ15 is connected between power supply node and the word line WL, connects the conducting resistance Rn of MOS transistor NQ20 between word line WL and ground connection node.Therefore, the voltage level of word line WL can be used VDDRn/ (Rp+Rn) expression.

Figure 10 (A) is the change in voltage figure that is illustrated in the selection word line under the lower situation of the threshold voltage vt hn of memory cell driving transistors (NQ1, NQ2), (B) is the input and output transport property figure under the lower situation of the threshold voltage of expression memory cell driving transistors NQ1, NQ2.Under the lower situation of the threshold voltage vt hn of memory cell driving transistors NQ1, NQ2, the threshold voltage of the N-channel MOS transistor NQ20 of drop down element PD reduces too, and its current driving capability increases, and electricity is led equivalence and increased.That is conducting resistance Rn reduces.Therefore, select the voltage VWL of word line to represent with following formula.

VWL＝VDD/(1+(Rp/Rn))

Therefore, under the situation that the conducting resistance Rn of MOS transistor NQ20 diminishes, as the conducting resistance Rp that supposes MOS transistor PQ15 is constant, and (linkage of the transistorized threshold voltage change of word line driver is little, compare with the change of the threshold voltage of memory cell transistor, the change of the transistorized threshold voltage of word line driver is fully little), then intrinsic standoff ratio diminishes, and selects the voltage level of word line voltage VWL to reduce (the drop-out voltage quantitative change is big).

Under the lower situation of the threshold voltage of driving transistors NQ1, the NQ2 of memory cell, in memory cell inside, the current potential of the memory node of high side becomes and discharges easily, shown in the block curve ND1 of Figure 10 (B) and ND2 like that, the narrowed width of the voltage-transfer characteristic of node ND1 and ND2, static noise margin SNM diminishes.In this case, the voltage level of word line WL is reduced greatly, and the electricity of access transistor is led diminish.Thus, it is big that the memory node ND1 of memory cell inside and the resistance between ND2 and the word line become, and suppresses the current potential come-up (memory node that is caused by access transistor when word line is selected on draw die down) of inner memory node ND1 and ND2.

Therefore, such shown in curve N D2C and ND1C, according to the less variation of storage node voltage level, begin discharge fast, voltage-transfer characteristic curve is at the territory, lateral areas, lower-left of curve N D1 and ND2 broadening, and the width of its input and output transport property broadens, and it is big that static noise margin SNM becomes.Therefore, under the situation that the threshold voltage of memory cell driving transistors reduces greatly, correspondingly, the current potential reduction amount of word line also becomes greatly, and the electricity of access transistor is led reduction, reads tolerance limit and increases, and can stably carry out data and read.

Figure 11 A is the change in voltage figure of the selection word line WL under the threshold voltage vt hn condition with higher of expression memory cell driving transistors NQ1 and NQ2, and Figure 11 B is the input and output transport property figure under the low situation of expression memory cell drive transistor threshold voltage.

Under the bigger situation of the threshold voltage vt hn of memory cell driving transistors NQ1 and NQ2, current driving ability diminishes, and it is big that its conducting resistance becomes.Therefore, according to above-mentioned formula, the conducting resistance of the N-channel MOS transistor NQ2 of drop down element PD also becomes greatly, and the voltage level of selection word line WL becomes the less high-voltage level of reduction amount of supply voltage.

Shown in Figure 11 B, under the threshold voltage vt hn condition with higher of the driving transistors NQ1 of memory cell and NQ2, even the current potential of the memory node of the L level of its internal node come-up, the maintenance potential level of H level does not change yet, and static noise margin SNW is with the same big originally.Under the voltage level of the selecting word line WL situation lower than supply voltage VDD, corresponding its reduction amount, the electricity of access transistor is led and is diminished, a little improvement of static noise margin.When under the situation of the higher deviation in driction of the threshold voltage vt hn of memory cell driving transistors, it is very big that static noise margin SNM becomes, and do not need to surpass the improvement of needs.In this case, select the voltage reduction amount of word line less, selecting the voltage level of word line is the level that reduces a little from supply voltage VDD.

Under the lower situation of the threshold voltage vt hn of memory cell driving transistors,, big and no problem because write tolerance limit originally under this state even the selection voltage of word line is set at lower voltage level.In addition, under situation about moving, because select the voltage level of word line to move, so the direction that writes tolerance limit to improvement moves to higher direction to the higher direction of the threshold voltage vt hn of this memory cell driving transistors.

Figure 12 is the figure of the change in voltage of bit line when data write and read in expression the present invention second example and memory node.

That is, when sense data, be driven at word line WL under the situation of selection mode, be the voltage level lower by its voltage level of drop down element PD than supply voltage VDD.Along with the driving of word line WL to selection mode, bit line BL and/the memory node ND1 and the ND2 coupling of BL and selection memory unit, its voltage level is along with selection memory unit storage data and change.In the memory cell, in memory node ND1 and ND2, keep the voltage level of the memory node of L level data also to rise by the row electric current that flows through bit line.Therefore, even in this case, also can be corresponding to driving transistors (NQ1, NQ2) threshold voltage, set the voltage level of selecting word line WL by drop down element PD, adjust the electricity of access transistor and lead, fully guarantee the static noise margin SNM of memory cell, stably carry out reading of data, the destruction of data can not taken place.

Write fashionable also equally in data, the voltage level of word line WL also reduces its voltage level by drop down element PD.In this case, bit line BL and/one among the BL be driven to the L level according to writing data.In this case, set the voltage level of selecting word line, can fully guarantee to write tolerance limit, carry out normal and data at a high speed write corresponding to the threshold voltage vt hn of memory cell driving transistors.

In addition, the action waveforms that this is shown in Figure 12 also can be suitable for for first example.In this case, replace because the decline of the word line voltage that drop down element PD causes, corresponding to the threshold voltage of load transistor, the level by word line driver moves the level adjustment that transistor (PQ10) carries out word line voltage.

As mentioned above, by this drop down element, can adjust the voltage level of selecting word line corresponding to the change of the threshold voltage of memory cell driving transistors.That is, reading under the little situation of tolerance limit (threshold voltage of memory cell driving transistors lower situation under), reduce the voltage level of selecting word line, improve static noise margin SNM, on the other hand, reading (under the threshold voltage condition with higher of memory cell driving transistors) under the bigger situation of tolerance limit, thereby by making the voltage level of selecting word line excessively not reduce and can write at a high speed.Thus, discrete for the threshold voltage of memory cell driving transistors revised the voltage level of selecting word line automatically, and correspondingly, that can revise memory cell writes and read tolerance limit, and carries out more that stable data writes/read action at a high speed.By this word line voltage adjustment operation, even for writing tolerance limit, also can automatic setting, so that the processing change caused discrete (writing the discrete of tolerance limit) of the threshold voltage of memory cell driving transistors is revised.

[first modification]

Figure 13 is the figure of expression modification of the drop down element of second example according to the present invention.In this structure shown in Figure 13, the N-channel MOS transistor NQ21 that drop down element PD accepts supply voltage VDD by its grid constitutes.The drain electrode of this MOS transistor NQ21 is connected to word line WL, source electrode and the coupling of ground connection node.Word line WL drives by word line driver WDV.This word line driver WDV has the structure identical with structure shown in Figure 8.

Under the situation of this drop down element PD shown in Figure 13, the grid of MOS transistor NQ21 is accepted supply voltage VDD, and maintains conducting state usually, comes the current potential of drop-down word line WL by its channel resistance.Therefore, with word line when selection mode drives, the current potential of word line WL, before the threshold voltage vt hn that rises to more than or equal to pull-down transistor NQ21, MOS transistor NQ21 becomes conducting state, can carry out drop-down action from the moment early.

In this MOS transistor NQ21, its conducting resistance also with the interlock of the threshold voltage of memory cell driving transistors, if the threshold voltage of memory cell driving transistors raises, then the conducting resistance of this drop-down MOS transistor NQ21 also becomes (current driving capability diminishes) greatly.Therefore, also same even use this structure shown in Figure 13 with previous structure shown in Figure 8, can be according to memory cell driving transistors (NQ1, the change of threshold voltage NQ2), the voltage level of adjustment selection word line WL.

[second modification]

Figure 14 is the figure of structure of second modification of the summary semiconductor storage of representing second example according to the present invention.Shown in Figure 14: on word line WL, near the situation of word line driver WDV configuration drop down element PDa and at the drop down element PDb of the far-end configuration of the word line driver WDV that leaves word line WL.Use any one among drop down element Pda and the PDb.

Disposing near word line driver WDV under the situation of drop down element PDa, the voltage level of word line WL is not subjected to the influence of the wiring resistance R w1 of word line, is set at the voltage level of VDDRn/ (Rp+Rn).Therefore, can set the current potential of word line WL corresponding to the value of the conducting resistance Rn of drop down element PDa.

On the other hand, same under the situation of using drop down element PDb, be Rn if suppose its conducting resistance, in the end near word line driver WDV, the voltage VWL1 of word line WL represents with following formula.

VWL1＝VDD·(Rw1+Rn)/(Rp+Rw1+Rn)

On the other hand, the voltage VWL2 at the word line WL of word line WL far-end represents with following formula.

VWL2＝VDD·Rn/(Rp+Rw1+Rn)。

Therefore, current potential for this word line WL, the influence of word line resistance Rw1 is worked, the selection voltage level of correctly adjusting word line WL corresponding to the conducting resistance Rn of the drop down element PDb difficulty that becomes, it is very difficult to change the voltage level of adjusting word line WL corresponding to the threshold voltage of this memory cell driving transistors.Therefore, under the situation of the selection voltage level of correctly revising word line WL corresponding to the change of the threshold voltage of memory cell driving transistors, this drop down element PD drop down element Pda as shown in figure 14 is like that as far as possible near word line driver WDV, that is to say, preferably between word line driver and memory cell, dispose.

In addition, less at word line resistance Rw1, for the less situation of influence of the resistance ratio of division that produces by drop down element PD, also can use the drop down element PDb of word line far-end.In addition, also can use these drop down element PDa and PDb both.

In addition, as the structure of drop down element PDa, also can use any one among the MOS transistor NQ21 that applies supply voltage VDD on MOS transistor NQ20 shown in Figure 8 or its grid as shown in figure 13 usually.

[the 3rd modification]

Figure 15 is the figure of structure of the 3rd modification of expression the present invention second example.In Figure 15, drop down element PD and memory cell MC are shown.Drop down element PD comprises the N-channel MOS transistor NU0-NUk of unit of a plurality of parallel connections.The grid of these N-channel MOS transistors NU0-NUk is connected to word line WL or accepts supply voltage VDD jointly.The N-channel MOS transistor NU0-NUk of these units has driving transistors NQ1 and the identical threshold voltage condition of NQ2 with memory cell MC.That is (ratio of channel width W and channel length W/L) is set with the driving transistors NQ1-NQ2 of N-channel MOS transistor NU0-Nuk of these units and memory cell as far as possible in the same manner with impurity injection condition, layout and size in the channel region.Therefore, form these driving transistorss NQ1 and NQ2 and the N-channel MOS transistor NU0-NUk of unit with identical manufacturing process.Thus, driving transistors NQ1 by improving memory cell MC and the discrete linkage of characteristic of NQ2, can be corresponding to the selection voltage level that disperses and revise word line WL of the threshold voltage of memory cell driving transistors NQ1 and NQ2, and can be discrete etc. to supply voltage, operating temperature condition and technology, in wide scope, improve operation margin.

Resistance value Rn for drop down element PD, usually, for the selection voltage level that makes word line WL is reduced to 100mV to about the 200mV, the charging of setting this word line driver WDV is with the conducting resistance (Rp) of P channel MOS transistor and the resistance ratio of division of drop down element PD (conducting resistance).

As this drop down element PD, owing to use a plurality of N-channel MOS transistor NU0-NUk of unit, may be subjected to the discrete at random influence such as discrete of the edge shape of impurity concentration instability in each element or layout, but adopt a plurality of parallel connections to connect drop down element PD, thereby can on average this disperse at random, and correspondingly can eliminate discrete at random.By use and the transistor of the driving transistors NQ1 of memory cell MC and the size of NQ2 same degree (can adopt from identical size and realize identical electrical specification) to about 2 times of life size as unit transistor, even use the little transistor of size, also on average the characteristic of unit N-channel MOS transistor NU0-NUk is discrete, more exactly, can be according to the selection voltage level that disperses and correctly revise word line WL of the threshold voltage of the driving transistors NQ1 of memory cell MC and NQ2.

Number to the N-channel MOS transistor NU0-NUk of unit is set, so that set optimized resistance ratio of division corresponding to the charging of word line driver WDV with the resistance value of the conducting resistance Rp of P channel MOS transistor, and makes its number optimization.

In addition, in drop down element PD, under the transistorized situation of a plurality of N-channel MOSs that has been connected in parallel, conducting resistance is considered to because this is connected in parallel and combined resistance diminishes.But,, set the voltage level of word line WL by being included in charging among the word line driver WDV with transistorized current driving capability be included in the synthetic current driving capability of the N-channel MOS transistor NU0-NUk of unit among this drop down element PD.Therefore, by being adjusted at the number of the N-channel MOS transistor NU0-NUk of unit that comprises among this drop down element PD, thereby can adjust the selection voltage level of word line WL, correspondingly can adjust to revise and select voltage level corresponding to the change of the threshold voltage of the driving transistors NQ1 of memory cell MC and NQ2.

[the 4th modification]

Figure 16 is the figure of structure of the 4th modification of expression the present invention second example.In Figure 16, the plane figure of expression drop down element PD and memory cell MC.In Figure 16, memory cell MC comprises: active region AC4 that forms in the N well area and AC5 and the active region AC3 and the AC6 that form respectively in the P well area of these N trap both sides.In active region AC4 and AC5, form respectively load transistor (PQ1, PQ2).In active region AC3 and AC6, form respectively driving transistors (NQ1, NQ2) and access transistor (NQ3, NQ4).

The length that active region AC3 has directions X is the zone (narrow width regions) of W2 and the length W3 zone (broad width regions) longer than length W2 of directions X.Polysilicon wire TG2 is set so that, in addition, polysilicon wire TG3 is set so that at directions X crosscut broad width regions at the narrow width regions of directions X crosscut active region AC3.Be formed for being electrically connected contact (contact) CC3 of bit line BL in the end of the directions X of the narrow width regions of active region AC3, be provided for accepting the contact CC6 of ground voltage VSS in the end of the directions X of broad width regions.Between these polysilicon wire TG2 and TG3, in the AC3 of active region, form the contact CV3 that is electrically connected the first metal line FM1.The first metal line FM1 is configured to extend to active region AC4 along directions X always.

In the AC4 of active region, be formed for accepting the contact CC7 of supply voltage VDD in the end of directions X, at the other end common contact SCT1 is set.This common contact SCT1, an end and active region AC4 coupling, the other end is connected with the polysilicon wire TG4 that disposes in the mode of crosscut active region AC5 and AC6 on directions X.Therefore this common contact SCT1 has contact and two kinds of functions of middle connecting wiring.This common contact SCT1 also is electrically connected on the metal line FM1 on upper strata.By this metal line FM1, each extrinsic region (drain electrode) of load transistor, driving transistors (NQ1) and access transistor (NQ3) is connected with memory node.

In the AC5 of active region, the end formation common contact SCT2 at directions X connects polysilicon wire TG3 on this common contact SCT2.This common contact SCT2 is connected in addition and is electrically connected with active region AC5 and on the metal line FM2 that directions X extends.Be formed for accepting the contact CC4 of supply voltage VDD at the other end of active region AC5.Form the grid of load transistor by the polysilicon wire TG4 that disposes in mode along directions X crosscut active region AC5.

In the AC6 of active region, be formed for being coupling in the contact CC5 on the ground voltage in the end of the directions X of broad width regions, polysilicon wire TG4 is configured to crosscut on directions X.This polysilicon wire TG4 constitutes the grid of driving transistors NQ2.In addition, in the other end of this broad width regions, be connected on the metal line FM2 by contact CV4.

Form polysilicon wire TG5 in mode, be formed for being electrically connected the contact CC8 of complementary bit lines/BL in the end of this narrow width regions along the narrow width regions of directions X crosscut active region AC6.

In mode at directions X crosscut memory cell MC, with metal line FM1 and FM2 is parallel and thereon layer form metal line SM1.This metal line SM1 constitutes word line WL, and extends continuously on directions X, is coupled with word line driver, and is coupled with drop down element PD.Metal line SM1 is coupling on the polysilicon wire TG5 by path (via)/contact VV3 at the outshot of its Y direction, in addition, is coupling on the polysilicon wire TG2 by path/contact VV2 at the outshot of-Y direction.

By the connection by the metal line SM1 that constitutes this word line, the grid of access transistor is connected respectively on the word line.In active region AC3 and AC6, form broad width regions and narrow width regions, and on active region AC3 and AC6, form memory cell driving transistors and access transistor.The width of the directions X of active region AC3 and AC6 is corresponding with transistorized grid width W.Therefore, length W1 is corresponding with the grid width of access transistor, and length W3 is corresponding with the grid width of driving transistors.Usually, from the viewpoint of the static noise margin of guaranteeing memory cell, the grid width W3 of driving transistors is set at 0.5 times to 5 times the value of the grid width W1 of access transistor, is preferably set to 0.8 times to 2.0 times.

In drop down element PD, form Y direction the active region AC1 and the AC2 of long rectangular shape separately.These active regions AC1 and AC2 form in the P well area.Shown in Figure 16: the P trap of memory cell MC extends to the formation zone of drop down element PD always, in memory cell MC and drop down element PD, and public use P trap (because memory cell MC is adjacent with drop down element PD).But,, also the P trap can be set respectively for memory cell MC and drop down element PD.

Be formed for accepting CC1 and the CC2 of ground voltage VSS at the downside end of the Y of active region AC1 and AC2 direction, form via-contacts CV1 and CV2 at the other end.These paths/contact CV1 and CV2 and metal line FM3 are coupled.Mode with these active regions AC1 of crosscut on directions X and AC2 has disposed the metal line SM1 that constitutes word line WL, and path/contact VVA is connected to metal line SM1 in the outshot of its Y direction.On the other hand, form path VV1 with respect to polysilicon wire TG1, by this path VV1, polysilicon wire TG1 is connected with metal line SM1.Thus, in active region AC1 and AC2, realize the transistorized grid of drop down element PD and the structure that drain electrode is connected to word line.

The width W 0 of the directions X of active region AC1 and AC2 is set between the width W 1 and W3 of memory cell transistor.In addition, the transistorized grid of memory cell MC is gone up in the direction (directions X) identical with the transistorized grid of drop down element PD and is extended.By these transistorized grids of configured in parallel, edge effects in the time of can making photomechanical production etc. are identical, and can suppress the discrete of transistor shape, in addition, it is poor that the impurity that generation causes owing to gate shapes in the time of can being suppressed at implanted dopant injects, and can suppress the difference of transistor characteristic.Thus, the transistor characteristic of the transistor characteristic of drop down element PD and memory cell similarly can be set (can make the change interlock of transistor characteristic), and can be set the voltage level of selecting word line corresponding to the change of the threshold voltage of memory cell transistor.

In addition, in the above description, the transistor that the flutter of use and memory cell driving transistors links is adjusted the voltage level of selecting word line.But the transistor that also can use the change with the threshold voltage of the access transistor of memory cell to link forms drop down element.

That is if the threshold voltage of the access transistor of memory cell reduces, then the current driving ability of access transistor becomes big, and the static noise margin of memory cell reduces.In this case, select the corresponding reduction of voltage of word line, make the electricity of access transistor lead reduction, its current driving capability is reduced, correspondingly suppress the reduction of static noise margin, improve and read tolerance limit.Write for data, under the lower situation of the threshold voltage of access transistor, guarantee to write tolerance limit,, also can fully guarantee to write tolerance limit even word line voltage reduces.

In addition, if the threshold voltage of access transistor rises, then the current driving capability of access transistor reduces, and can guarantee static noise margin substantially.In this case, the threshold voltage of drop down element also rises, and suppresses to select the voltage reduction amount of word line, suppresses excessive selection word line voltage and reduces.Writing fashionablely, writing tolerance limit and reduce and reduce, but it is little to reduce to select the voltage of word line to reduce quantitative change, suppresses to write the deterioration of tolerance limit, realizes writing at a high speed corresponding to the current drives amount of access transistor.

In addition, for the transistor that constitutes this drop down element is had and memory cell driving transistors (NQ1, NQ2) identical electrical specification, be made into its impurity injection condition, layout, size etc. identical, thereby can correctly link with the threshold voltage change of this memory cell driving transistors, adjust the conducting resistance (conducting resistance of equivalence) of drop down element, and can correctly select the automatic correction of the voltage level of word line WL.

Specifically, the transistorized size of the unit N-channel MOS (ratio of channel length and channel width that this is shown in Figure 16,0.5 times to 5 times, preferred about 0.8 times the size that the channel width when perhaps channel length is identical), also can have the size of memory cell driving transistors NQ1 and NQ2 or access transistor NQ3 and NQ4 to 2 times of left and right sides scopes.This be because, it is generally acknowledged by with the transistorized value that is sized to size (ratio of grid width and grid length) of unit N-channel MOS, thereby can make the change of electrical specifications such as these transistorized threshold voltage changes identical near access transistor and/or driving transistors.It is generally acknowledged, if size has 1 difference, then the linkage of the electrical specification of unit transistor and access transistor and/or driving transistors diminishes, and/or reflects that by unit transistor the change of the electrical specification of driving transistors will become very difficult in drop down element.

Comparatively ideally be, preferably make size (grid width) identical, still, usually, discrete for transistorized form parameter adjusted manufacturing process it is in the discrete range about 10.Therefore, even during fabrication, just often, the size that has drop-down unit transistor is 0.9 times a situation of memory cell transistor, as considering that tolerance limit then is set at the lower limit of size 0.8 times size.Even in this case, also can guarantee the linkage of the threshold voltage change of the transistor of memory cell and pull-down transistor, can correctly set and select word line voltage corresponding to the change of the threshold voltage of memory cell transistor so that suppress this change.

In addition, compare with the situation of grid width broad, under the narrower situation of grid width, the bigger tendency of change degree that has threshold voltage, also depend on the grid width of access transistor and driving transistors, but it is generally acknowledged, if the access transistor that the grid width of drop-down unit transistor (size) surpasses memory cell with and/or 2 times of the grid width of driving transistors, then the influence of the threshold voltage of the memory cell transistor change degree that is reflected in unit transistor diminishes, and is preferably 2 times as the upper limit of size ratio.

In addition, under the situation that the grid length of accessed memory cells transistor and driving transistors is equal to each other, the grid width of the unit transistor of drop down element also can be set between access transistor and the drive transistor gate width.In addition, viewpoint from static noise margin, with access transistor (NQ3, NQ4) grid width is compared, usually with driving transistors (NQ1, NQ2) grid width set big (under the identical situation of grid length), the grid width of drop-down unit transistor (size) also can be set between the grid width of these access transistors and driving transistors.In this case, the size of pull-down transistor (grid width) is the value near access transistor and both sizes of driving transistors (grid width), can reflect that the voltage of selecting word line is set in the change of the threshold voltage of access transistor and driving transistors.

As mentioned above,,, connect drop down element, can suppress the rising of word line voltage level,, also can not be subjected to the influence of threshold voltage dispersion, stably guarantee to read tolerance limit even under low supply voltage with respect to word line according to second example of the present invention.

[the 3rd example]

Figure 17 is the figure of expression based on the structure of the drop down element PD of the present invention's the 3rd example.In Figure 17, drop down element PD comprises: be connected between word line and the ground connection node and the complementary N-channel MOS transistor NQ25 that writes indicator signal/WE of grid acceptance.The structure of word line driver WDV and word line driver WDV shown in Figure 8 is identical, gives identical reference marks for corresponding part, and omits its detailed description.

Complementary indicator signal/the WE that writes is generated by main control circuit shown in Figure 77, and the one-piece construction of the semiconductor storage of the 3rd example of the present invention is identical with structure shown in Figure 7.

Complementary indicator signal/the WE that writes generates by writing indicator signal WE, becomes the H level when the data readout mode, writes the fashionable L of becoming level in data.

Figure 18 is illustrated in the figure that the signal waveform of fashionable main node was read and write to data when having used drop down element PD shown in Figure 17.When data are read, the indicator signal/WE that writes of complementation is set at the H level, N-channel MOS transistor NQ25 becomes conducting state in drop down element PD.Therefore, the voltage level of being determined by the ratio of the conducting resistance of the N-channel MOS transistor NQ25 of the conducting resistance of the P channel MOS transistor PQ15 of the driving stage among the word line driver WDV and this drop-down usefulness drives selection word line WL.Under the lower situation of the voltage of word line WL, bit line BL shown in Figure 7 and/BL is last to produce potential change corresponding to the storage data of memory cell, inner memory node ND1 or the voltage level of ND2 also rise by row electric current (bit line current), nonetheless, also can fully guarantee to read tolerance limit (static noise margin SNM), and stably keep data.Can not produce data corruption and carry out reading of data.When this is read tolerance limit guarantee identical with the situation of first and second example.

On the other hand, write fashionablely in data, the indicator signal/WE that writes of complementation is set at the L level, drop-downly become nonconducting state with N-channel MOS transistor NQ25.Therefore, in this case, word line WL is when selecting, and the P channel MOS transistor PQ15 of the charging usefulness by word line driver WDV is driven to supply voltage VDD level.Therefore, the voltage level of writing fashionable word line WL in data raises, and writes tolerance limit and raises, and can carry out writing of data at high speed.

Therefore, write fashionablely in data,, be set to mains voltage level, and can prevent to write fashionable tolerance limit and worsen, take place data and write bad thereby data can be write fashionable word line voltage level by stopping the drop-down action of drop down element PD.Thus, no matter read and write fashionable, can both fully guarantee tolerance limit, be not subjected to the influence of the threshold voltage dispersion of memory cell, stably carry out writing/reading of data in data.

In addition, in this drop down element PD shown in Figure 17, (NQ1, electrical resistance characteristic NQ2) is identical, and the second satisfied and previous example is drop-down with MOS transistor NQ20 or the identical condition of NQ21 also to form MOS transistor NQ25 and memory cell driving transistors.

As mentioned above, according to the 3rd example of the present invention, in drop down element, constitute and when data write pattern, stop this pulldown function, can suppress the reduction that data are write the voltage level of fashionable selection word line, in addition, when data are read, can reduce the voltage level of selecting word line, that can fully guarantee data reads and writes tolerance limit, stably carries out writing/reading of data.

In addition, as drop down element, the structure of the drop down element shown in second example before can priority of use.Replace word line or supply voltage that the control signal transmission line is coupled on the transistorized grid of drop down element.

[the 4th example]

Figure 19 is the figure of the pith structure of the summary semiconductor storage of representing the 4th example of the present invention.In Figure 19, memory cell array 1 is split into a plurality of row piece CBK0-CBKk.In row piece CBK0-CBKk, memory cell MC is arranged in rectangular, and disposes sub-word line corresponding to memory lines.In Figure 19, in row piece CBK0, corresponding to each column of memory cells, dispose sub-word line SWL00, SWL10 ... SWLj0, in row piece CBK1, corresponding to each column of memory cells, dispose sub-word line SWL01, SWL11 ... SWLj1.In row piece CBKk, corresponding to column of memory cells, dispose sub-word line SWL0k, SWL1k ... SWLjk.

To the column of memory cells of these row pieces CBK0-CBKk dispose jointly main word line MWL0, MWL1 ... MWLj.Main word line MWL0-MWLj is driven to selection mode according to the row selection signal from row decoding circuit 20 (corresponding to the row decoder of Fig. 1).

Corresponding to each sub-word line SWL00-SWLjk, sub word line driver SD00-SDjk is set.(i=0～j, h=0～k) is driven into selection mode according to the signal potential on the main word line MWLi of correspondence and block selection signal BSh with the sub-word line SWLih of correspondence to sub word line driver SDih.

Block selection signal BS0-BSk generates according to column address signal CA from piece decoding circuit 22 (being included in the column select circuit shown in Figure 1 4), and the block selection signal that appointment is comprised the row piece of selecting row is driven into selection mode (H level).

In addition, corresponding to each sub-word line SWL00-SWLjk, drop down element PD00-PDjk is set.These drop down element PD00-PDjk is made of N-channel MOS transistor (NQ25).This drop down element PD00-PDjk according to row block selection signal BS0-BSk with write indicator signal WE, will select the drop down element of row piece to write the fashionable nonconducting state that is set in data.That is, corresponding to each row piece CBK0-CBKk, drop-down control gate G0-Gk is set.Drop-down control gate G0-Gk, accept block selection signal BS0-BSk and accept to write indicator signal WE at first input end at second input end, at the block selection signal BSi of correspondence is the H level of selection mode and to write indicator signal WE be expression when writing the H level of pattern, output L level signal.

The output signal of drop-down control gate G0 offer jointly row piece CBK0 drop down element PD00, PD01 ..., PD0j control gate, the output signal of drop-down control gate G1 offer jointly row piece CBK1 drop down element PD01, PD11 ..., PDj1 control gate.The output signal of drop-down control gate Gk offers the control gate of the drop down element PD0k-PDjk of row piece CBKk jointly.

When data were read, writing indicator signal WE was the L level, and the output signal of drop-down control gate G0-Gk is the H level, and drop down element PD00-PDjk is irrelevant with the state of block selection signal BS0-BSk, is in conducting state.On the other hand, when writing indicator signal WE and be the H level, drop-down control gate G0-Gk moves as phase inverter, selects the output signal of the drop-down control gate Gi of row piece correspondence to become the L level, and selecting the drop down element of row piece is nonconducting state.In remaining non-selection row piece, block selection signal is the nonselection mode of L level, and the output signal of corresponding drop-down control gate is the H level, and drop down element is kept conducting state, corresponding sub-word line maintains ground voltage level (in non-selection piece, sub-word line is a nonselection mode).

Figure 20 is the figure of the structure of expression sub word line driver shown in Figure 19 and drop down element.In Figure 20, schematically illustrated sub word line driver SD and the drop down element PD that disposes corresponding to a sub-word line SWL.

In Figure 20, sub word line driver SD comprises the NAND circuit 25 of the signal accepted on the corresponding main word line MWL and row block selection signal BS (any one among the BS0-BSk) and constitutes the P channel MOS transistor PQ15 and the N-channel MOS transistor NQ15 of CMOS phase inverter of the output signal of this NAND circuit 25 of counter-rotating.

Drop down element PD accepts the N-channel MOS transistor NQ25 of the signal of self-corresponding drop-down control gate/(BSWE) to constitute by its grid.

As shown in Figure 20, by sub word line driver SD, sub-word line SWL in correspondence is driven under the situation of H level, MOS transistor PQ15 and NQ25 all are in conducting state, and the voltage level of sub-word line SWL maintains the voltage level that the ratio by the conducting resistance of these MOS transistor PQ15 and NQ25 is determined.

Figure 21 is the figure that the data of the semiconductor storage of expression the present invention the 4th example are write the signal waveform of fashionable main node.Below with reference to signal waveforms shown in Figure 21, illustrate that the data of Figure 19 and structure shown in Figure 20 are write fashionable action.

Data are write fashionable, will write indicator signal WE and be set at the H level.According to the column address signal (CA) that comes from the outside, will be driven into selection mode for the block selection signal BS that comprises the row piece of selecting row, for non-selection piece, block selection signal BS keeps the nonselection mode of L level.

In this non-selection piece, as shown in figure 19, even corresponding main word line MWL is driven to selection mode, the output signal of sub word line driver SD remains the L level, and sub-word line SWL keeps ground voltage level.Therefore, in memory cell, access transistor is kept nonconducting state, bit line BL ,/voltage level of BL (not shown among Figure 19) keeps precharge voltage level.In addition, memory node ND1, the ND2 of the internal node of the memory cell of non-selection row piece also maintains and the corresponding potential level of these storage data, and these voltage levels do not change.

On the other hand, in selecting the row piece, row block selection signal BS is " 1 (a H level) ", and sub word line driver SD according to the current potential of the main word line MWL (any one among the MWL0-MWLj) of correspondence, is driven into selection mode with the sub-word line SWL of correspondence.Select in the row piece at this, the output signal of drop-down control gate (any one among the GiG0-Gk) becomes the L level, and drop down element PD becomes nonconducting state.Therefore.Chooser word line SWL before reaching supply voltage VDD level, charges by the P channel MOS transistor PQ15 that is included in the charging usefulness among the sub word line driver SD.Therefore, data are write fashionable, can fully guarantee to write tolerance limit, according to bit line BL and/current potential that writes of the last appearance of BL sets the memory node ND1 of memory cell inside and the voltage level of ND2 at high speed, and can realize that data at a high speed write.

The voltage level of the sub-word line of the correspondence of non-selection memory unit is a nonselection mode, increases even write tolerance limit, also can prevent to read deterioration in memory cell, realizes that stable data writes.By reducing the number of the memory cell that on a sub-word line, connects as much as possible, carry out data access (writing/read) concurrently for the memory cell that on a sub-word line, connects, thereby can prevent to worsen at the static noise margin of writing fashionable non-selection memory unit.Can carry out stable data writes and reads.

When data were read, writing indicator signal WE was the L level, and the output signal row block selection signal of drop-down control gate G0-GIi is the H level.Therefore, drop down element PD (PD00-PDjk) all is in conducting state and the second and the 3rd example is same, and the voltage level of chooser word line is set at ratio corresponding voltage levels with the conducting resistance of MOS transistor PQ15 and NQ25.That is, adjust the voltage level of chooser word line corresponding to the threshold voltage characteristic of memory cell driving transistors.Under the threshold voltage condition with higher of memory cell driving transistors, the voltage level of sub-word line and the conducting resistance of drop down element raise.Under this state, owing to fully guaranteed static noise margin SNM, the voltage level of sub-word line raises.On the other hand, under the lower situation of the threshold voltage of memory cell driving transistors, it is big that the driving force of its drain current Ids becomes, and static noise margin SNM reduces.In this case, reduce the voltage level (the drop down element conducting resistance diminishes) of chooser word line, improve static noise margin (by adjusting the amount of drive current of access transistor).

In addition, as drop-down control gate, can use the drop down element of in second example, using.

As mentioned above, according to the 4th example of the present invention, memory cell array is divided into a plurality of row pieces, in selecting the row piece, carry out writing/reading of data, keeping sub-word line in non-selection row piece is inactive state (nonselection mode), can prevent because the deterioration of the static noise margin of the memory cell of non-selection row causes data corruption.Thus, even under the more situation of columns, discrete for the threshold voltage of memory cell also can stably have reading and writing of tolerance limit.

[the 5th example]

Figure 22 is the figure of expression pith structure of the semiconductor storage of the 5th example according to the present invention.In Figure 22, the expression structure partly that is associated with a word line WL.Word line WL is driven to selection/nonselection mode by word line driver WDV.This word line driver WDV in its driving stage, comprises the P channel MOS transistor PQ15 and the N-channel MOS transistor NQ15 that constitute the CMOS phase inverter.

On word line WL, common connected storage unit MC and dummy cell DMC.Memory cell MC comprises: constitute P channel MOS transistor PQ1, the PQ2 of trigger and N-channel MOS transistor NQ1 and NQ2 and according to the current potential of word line WL with memory node ND1 and ND2 and bit line BL and/ access transistor NQ3 and NQ4 that BL is coupled.

Dummy cell DMC comprises: respectively with the corresponding respectively P channel MOS transistor PT1 of the P channel MOS transistor PQ1 of memory cell MC and PQ2 and PT2, with the corresponding N-channel MOS transistor NT1 of the N-channel MOS transistor NQ1 of memory cell MC and NQ2 and NT2, distinguish corresponding N-channel MOS transistor DT1 and DT2 with access transistor NQ3 and the NQ4 of memory cell MC.

Memory cell MC and dummy cell DMC, wiring connects different, but the transistorized layout of its inside is identical.That is in dummy cell DMC, MOS transistor PT1, PT2, NT1 and NT2 have the layout identical with MOS transistor PQ1, PQ2, NQ1 and the NQ2 of memory cell MC, connect in an identical manner in addition.

That is, in dummy cell DMC, with access transistor NQ3 and corresponding N-channel MOS transistor DT1 and the DT2 of NQ4 of memory cell MC, its grid and first node (drain node) are coupled with word line WL respectively, Section Point (source node) and the coupling of ground connection node.Therefore, in dummy cell DMC, N-channel MOS transistor DT1 and DT2 separate from node DN1 and the DN2 corresponding with the memory node ND1 of memory cell MC and ND2.The transistorized layout of the MOS transistor DT1 of dummy cell DMC and DT2, identical with the layout of the access transistor NQ3 of memory cell MC and NQ4, Bu Xian connected mode difference only.Therefore, the electrical specification of the access transistor NQ3 of the electrical specification of the MOS transistor DT1 of this dummy cell DMC and DT2 and memory cell MC and NQ4 is identical substantially.

In this structure shown in Figure 22, the MOS transistor DT1 of dummy cell DMC and DT2 are as the drop down element effect.The driving transistors NQ1 of the MOS transistor DT1 of dummy cell DMC and DT2 and memory cell MC and NQ2 are near configuration, dispersing of Fabrication parameter, produce equally among both at memory cell and dummy cell, the electrical specification (threshold voltage characteristic) of the MOS transistor DT1 of the drop-down usefulness of the discrete and dummy cell of the electrical specification (threshold voltage characteristic) of the driving transistors NQ1 of memory cell MC and NQ2 and DT2 discrete can be set at identical, can be in the threshold voltage of the pull-down transistor DT1 of dummy cell DMC and DT2 the change of the transistor parameter of reflection memory cell, correspondingly, the voltage level of selecting word line can be set at the voltage level of proofreading and correct according to the change of the threshold voltage of memory cell.

If the ratio of the synthetic conducting resistance Rn of the conducting resistance Rp of the P channel MOS transistor PQ15 among this word line driver WDV and the N-channel MOS transistor DT1 of dummy cell DMC and DT2 is 1: 23 for example.In this case, if supply voltage VDD is 1.2V, then the voltage VWL the during selection mode of word line WL can be represented by the formula.

1.2·23/24＝1.15V

Therefore, can in selecting word line WL, produce the voltage drop of about 50mV.Current driving capability corresponding to MOS transistor PQ15 and MOS transistor DT1 and DT2 is set at suitable value with channel width W, thereby can set these conducting resistance Rp and synthetic conducting resistance Rn so that the intrinsic standoff ratio of realizing wishing.For example, if the conducting resistance Rp of MOS transistor PQ15 is 1.1K Ω, then the synthetic conducting resistance Rn of N-channel MOS transistor DT1 and DT2 is 25K Ω.Under the situation of this resistance value, the perforation electric current amount that flows to the ground connection node from the power supply node of word line driver WDV via the MOS transistor DT1 and the DT2 of drop-down usefulness by word line WL be 1.2/ (26.1 * 10^3), about 44 μ A.This perforation electric current only flows through the increase of the electric current of can fully inhibiting consumption during word line is selected in the word line of selecting row.

Figure 23 be summarily represent as should drop down element shown in Figure 22 the figure of the current potential of word line WL under the situation of the transistor DT1 of use dummy cell DMC and DT2.Under the threshold voltage vt h condition with higher of the driven MOS transistor NQ1 of memory cell MC and NQ2, correspondingly in dummy cell DMC, the threshold voltage of MOS transistor DT1 and DT2 also rises, and conducting resistance (electricity is led) rises, and their drain current Ids descends.In memory cell MC, static noise margin SNM raises, and write diagnostics worsens.In this case, in dummy cell DMC, the conducting resistance of MOS transistor DT1 and DT2 increases, and selects the voltage level of word line WL to raise, and guarantees the tolerance limit that writes of memory cell MC.

Under the situation of driving with the threshold voltage vt h reduction of N-channel MOS transistor NQ1 and NQ2 of memory cell MC, the write diagnostics of memory cell raises, and static noise margin SNM reduces.In dummy cell DMC, the threshold voltage of MOS transistor DT1 and DT2 also reduces, and correspondingly its drain current rises, and conducting resistance reduces.In this case, select the voltage level of word line WL to reduce, suppress the deterioration of the static noise margin SNM of memory cell MC corresponding to the conducting resistance of this MOS transistor DT1 and DT2.

Therefore, by use the transistor DT1 and the DT2 that are equivalent to access transistor of this dummy cell DMC as drop down element, the voltage level of selecting word line WL is adjusted on the ground that can link according to the change of the change of the threshold voltage of the driving transistors of memory cell MC and this threshold voltage automatically, and can stably carry out writing/reading of data.

In this dummy cell DMC, the transistor corresponding with the access transistor of memory cell MC used as pull-down transistor.Therefore, when the influence of the threshold voltage change of the access transistor of memory cell is bigger than the influence of the threshold voltage change of driving transistors, can adjust the selection word line voltage in linkage with the change of the threshold voltage of this access transistor, guarantee to read tolerance limit and write tolerance limit.

In addition, dummy cell DMC has identical layout with memory cell MC, and the access transistor of the correspondence of pull-down transistor and memory cell carries out layout with same size (ratio of grid width and grid length).Therefore, corresponding to the voltage reduction amount of this word line WL, the size of this dummy cell also can be carried out correspondence by identical size ratio with 0.8 to 2 times with second example.

In addition, each a column of memory cells dummy cell DMC of configuration and two pull-down transistors.But the number of this dummy cell can suitably be selected corresponding to the voltage drop amount of word line.

[first modification]

Figure 24 is the figure of dummy cell DMC structure of the modification of expression the present invention the 5th example.Dummy cell DMC shown in Figure 24, textural element is identical with memory cell MC shown in Figure 22.In memory cell MC and dummy cell DMC, transistorized layout is identical, and wiring connects different.That is with access transistor NQ3 and corresponding N-channel MOS transistor DT3 and the DT4 of NQ4 of memory cell MC, first node separately is connected respectively to word line WL, and grid separately is connected to word line WL.The Section Point of these N-channel MOS transistor DT3 and DT4 is connected respectively to internal node DN1 and DN2 and is connected to the ground connection node.

MOS transistor PT1, PT2, NT1 and NT2 MOS transistor PQ1, PQ2, NQ1 and the NQ2 with the trigger that constitutes memory cell MC shown in Figure 22 respectively are corresponding.

In this dummy cell DMC shown in Figure 24, its internal node DN1 and DN2 respectively with the coupling of the Section Point of MOS transistor DT3 and DT4.On the other hand, the high side power supply node of MOS transistor PT1 and PT2 maintains quick condition.

In the structure of this dummy cell DMC shown in Figure 24, MOS transistor DT3 and DT4 also work as drop down element.Node DN1 and DN2 are ground voltage level, the source node that is equivalent to the high side power supply node of MOS transistor PT1 and PT2 is fixed on the level (absolute value of the threshold voltage of supposition MOS transistor PT1 and PT2 is Vthp) of voltage Vthp by MOS transistor PT1 and PT2.

In the syndeton of this dummy cell DMC shown in Figure 24, the influence of the driving transistors NQ1 of memory cell MC and the threshold voltage dispersion of NQ2 appears at too and is disposed near its access with among N-channel MOS transistor NQ3 and the NQ4.Correspondingly, in dummy cell DMC, the MOS transistor DT3 of drop-down usefulness and DT4 also illustrate discrete identical discrete with the threshold voltage of the driving transistors NQ1 of memory cell MC and NQ2, the voltage level of word line WL can be set at the discrete corresponding voltage levels with the threshold voltage of memory cell MC.

In addition, the transistor corresponding with access transistor used as pull-down transistor, can reflect that the selection word line voltage is adjusted in the change of the transistorized threshold voltage of accessed memory cells.In addition, adopt under the situation of size (ratio of grid width and grid length) same structure at accessed memory cells transistor and driving transistors, can will select word line voltage to be set at the voltage level of reflection access transistor and both threshold voltage changes of driving transistors by the pull-down transistor of dummy cell.

Figure 25 is the figure that summarily represents the plane figure of dummy cell DMC shown in Figure 24.In Figure 25, represent the plane figure of memory cell MC in the lump.

In Figure 25, form the zone as transistor unit, dummy cell DMC comprises: the active region AR2 of the P type that forms in the N trap and AR3 and the active region AR1 and the AR4 that form respectively in the P well area of these N trap both sides.Active region AR1-AR4 is respectively formed at the rectangular shape that the Y direction has long limit.

Each end in the both ends of active region AR1 forms contact CT1 and contact/path VC1, forms contact CT2 in the central area of active region AR1.

Extend and form the first polysilicon wire PS at directions X in the mode of crosscut active region AR1 and AR2, in addition,, form the first polysilicon wire PS1 in the mode of crosscut active region AR1 near contact/path VC1.In addition, mode with crosscut active region AR3 and AR4 forms the first polysilicon wire PS3 that extends along directions X in memory cell area, in addition, near path/contact VC2, extend and form the first polysilicon wire PS4 in the mode of crosscut active region AR4 at directions X.The first polysilicon wire PS2 is coupled to active region AR3 by common contact SC2, and active region AR2 is in addition by common contact SC1 and polysilicon wire PS3 coupling.These common contact SC1 and SC2 form contact point unit that connects the active region and the routing cell that extends to polysilicon wire PS2 and PS3 respectively continuously, have the function of contact and wiring by one deck wiring.

In the AR1 of active region, contact CT1 and CT2 interconnect by the first metal line MM1.The first metal line MM1 is the wiring of more leaning on the upper strata than polysilicon wire PS2.Contact CT1 is coupled to the ground wire of supplying with ground voltage VSS.

Mode with this dummy cell of crosscut DMC disposes the 3rd metal line MM3 that extends and constitute word line WL along directions X.Constitute the 3rd metal line MM3 of word line WL, be coupled to polysilicon wire PS1 by path VA1, and be coupled to active region AR1 by path/contact VC1.In addition, the 3rd metal line MM3 is coupled to the first polysilicon wire PS4 by path VA2, and is coupled to active region AR4 by path/contact VC2.

In the AR4 of active region, contact CT5 and CT6 interconnect by the first metal line MM2, and contact CT6 is coupled to the ground connection node.

In active region AR1 and AR4, common and the ground connection node coupling of the transistorized source electrode of the correspondence of memory cell driving transistors and drain electrode, transistor (the DT3 corresponding with the access transistor of memory cell, DT4) grid and drain electrode are connected to word line, its source electrode in addition and the ground connection node be coupled.

Having used the 3rd metal line MM3 as word line WL3, is the cause of using second metal line to be configured because of in the wiring of memory cell internal transmission supply voltage VDD.

The contact CT3 of active region AR2 and AR3 and CT4 are not coupled with the power lead that transmits supply voltage VDD respectively, and become quick condition.

In memory cell MC, also the same with this dummy cell DMC, active region AR12 and AR13 form the long rectangular shape of Y direction in the N well area, in addition, in the P of its both sides well area, form Y direction the active region AR11 and the AR14 of long rectangular shape.Mode with this active region of crosscut AR11 forms polysilicon wire PS11, and this polysilicon wire PS11 is coupled by path VA11 and the 3rd metal line MM3 that forms word line WL.

At the central portion of active region AR11, contact CT18 and first metal line MM11 coupling, this first metal line MM11 is by common contact CS11 and active region AR12 coupling.Contact CT18 is electrically connected the first metal line MM11 and active region AR11, forms the connection of transistor to the interior memory node of memory cell thus.This common contact CS11 is connected to the polysilicon wire PS13 of mode in directions X extends to memory cell MC zone with crosscut active region AR13 and AR14.

In the AR12 of active region, at the contact CT13 that forms in the face of the end of common contact CS11 power supply node, in the AR13 of active region, with the position of contact CT13 mirror image symmetry on form the contact CT14 that accepts supply voltage.In the AR13 of active region, in facing the end regions of contact CT14, form common contact CS12 in addition.On the polysilicon wire PS12 that extends on the directions X, connect common contact CS12 in mode with crosscut active region AR12 and path 11.

This common contact CS12 is connected to the contact CT19 in the middle section that is formed on active region AR14.Contact CT19 is connected electrically to the zone of active region AR14, and by the first metal line MM12, the transistor of another memory node in the configuration memory units connects.

The contact CT15 of active region AR14 upside and bit line/BL coupling, in addition, the contact CT16 that forms on the position relative with contact CT15 is coupled with the ground wire of transmission ground voltage VSS.

For active region AR14, form the polysilicon wire PS14 that extends at directions X in the mode of this active region of crosscut AR14, this polysilicon wire PS14 is connected with the 3rd metal line MM3 that constitutes word line by path Va12.

In this layout shown in Figure 25, in dummy cell DMC, MOS transistor DT1 forms in the AR1 of active region, its grid forms by polysilicon wire PS1, its extrinsic region is connected to WL (the 3rd metal line MM3), and source electrode is coupled by contact CT2 and CT1 and the node of accepting ground voltage VSS.

MOS transistor DT4 forms in the AR4 of active region, and its grid is applied to polysilicon wire PS4, and an one conducting node is connected electrically to the 3rd metal line that forms word line WL by path/contact VC2.In addition, the source node of this MOS transistor DT4 is coupled by contact CT5 and CT6 and ground connection node.

In the formation zone of memory cell MC, in the AR11 of active region, form access transistor NQ3 and driving transistors NQ1, in the AR14 of active region, form access transistor NQ4 and driving transistors NQ2.Common contact SC11 and SC12 are corresponding with memory node ND1 and ND2 respectively.

Therefore, as shown in Figure 25, dummy cell DMC and memory cell MC have same layout, and dispose along directions X adjusting to a line.The first metal line MM1 and MM2 extend and interconnect contact CT1 and CT2 and interconnect contact CT5 and CT6 along the Y direction in the active region in dummy cell DMC.On the other hand, the contact CT18 of this first metal line MM11 and MM1 and common contact SC11 and active region AR11 is coupled in illusory memory cell MC, and interconnects the contact CT19 of common contact SC12 and active region AR14.

The first metal line MM1, MM2, MM11 and MM12 be the bearing of trend difference only, and in same manufacturing process, the first metal line MM11 and the MM12 of these first metal lines MM1, MM2 and memory cell MC form in same operation.

Only in dummy cell DMC, and then, the 3rd metal line MM3 that forms word line WL be connected to the bit line BL of memory cell MC and/the corresponding path in the last contact that is connected of BL/contact VC1 and VC2 on.Therefore, dummy cell DMC and memory cell MC can form with identical layout and in same manufacturing process, in addition, the transistorized configuration direction of this memory cell MC and dummy cell DMC is identical, by the identical unit figure of repeated configuration, thereby use access transistor DT3 and the DT4 of dummy cell DMC, can will have the transistor identical as selecting the word line voltage drop down element to be configured with the memory cell transistor electrical specification.

In addition, dummy cell DMC is identical with memory cell MC layout, can adopt the cloth line procedures identical with memory cell MC, in dummy cell, the word line voltage pull-down transistor is connected and routes on the word line.

In addition, in dummy cell DMC, the P and the transistorized grid of N-channel MOS that constitute phase inverter interconnect, and drain node separates.By interconnect contact CT2 and common contact SC1 with first metal line, and interconnect contact CT5 and common contact SC2, thereby can on node DN1 corresponding and DN2, connect P channel MOS transistor and N-channel MOS transistor drain node with memory node with first metal line.

[second modification]

Figure 26 is the figure of layout of the dummy cell DMC of summary second modification of representing the present invention's the 5th example.The layout of the memory cell MC corresponding with this dummy cell DMC shown in Figure 26, identical with the layout of memory cell MC shown in Figure 25, constitute the 3rd metal line MM3 of word line WL, be equipped on the memory cell MC that follows adjusting to a line configuration on the direction publicly.Therefore, the layout of not shown memory cell in Figure 26.Dummy cell DMC and memory cell adjusting to a line configuration.

In this dummy cell DMC shown in Figure 26, the configuration of active region AR1-AR4, that is transistorized configuration, identical with configuration and the transistorized configuration of active region AR1-AR4 shown in Figure 25.The laying-out and wiring of the distributing of the distributing of the dummy cell DMC that this is shown in Figure 26 and dummy cell DMC shown in Figure 25 is different in the following areas.

That is, in the AR1 of active region, the contact that between polysilicon wire PS1 and PS2, disposes/path VC21 and the 3rd metal line MM3 coupling that is not the formation word line WL of active region AR1.The 3rd metal line MM3 is by path VA1 and polysilicon wire PS1 coupling.Be not coupled word lines, but the node of supply ground voltage VSS is coupled on the bit line contact CT21 of active region AR1.

On the other hand, the contact CT1 of the other end of this active region AR1 maintains quick condition.This contact/path VC21 only is coupling in the 3rd metal line MM3 that constitutes word line, and common contact SC1 and contact/path VC21 is separated.

Among the active region AR4 in another P trap, contact/path the VC22 of configuration also is coupled with the 3rd metal line MM3 in the zone between polysilicon wire PS4 and PS3, and the extrinsic region of active region AR4 central authorities is connected to word line WL by contact/path VC22.The 3rd metal line MM3 is coupled to polysilicon wire PS4 by path VA2 in addition.Contact CT5 separates with the 3rd metal line MM3, and is not with word line but is coupled with the node of supplying with ground voltage VSS.In addition, in the AR4 of this active region, be configured in the contact CT6 of the other end, supply with node from ground voltage and separate, and maintain quick condition.

Common contact SC1 that forms on active region AR2 and AR3 and SC2 are coupled with polysilicon wire PS3 and PS2 respectively.By the first metal line MM31 on polysilicon wire PS2 upper strata, power contact CT3 and common contact SC1 are electrically connected, and in addition, common contact SC2 is by the first metal line MM32 and power contact CT4 electrical couplings.

Other configurations of the dummy cell DMC that this is shown in Figure 26, identical with configuration shown in Figure 25, give identical cross reference number for corresponding part, omit its detailed description.

Figure 27 is the figure of the electrical equivalent circuit of expression dummy cell DMC shown in Figure 26.In Figure 26 and Figure 27, in the AR1 of active region, form N-channel MOS transistor DT5 and NT3.Contact/path VC21 is corresponding with the connected node (common extrinsic region) of MOS transistor DT5 and NT3, with word line WL electrical couplings.The grid of MOS transistor DT5, (by path VA1) and word line WL are coupled.Another conducting node of this MOS transistor DT5 is accepted ground voltage VSS by contact CT21.

In the AR2 of this active region, form P channel MOS transistor PT3, in the AR3 of active region, form P channel MOS transistor PT4.The grid of MOS transistor PT3 and NT3 forms by polysilicon wire PS2, is coupled with common contact SC2.The grid of MOS transistor PT4 and NT4 forms by polysilicon wire PS1, is coupled with common contact SC1.Therefore, the drain node of MOS transistor PT3 and NT3 is separated, and same, the drain node of MOS transistor PT4 and NT4 is separated.The source node of MOS transistor PT3 and PT4 is accepted supply voltage VDD by contact CT3 and CT4.

In the AR4 of active region, form N-channel MOS transistor NT4 and DT6.The connected node of MOS transistor NT4 and DT6 is connected to word line WL by contact/path VC22, and in addition, the grid of MOS transistor DT6 is connected to word line WL.The source node of MOS transistor DT6 is accepted ground voltage VSS by contact CT6.The source node of MOS transistor NT4 maintains quick condition by contact CT5.

In this dummy cell DMC shown in Figure 27, also by have with the access transistor that is configured in memory cell near the MOS transistor DT5 and the DT6 of the identical transistor layout of driving transistors, voltage level that can drop-down word line WL.The grid of MOS transistor NT3 and NT4 maintains supply voltage VDD level, and for through normally on, and source node is a quick condition, so the discharging action of MOS transistor DT5 and DT6 is not exerted an influence.

The grid of MOS transistor PT3 and PT4, source electrode and drain node are connected to power supply node, and maintain nonconducting state usually.The node (source node of transistor NT3 and NT4 maintains word line potential) that in dummy cell DMC, does not have quick condition.

In addition, in dummy cell DMC, replace supply voltage VDD also can supply with ground voltage VSS.In this case, MOS transistor NT3 and NT4 can maintain through normally on, can lower the stray capacitance of word line, and can reduce the influence that actuating speed caused of the selection mode that is driven into word line.

Even this dummy cell DMC transistor shown in Figure 27 is used as the word line drop down element, parameter change during the transistorized manufacturing process of the N-channel MOS of dummy cell DMC and memory cell MC is also identical, can use MOS transistor DT5 and DT6 word line WL to be set at driving N-channel MOS transistor (NQ1, the voltage level of threshold voltage change NQ2) that has reflected memory cell.

In addition, in these first to the 3rd modifications, (access transistor and driving transistors form in same rectangular area the transistor of memory cell, grid width is identical) and the size ratio of the pull-down transistor of dummy cell, identical with second example, can be set at 0.5 to 5 times size ratio, be preferably 0.8 to 2 times.

As mentioned above, according to the 5th example of the present invention, drop down element as word line, use is corresponding to the transistor of the dummy cell of access transistor, with memory cell adjusting to a line and dummy cell with the configuration of identical transistor layout in, can reflect the threshold voltage change of memory cell, can correctly will select word line to be set at the voltage level of the transistorized threshold voltage dispersion of N raceway groove MOD that has reflected memory cell, and can be to revise the selection word line voltage High Precision Automaticly, carry out the reading and writing of data of memory cell.

[the 6th example]

Figure 28 is the figure of pith structure that summarily represents the semiconductor storage of the 6th example according to the present invention.In Figure 28, word line is divided into a plurality of word line group WG0-WGi that comprise word line WL0-WLk respectively.Difference connected storage unit MC on word line WL0-WLk, but shown in Figure 28: a memory cell connected with respect to each word line.In addition, in Figure 28, corresponding to memory cell columns dispose bit line BL ,/BL, not shown among Figure 28 for simplifying picture.

In each word line group WG0-WGi, word line decode/driver WDK0-WDKk is set corresponding to each word line WL0-WLk.In each word line group WG0-WGi, word line decode/driver WDK0-WDKk is decoded row address pre-decode signal XH, XM and XL respectively, and according to its decoded result, when selecting corresponding word lines, it is selection mode that corresponding word lines is driven.Predecoding signal XH, XM and XL provide different combinations to each word line decode/driver, and specify a word line from all word lines.

Word line decode/driver WDK0 comprises the NAND door NG0 of decoding predecoding signal XH, XM and XL and corresponding word lines is driven into the inverter circuit IVG0 of selection mode according to the output signal of NAND door NG0.This inverter circuit IVG0 comprises P channel MOS transistor PQ30, N-channel MOS transistor NQ30.Other word line decode/driver WDK is because have and the structure (predecoding signal XH, XM that is provided and the combination difference of XL) that word line decode/driver WDK0 is identical, so the inner structure of not shown these word line decode/drivers.

In each word line group WG0-WGi, word line decode/driver WDK0-WDKk accepts action power voltage by drive power supply line DPL (DPL0-DPLi) jointly.Drive power supply line DPL0-DPLi by drive power supply line pre-charge circuit DPG0-DPGi, is pre-charged to supply voltage VDD level respectively.Drive power supply line pre-charge circuit DPG0, comprise decoding predecoding signal XH and XM NAND door NG1, counter-rotating NAND door NG1 output signal inverter circuit IVG1, when the output signal of inverter circuit IVG1 is the L level to the P channel MOS transistor PQ32 of the drive power supply line DPL0-DPLk of correspondence transmission supply voltage VDD.Drive power supply line pre-charge circuit DPG0-DPGi is because have identical structure, so the reference marks of giving its textural element to power lead pre-charge circuit DPG0 only.

By the combination of predecoding signal XH and XM, specify a word line group among the word line group WG0-WGi.Therefore, in selecting word line group, drive power supply line pre-charge circuit DPG (any one among the DPG0-DPGi) becomes inactive state (nonconducting state), stops the precharge to the supply voltage VDD level of the drive power supply line DPL (any one of DPL0-DPLi) of correspondence.

Under the situation of carrying out consecutive access or when making word line maintain the long period of selection mode for a long time, for the voltage level that prevents drive power supply line DPL0-DPLk is crossed low and drive power supply line pre-charge circuit DPG0-DPGi is set.

For drive power supply line DPL0-DPLi, level shifter LSF0-LSF1 is set.Level shifter LSF0-LSF1 respectively with the lower voltage limit clamping of the drive power supply line DPL0-DPLi of correspondence at voltage VDD-Vthp level.

Figure 29 is the figure of the routine structure of expression level shifter LSF0-LSF1.Level shifter LSF0-LSF1 is because have identical structure, so represent these level shifters LSF0-LSF1 typically with symbol LSF in Figure 29.

Level shifter LSF is included between power supply node and the node ND5 and connects respectively and its grid is connected to P channel MOS transistor DPQ1 and DPQ2, the N-channel MOS transistor DNQ3 of series connection mutually and the N-channel MOS transistor DNQ4 and the DNQ2 of DNQ1 and series connection mutually of ND5.Node ND7 and ND9 maintain quick condition, and the grid of MOS transistor DNQ1 and DNQ2 is connected to node ND5 jointly.

The absolute value of the threshold voltage of MOS transistor DPQ1 and DPQ2 is Vthp, the voltage level of node ND5, the voltage level that MOS transistor DPQ1 that connects by these diodes and DPQ2 maintain VDD-Vthp, MOS transistor DNQ1 and DNQ2 conducting.The connected node of MOS transistor DNQ3 and DNQ1 separates from node ND5, and in addition, the connected node of MOS transistor DNQ2 and DNQ4 also separates from node ND5.Therefore the node ND7 of quick condition and ND9 maintain ground voltage level by MOS transistor DNQ1 and DNQ2.

This level shifter LSF has the transistor layout identical with the textural element of memory cell MC, the connected mode difference of its wiring.MOS transistor DPQ1 and DPQ2 illustrate the identical change of threshold voltage change with the load transistor of memory cell.Therefore, the voltage VDD-Vthp of drive power supply line DPL maintains the voltage level of the threshold voltage change that is reflected in the load P channel MOS transistor that comprises among the memory cell MC.

Figure 30 is the signal waveforms of the action of this Figure 28 of expression and semiconductor storage shown in Figure 29.Below with reference to Figure 30, the action of Figure 28 and semiconductor storage shown in Figure 29 is described.

In Figure 30, this semiconductor storage and clock signal clk synchronization action, expression and clock signal clk are synchronously supplied with the action form of the address signal that comes from the outside.Clock signal clk can be the clock signal (processor and clock signal are synchronously supplied with address signal to semiconductor storage) of action cycle of the processor of regulation semiconductor storage outside, also can together address signal be supplied to semiconductor storage from ppu and clock signal clk.

When clock signal clk rises, determine the row address signal next from the outside, by not shown pre decoder, determine the state of predecoding signal XH, XM and XL.Now, suppose and selected word line group WG0.In this case, according to the combination of predecoding signal XH and XM, the output signal of NAND door NG1 becomes the L level, and correspondingly, the output signal of phase inverter IVG1 becomes the H level, and MOS transistor PQ32 becomes nonconducting state.Correspondingly, end is for the precharge of the supply voltage VDD of drive power supply line DPL0.At drive power supply line DPL0 is the occasion of supply voltage VDD level, and MOS transistor DPQ1 shown in Figure 29 and DPQ2 are nonconducting states, and therefore, drive power supply line DPL is in quick condition under supply voltage VDD.

In word line decode/driver WDK0-WDKk, carry out decode operation, according to predecoding signal XH, XM and XL, in the word line decode/driver of corresponding selection word line configuration, the output signal of NAND door NG0 becomes the L level, and correspondingly, the output signal of phase inverter IVG0 becomes the H level.Now, suppose and selected word line WL0 that then word line WL0 charges by the MOS transistor PQ30 of word line decode/driver WDK0.The charging current of this word line WL (WL0) is supplied with from drive power supply line DPL (DPL0), and correspondingly, the voltage level of this drive power supply line DPL0 reduces.If the voltage level of this drive power supply line DPL0 reduces, then clamp function work in level shifter LSF0-LSF1 by MOS transistor DPQ1 and DPQ2, maintains the VDD-Vthp level with the voltage level of drive power supply line DPL0.

The absolute value Vthp of the threshold voltage of the load transistor in being included in memory cell MC raises, when its amount of drive current diminishes, improvement is write tolerance limit, and static noise margin SNM worsens.In this case, the voltage clamp level of drive power supply line DPL is the voltage level (Vthp big) lower than supply voltage VDD, selects the voltage level of word line WL0 to become the bigger low voltage level of reduction amount, improves the static noise margin of memory cell.

On the other hand, under the lower situation of the absolute value Vthp of the threshold voltage of the load mos transistor of memory cell MC, its amount of drive current increases, and static noise margin SNM is enhanced, and worsens (tolerance limit that writes of data reduces) and write tolerance limit.In this case, the clamp level of drive power supply line DPL is voltage VDD-Vthp, so the reduction amount is little, the voltage level of selection word line WL0 becomes the voltage level near supply voltage VDD, improves writing tolerance limit.

Therefore, select the voltage level of word line, can adjust automatically along with the change of the threshold voltage vt hp of the load mos transistor of memory cell, and can stablize and correctly carry out writing and reading of data.

Especially,, use transistor with transistor layout identical with memory cell as level shifter, can with threshold voltage change correctly the carrying out adjustment of word line voltage level of the load mos transistor of memory cell with linking.

In addition, be included in the number of the word line WL0-WLk among this word line group WG0-WGi respectively, can be according to the bit line of predecoding signal and suitably decision.

In addition, with the number of the level shifter LSF of drive power supply line coupling, as long as the electric current can supply with the driving of a word line time, the transistorized size according to level shifter is set at suitable value with this number.

[first modification]

Figure 31 is the figure of structure of modification of array element of the semiconductor device of expression the present invention the 6th example.In Figure 31, word line forms the hierarchy of main word line and sub-word line.Main word line is divided into the main word line group MWG that comprises a plurality of main word lines respectively.In Figure 31, the schematically illustrated main word line group MG1 that comprises the main word line group MWG0 of main word line MWL0-MWLi and comprise main word line MWLi+1-MWLj.

Corresponding respectively with main word line MWL0-MWLi and MWLi+1-MWLj, main word line drivers/decoders MWDV0-MWDVi, MWDVi+1-MWDVj are set.By these main word line drivers/decoders MWDV0-MWDVj ..., a main word line is driven into selection mode.

Memory cell array is split into row piece CBK0-CBKk.Corresponding respectively with main word line MWL0-MWLj, sub-word line SWL is set in each row piece.In Figure 31, with main word line MWL0 word line SWL00-SWL0k is set accordingly, with main word line MWLi word line SWLi0-SWLik is set accordingly.With main word line MWLi+1 word line SWL (i+1) 0-SWL (i+1) k is set accordingly, sub-word line SWLj0-SWLjk is set accordingly with main word line MWLj.The memory cell MC that on this a little word line SWL00-SWLjk, connects 1 row of respective column piece.

On this a little word line SWL00-SWLjk, sub word line driver SDV00-SDVjk is set respectively.These sub word line drivers SDV00-SDVjk, the signal potential on the main word line MWL (any one among the MWL0-MWLj) of response row block selection signal BS (BS0-BSk) and correspondence is driven into selection mode with the sub-word line of correspondence.

That is sub-word line is configured corresponding to column of memory cells by in each row piece of block selection signal BS0-BSk appointment, in selecting the row piece, the sub-word line corresponding with selecting main word line is driven into selection mode.

In main word line group MWG0-MWG1, drive power supply line pre-charge circuit SDPG is set by each row piece CBK0-CBKk.In Figure 31, in main word line group MWG0, drive power supply line pre-charge circuit SDPG00-SDPG0k is set accordingly respectively with row piece CBK0-CBKk, in main word line group MWD1, drive power supply line pre-charge circuit SDPG10-SDPG1k is set.These drive power supply line pre-charge circuits SDPG00-SDPG1k supplies with action power voltage to the sub word line driver of the row piece of the main word line group of correspondence respectively by sub word line driver power lead SDPL00-SDPL1k.

These sub word line driver power leads SDPL00-SDPL1k has connected level moving meter LSF0-LSF1 respectively.

Concerning the structure of drive power supply line pre-charge circuit SDPG10-SDPG1k, except that further with predecoding signal XH and XM supply with this point of row block selection signal BS (BS0-BSk), all the structure with drive power supply line pre-charge circuit DPG0-DPGk shown in Figure 28 is identical for other.In addition, also the structure with driving demoder/driver WDK-WDKk shown in Figure 28 is identical for main word line drivers/decoders MWDV0-MWDVj.According to predecoding signal XH, XM and XL, main word line drivers/decoders MWDV0-MWDVj is driven into selection mode with the main word line MWL0-MWLj of correspondence.

In addition, level moving meter LSF0-LSF1, its structure also structure with shown in Figure 26 is identical, has the transistorized layout identical with memory cell MC, diode connects the P channel MOS transistor corresponding to load transistor, and with corresponding drive power supply line SDPL00-SDPL1k coupling.

Under the situation of this layering word line structure shown in Figure 31, only in the row piece that comprises the memory cell of selecting row, the sub-word line of correspondence is driven into selection mode, by corresponding word lines drive power supply line pre-charge circuit and level shifter LSF0-LSF1, its voltage level is moved down into the VDD-Vthp level.In non-selection row piece, sub-word line all is in nonselection mode, and in addition, corresponding drive power supply line pre-charge circuit DPG maintains supply voltage VDD level with the drive power supply line SDPL of correspondence respectively.Therefore, writing fashionablely, can fully guarantee the tolerance limit of reading of non-selection memory unit, can not produce the data corruption of non-selection memory unit, can carry out writing of data at high speed.

In addition, can reduce corresponding word lines is that selection mode and bit line are the half selected numbers of selecting the memory cell of state of nonselection mode, and can reduce and write the fashionable tolerance limit of reading owing to the half selected memory cell of selecting state in data and worsen the possibility that the data corruption that causes takes place.

In the structure of layering word line shown in Figure 31, in each row piece, main word line and sub-word line are corresponding one by one.But, also can use a plurality of sub-word lines and a structure that main word line is corresponding, sub word line driver is driven into corresponding sub-word line according to the signal on predecoding signal (XL) and the main word line selection mode in each row piece.

[second modification]

Figure 32 is the figure of the memory array cell structure of summary second modification of representing the present invention's the 6th example.In Figure 32, memory cell array 1 comprises the word line voltage adjustment unit 52 that memory cell MC is arranged in rectangular normal memory array 50, adjusts the selection voltage level of word line WL.Word line voltage adjustment unit 52 comprises the word line voltage of the configuration corresponding to each column of memory cells (word line) and adjusts circuit 58.On word line WL, connect the memory cell of each corresponding row.

Word line voltage is adjusted circuit 58 and memory cell MC adjusting to a line configuration, its structure will describe in detail in the back, have the transistor arrangement identical, connect by the wiring of changing its inside, thereby the function of the voltage level of word line is adjusted in realization with memory cell MC.

Corresponding to each word line WL, be provided with according to the word line driver 56 that corresponding word lines is driven into selection mode from the word line selection signal of row decoder 54.This word line WL, number (for example from 16 to 64 word lines (WL)) grouping according to the rules, corresponding to each word line group WG, configuration driven device power lead DPLC.This drive power supply line DPLC, by each word line group WG coupled in common to the clamp power lead DPLA and the DPLB that are disposed on the word line voltage adjustment unit.Clamp power lead DPLA and DPLB and drive power supply line DPLC form the loop shape by each word line group WG, supply with action power voltage to the word line driver 56 of corresponding word lines group.Clamp power lead DPLA and DPLB, as an example, adopt and bit line BL and/BL forms with the wiring of layer, use to have the voltage level of drive power supply line DPLC is clamped at voltage VDD-Vthp level with the word line voltage adjustment circuit 58 of memory cell MC same structure (transistor arrangement).

Between word line group WG, trap potential power supply unit TAP is set, supply with the trap bias voltage to the well area of each memory cell MC of configuration and word line voltage adjustment circuit 58.Trap potential power supply unit TAP supplies with the trap voltage of prescribed voltage level respectively to the N trap of the P channel MOS transistor (load transistor) that forms memory cell MC and the P well area that forms N-channel MOS transistor (access transistor and driving transistors).

Figure 33 is the figure that expression word line voltage shown in Figure 32 is adjusted the structure of circuit 58.In Figure 33, word line voltage is adjusted circuit 58 and is comprised: the P channel MOS transistor PQ30 of connection and its grid and clamp power lead DPLA and DPLB coupling between power supply node and clamp power lead DPLA, the P channel MOS transistor PQ31 of connection and its grid and clamp power lead DPLA and DPLB coupling between power supply node and clamp power lead DPLB, the N-channel MOS transistor NQ31 of connection and its grid and clamp power lead DPLA and DPLB coupling between node ND30 and ground connection node, the N-channel MOS transistor NQ32 of connection and its grid and clamp power lead DPLA and DPLB coupling between node ND31 and ground connection node, its first conducting node is connected the N-channel MOS transistor NQ33 of word line WL with node ND30 coupling and its grid, with and the first conducting node is connected with node ND31 and its grid is connected to the N-channel MOS transistor NQ34 of word line WL.

MOS transistor NQ33 and the NQ34 second conducting node separately maintains quick condition (open-circuit condition).In memory cell MC, the transistorized second conducting node corresponding with MOS transistor NQ33 and NQ34 respectively with bit line BL and/BL coupling.

The structure of the electrical equivalent circuit of memory cell MC and memory cell MC shown in Figure 2 is identical.Word line voltage shown in Figure 33 is adjusted circuit 58 and is disposed in line direction adjusting to a line with memory cell MC.

Adjust in the structure of circuit 58 at this word line voltage shown in Figure 33, MOS transistor PQ30 and PQ31, with the diode mode action, with the lower voltage limit level clamping of clamp power lead DPLA and DPLB at the VDD-Vthp level.Vthp is the absolute value of the threshold voltage of MOS transistor pQ30 and PQ31.

MOS transistor NQ31 and NQ32 by the voltage of these clamp power lead DPLA and DPLB, are in the state of conducting usually, and node ND30 and ND31 are maintained ground voltage level.MOS transistor NQ33 and NQ34, voltage level corresponding to word line WL optionally becomes conducting state, and with memory cell in and bit line BL and/ the second conducting node that the node of BL coupling is suitable is in quick condition (open state), in addition, node ND30 and ND31 separate from clamp power lead DPLA and DPLB, and the conduction/non-conduction state of these MOS transistor NQ33 and NQ34 does not influence the clamping voltage level of clamp power lead DPLA and DPLB.

The grid capacitance conduct of MOS transistor NQ33 and NQ34 is worked to the load capacitance of the dummy cell of word line WL.As shown in figure 33, the transistorized wiring identical (with reference to Fig. 2) of the electrical equivalent circuit of word line voltage adjustment circuit 58 and the transistorized electrical equivalent circuit of memory cell MC, the syndeton difference of internal wiring.

This word line voltage shown in Figure 33 is adjusted the structure of circuit, and is identical with the structure of level shifter shown in Figure 29, and it is different that this point of two clamp power leads of clamp power lead DPLA and DPLB only is set.

Figure 34 is the figure of the structure of expression word line driver 56 shown in Figure 32.In Figure 34, word line driver 56 comprises P channel MOS transistor PQ40 and the NQ40 that constitutes the CMOS phase inverter.The source node of MOS transistor PQ40 and drive power supply line DPLC coupling.These MOS transistor PQ40 and NQ40 according to the word line selection signal from row decoder shown in Figure 32, when selecting word line WL, are driven into the voltage (the clamping voltage level on the clamp power lead) on the drive power supply line DPLC.

Memory cell MC has distributing and the transistor arrangement identical with memory cell MC shown in Figure 25, and word line voltage is adjusted circuit 58, and its transistor arrangement is also identical with memory cell MC.Therefore, memory cell MC and word line voltage are adjusted the transistor arrangement of circuit 58 in the line direction repeated configuration.The current supply power of the clamping transistor that the diode of word line voltage adjustment circuit 58 connects is identical with the load transistor of memory cell.But, dispose the word line voltage-regulating circuit accordingly with the word line that is included among the word line group WG, adjust the voltage level of word line driving power supply line concurrently, when selecting word line, in the corresponding word lines group, only a word line is driven into selection mode, can will selects word line to be driven into voltage VDD-Vthp level fully at high speed.

Memory cell is identical with the transistor arrangement that word line voltage is adjusted circuit, and below the explanation word line voltage is adjusted the transistor arrangement and the distributing of circuit 58.Memory cell MC and word line voltage are adjusted the transistorized allocation position relation of circuit 58, with previous identical in the configuration of memory cell shown in Figure 25 and dummy cell, replace dummy cell and dispose word line voltage-regulating circuit 58.

Figure 35 is the figure that this word line voltage of expression is adjusted the layout of the active region of circuit 58 and first polysilicon wire.In Figure 35, word line voltage is adjusted circuit 58 and is comprised: active region 60b that forms in the N trap and 60c, the active region 60a and the 60d that form in the P well area of N trap both sides.Active region 60a-60d forms the long rectangular shape of Y direction respectively.

At the two ends of the Y of active region 60a direction, form bit line contact 64c and ground voltage contact 64b respectively.Form polysilicon wire 62a in mode along this active region of directions X crosscut 60a.On this polysilicon wire 62a,, form word line contact 64a in one end thereof.

For active region 60b, form power supply respectively at its two ends with contact 64d and common contact 65a, in the 60c of active region, the downside end formation power supply contact 64e in its Y direction forms common contact 65b in the upper-side area of its Y direction.This common contact 65b and the polysilicon wire 62b that extends on directions X in the mode of crosscut active region 60b and 60a are coupled polysilicon wire 62b and active region 60c electrical couplings.

Common contact 65a and the polysilicon wire 62c that disposes in the mode along directions X crosscut active region 60c and 60d are electrically connected.Like this, active region 60b and polysilicon wire 62c are electrically connected.

In the 60d of active region,, bit line contact 64f and earthing contact 64g are set at the two ends of its Y direction.Form polysilicon wire 62d in mode, this polysilicon wire 62d and the word line contact 64d electrical couplings that in word line voltage is adjusted the borderline region of circuit 58, forms along directions X crosscut active region 60d.

This word line voltage shown in Figure 35 is adjusted the transistor arrangement of circuit 58 and the configuration of door, and for memory cell MC too, the transistor arrangement that this is shown in Figure 35 is along the shape repeated configuration of directions X with the mirror image symmetry.Therefore, the word line voltage of directions X is adjusted circuit 58 and is identical about the transistor arrangement and the wiring of the Y direction of memory cell MC, can the layout figure of the memory cell in the memory cell array not exerted an influence, can dispose word line voltage-regulating circuit 58 and memory cell MC.In addition, adjust circuit 58 and memory cell MC because form word line voltage, so can set identically with each transistorized electrical specification (making by manufacturing process under the same conditions) that word line voltage is adjusted circuit 58 the transistorized electrical specification of memory cell MC with identical transistor arrangement.

Figure 36 is the figure of the distributing on the transistor arrangement wiring upper strata shown in the summary table diagrammatic sketch 35.In Figure 36, the layout and the path that is connected this ground floor metal line of expression ground floor metal line.In addition, in Figure 36, give identical cross reference number, and omit its detailed description for the contact identical with contact shown in Figure 35.

For adjusting the word line contact 64a that disposes in the borderline region of circuit 58, be provided with the first metal line 70a of long rectangular shape of Y direction at word line voltage.On this first metal line 70a, the mode that overlaps with word line contact 64a with its part forms path 72b.

For earthy contact 64b, form the first metal line 70b of the elongated rectangular shape of directions X.In the end of this first metal line 70b, be formed for connecting the path 72a of ground wire.

With respect to the contact 64c that the bottom of active region 60a shown in Figure 35 forms, form the first metal line 70c of rectangular shape, and form middle layer with respect to bit line.

With respect to the power supply contact 64d that in N trap active region (the active region 60b of Figure 35), forms, form the first metal line 70d of rectangular shape, with the mode that overlaps with contact 64d with this power supply, formation path 72d on the first metal line 70d.In addition,, form the first metal line 70f of rectangular shape,, form path 72e in the mode that overlaps with contact 64e on this first metal line 70f upper strata for the power supply contact 64e of the active region downside of this N trap.With common contact 65a and 65b contacts and extend at directions X, form the first metal line 70e.Upper strata at this first metal line 70e forms path 72c and 72f.

The first metal line 70e, by with memory cell (MC) in be used to be connected the storage inside node the identical manufacturing process of first metal line form.In memory cell, replace path 72c and 72f, configuration is connected electrically to active region 60a shown in Figure 35 and the contact of 60d respectively, in addition, common contact 65a and 65b electrical separation (with reference to Figure 25).

As shown in figure 36, adjust in the circuit 58 at word line voltage, can use first metal line that is connected usefulness with the memory node of memory cell with the node that the first metal line 70e of layer interconnects the memory node that is equivalent to memory cell inside, realize that diode has connected the distributing of the load transistor of memory cell.

For contact 64f, form the first metal line 70g of rectangular shape, for contact 64g, form the first metal line 70h of long rectangular shape of directions X, in the first metal line 70h, form path 72g in its end.For contact 64d, form the first long metal line 70i of Y direction, form path 72h for this first metal line 70i.In this word line voltage adjustment circuit 58, realize about the point-symmetric distributing of central part.

Figure 37 is the figure of the distributing on expression distributing upper strata shown in Figure 36.In Figure 37,, omit its detailed description also to giving identical cross reference number with the corresponding path of path shown in Figure 36.

In this distributing shown in Figure 37, the second metal line 74a of rectangular shape is set on path 72a upper strata, in the second metal line 74a, alternate path 76a is set in the mode that overlaps with path 72a.

For path 72b, the second metal line 74b of long rectangular shape of Y direction is set, on this second metal line 74b upper strata, the mode that overlaps with path 72b with its part is provided with the 3rd path 76b.For path 72c, the second metal line 74c that extends along the Y direction is set.This second metal line 74c constitutes clamp power lead DPLA, is equivalent to bit line BL in memory cell MC.

For path 72d and 72e, connect the second metal line 74d that extends along the Y direction.Use the supply voltage VDD of this second metal line 74d transmission memory unit.

The second metal line 74e that extends along the Y direction also is set for path 72f.The second metal line 74e constitutes clamp power lead DPLB, constitutes complementary bit lines/BL in memory cell MC.

For path 72h the first metal line 74f of long rectangular shape of Y direction is set, on this first metal line 74f, the mode that overlaps with path 72h with its part is provided with alternate path 76c.For path 72g, the second metal line 74g of rectangular shape is set, on this second metal line 74g, form path 76d in the mode that overlaps with path 72g.

Extend at directions X, the 3rd metal line 80a, 80b and 80c dispose separately.The 3rd metal line 80a is connected to the second metal line 74a by second/the 3rd path 76a.The 3rd metal line 80b is coupled to second metal line 74f and the 74b by alternate path 76c and 76b.The 3rd metal line 80b is equivalent to word line WL, and the 3rd metal line 80a is corresponding with the ground wire of transmission ground voltage VSS.

The 3rd metal line 80c is coupled to the second metal line 74g by path 76d, transmission ground voltage VSS.

Transmit ground voltage VSS by second/the 3rd path 76a and 76d to the second metal line 74a and 74g, can prevent the power lead 74d of transmission supply voltage VDD in the memory cell and the conflict of ground wire, thus transmission ground voltage and supply voltage.

In this structure shown in Figure 37, except that this point of this path 72c and 72f was not set, the distributing that word line voltage is adjusted circuit 58 was identical with the distributing of memory cell MC.Thus, the 3rd metal line 80b, ground wire and the 3rd metal line 80a of constituting word line WL and 80c are extended accordingly continuously along directions X and column of memory cells.

Therefore, arrive shown in Figure 37 as this Figure 35, use the transistor arrangement of memory cell MC, can use identical in fact distributing to dispose word line voltage-regulating circuit 58, and the repeated configuration transistor arrangement identical with memory cell MC, can use the homophase wiring to dispose bit line and clamp power lead in addition with identical distributing, can not influence the distributing of memory cell array, and the mains voltage level of word line driver is clamped at the VDD-Vthp level, change corresponding to the threshold voltage of the load transistor of memory cell and adjust the voltage level of selecting word line.

In addition, level shifter LSF disposes transistor with the layout identical with memory cell MC.Constitute the size ratio of load transistor of the correspondence of the transistor of this level shifter and memory cell, also can constitute equally from 0.8 times to 2 times scope with second example.

As mentioned above, according to the 6th example of the present invention, in order to adjust the voltage level of selecting word line voltage, use has the word line voltage of transistor arrangement identical with memory cell and same distributing and adjusts circuit or level shifter, can not produce baneful influence, can dispose the word line voltage-regulating circuit expeditiously the distributing of memory cell array.

In addition, use the level shifter or the word line voltage of the transistor arrangement identical to adjust circuit with memory cell, can be corresponding to the transistorized electrical specification of memory cell, correctly reflect electrical specification discrete of memory cell transistor, adjust and select word line voltage level.

[the 7th example]

Figure 38 is the integrally-built figure of the summary semiconductor storage of representing the 7th example according to the present invention.The semiconductor storage that this is shown in Figure 38, the structure with semiconductor storage shown in Figure 7 is different in the following areas.

That is, for the drop down element PD that each word line WL0-WLn is provided with, be provided for adjusting the word line voltage adjustment circuit 100 of the transistor unit number of these drop down element PD under conducting state.In drop down element PD, as illustrated in second example formerly, a plurality of transistor units are coupled with corresponding word lines respectively in parallel.Adjust the number of the transistor unit that is in conducting state according to the control signal group SMG that adjusts the static noise margin adjustment usefulness of circuit 100 from word line voltage.Thus, the voltage level of the selection word line when the design phase, optimization was read.In addition, when product is made, corresponding to the characteristic of memory cell, adjust the number of the pull-down transistor element that is in conducting state, the characteristic of compensation drop down element is discrete, will select word line voltage level to be set at optimized level.

In addition, corresponding to each memory cell columns, unit power-supply wiring PVLA is set, this unit power-supply wiring PVLA adjusts its voltage level by writing auxiliary array power circuit 108 with the unit of classifying as respectively.Unit power-supply wiring PVLA as shown structure in the back, comprising: to memory cell transmit high side supply voltage VDD the unit power lead, be used to reduce the decline power lead of the voltage level of unit power lead.

Write auxiliary array power circuit 108,, write the voltage level that the unit power lead (VDD power lead) of row is selected in fashionable reduction, correspondingly, enlarge and write fashionable operation margin in data according to writing indicator signal WE and array selecting signal CSL.Illustrated in second example etc.,, reduce the voltage level of selecting word line as the front, the driving force of auxiliary transistor is diminished, guarantee to read tolerance limit by reading the drop down element PD of auxiliary usefulness.In this case, by mains voltage level, might reduce writing tolerance limit.In order to suppress the reduction that this writes tolerance limit, reduce the voltage level of unit power lead (VDD power lead) a little, reduce the ability that latchs of memory cell MC, expansion writes tolerance limit.Thus, stable and carry out data reliably at a high speed and write and read.

So to selecting row and be the memory cell of non-selection row, the voltage level of unit power lead reduces, and the driving force of access transistor reduces, and fully guarantees to read tolerance limit.For being non-selection row and being the memory cell of selecting row that access transistor is a nonconducting state, even high side unit supply voltage reduces, also can stably keep data.

Figure 39 A and Figure 39 B are the figure of the routine structure of expression drop down element PD shown in Figure 38 and word line driver WDV.In Figure 39 A, word line driver WDV corresponds respectively to each word line WL0-WLn and is provided with, and according to word line selection signal (decoded signal) corresponding word lines is driven into selection mode.

These word line drivers WDV has identical structure, so in Figure 39 A, give reference marks to the textural element of the word line driver WDV that is provided with respect to word line WL0.Word line driver WDV comprises according to word line selection signal to the P channel MOS transistor PQ15 of corresponding word lines (WL0) supply line voltage VDD, make the N-channel MOS transistor NQ15 of corresponding word lines (WL0) to the ground voltage level discharge according to word line selection signal.

Corresponding to bit line BL and/cross unit of BL and word line WL0-WLn comes configuration memory units MC.For memory cell MC, each memory cell also has same configuration, schematically shows the structure of the memory cell MC that is connected to word line WL0.Memory cell MC, comprise by the trigger FF that constitutes of anti-phase latch of storage data, signal on the response corresponding word lines (WL0) make inner memory node be connected to bit line BL and/the access transistor ATr of BL.

With respect to and drop down element PD that be provided with corresponding, because also have identical structure, so give reference marks in Figure 39 A, for the textural element of the drop down element PD that is provided with respect to word line WL0 with each word line WL0-WLn.Drop down element PD, comprise optionally conducting according to drop-down control signal LSM, make pull-down transistor DTra that corresponding word lines and ground connection node be coupled during conducting, according to drop-down control signal LSM＜0 optionally conducting, make the pull-down transistor DTrb of corresponding word lines and ground connection node coupling during conducting, according to drop-down control signal SM＜1 make the pull-down transistor DTrc of corresponding word lines (WL0) and the coupling of ground connection node when optionally conducting, conducting.

These pull-down transistors DTra-DTrc is made of the doublet of threshold voltage characteristic (identical layout) transistor (replica transistor) identical with the access transistor ATr of memory cell MC respectively.In Figure 39 A, with pull-down transistor DTra and DTrb respectively by 4 duplicate that access transistor ATr constitutes, pull-down transistor DTrc duplicates the situation that access transistor ATr constitutes by 8 and illustrates as an example.

Figure 39 B is the figure of pull-down transistor DTra-DTrc (representing with the DTr) structure shown in this Figure 39 A of expression.In Figure 39 B, (DTra, DTrb DTrc), are included in a plurality of unit transistors (duplicating access transistor) UATr in parallel between word line WL and the ground connection node to pull-down transistor DTr.Unit transistor UATr has the layout identical with the access transistor ATr of memory cell MC, and is corresponding with each word line, is configured with gate pitch and the grid-contact distance identical with the access transistor ATr of memory cell MC.Layout about this pull-down transistor will be elaborated in the back.

These unit transistors UATr, k are arranged in parallel, and become parallel conducting state according to control signal SM (LSM, SM＜0〉and SM＜1 〉) respectively.If supposing the conducting resistance of unit transistor is Rn, then the synthetic conducting resistance of k unit transistor UATr is Rn/k.Therefore,, can adjust the resistance ratio with the conducting resistance of the PQ15 that pulls up transistor of word line driver WDV by set the number of the unit transistor UATr be in conducting state according to control signal, correspondingly, voltage level that can the optimization selection word line.

Shown in this Figure 39 A, in drop down element PD, by constituting pull-down transistor DTr by having the transistor (duplicating access transistor) identical with the access transistor ATr layout of memory cell MC, thereby the transistor parameter of the threshold voltage characteristic of drop down element PD and conducting resistance etc. can be reflected in transistor parameter discrete of the driving transistors that comprises among the trigger FF by the access transistor ATr of memory cell MC.Therefore, identical with the previous situation of in Figure 22, using dummy cell to form drop down element, can be according to the threshold voltage variation of the access transistor ATr among the memory cell MC, adjust the current potential reduction amount of word line WL0-WLn, and can suppress the reduction of the static noise margin of memory cell MC, enlarge and read tolerance limit.

Particularly, use control signal LSM, SM＜0〉and SM＜1, in drop down element PD, pull-down transistor DTra, DTrb and DTrc optionally are set at conducting state.By this structure, synthetic conducting resistance that can inching drop down element PD.In the design phase, the resistor voltage divider circuit intrinsic standoff ratio that can will be included in the synthetic conducting resistance of the conducting resistance of the P channel MOS transistor PQ15 among the word line driver WDV and drop down element PD according to the characteristic of memory cell MC is set at optimal value.When beginning to produce, in manufacturing process, determine before the manufacturing process, use these control signals to come inching to select the voltage level of word line, make and read and write the tolerance limit optimization.In addition, fixing in the batch process stage of manufacturing process, in the test step when product is made, can adjust word line voltage level corresponding to the tolerance limit of memory cell, and can improve the production rate.

In addition, control signal LSM, SM＜0〉and SM＜1 be included in from word line voltage shown in Figure 38 and adjust the control signal group SMG of circuit 100 supplies.In the test step of semiconductor storage, with control signal LSM, SM＜0〉and SM＜1 being driven into selection mode in turn, test is read tolerance limit and is write characteristic such as tolerance limit.Corresponding to this test result, with control signal LSM, SM＜0〉and SM＜1, for example use fuse program circuit etc. to set its potential level regularly.

In addition, control signal LSM as so-called default value, also can use the structure that is set at selection mode usually.Control signal LSM only one maintain activated state, with control signal SM＜0 and SM＜1 all maintain under the situation of nonselection mode, be in the state of the resistance value maximum of drop down element, be the current potential reduction amount of word line when selecting hour, corresponding to the state of the static noise margin SNM maximum of memory cell MC.SNM diminishes along with static noise margin, and the number of the drop-down unit transistor UATr that becomes conducting state is increased.

Figure 40 is the figure that more specifically represents the pith structure of semiconductor storage shown in Figure 38.In Figure 40, memory cell MCa and the MCb that is configured to 1 row, 2 row represented as the representative of memory cell MC.In word line WLa-WLc, also distinguish connected storage unit MC.In these word lines WLa-WLc, word line driver WDB and drop down element PD are set.Drop down element PD, unit transistor (duplicating access transistor) UATr it is inner by the control signal group SMG shown in Figure 39 A and the 39B optionally is set at conducting state.In Figure 40, in drop down element PD, the not shown unit transistor that maintains nonconducting state.The control signal of control signal group SMG is because be set at mains voltage level, so in Figure 40, the grid that is expressed as the unit transistor UATr of the conducting state in the drop down element PD is connected with power supply node when selecting.

Memory cell MCa is connected to bit line BLa/BLa, memory cell MCb and bit line BLb and/BLb coupling.

Unit power-supply wiring PVLA, comprise unit power lead ARVD corresponding to the configuration of each memory cell columns (ARVDa, ARVDb) and decline power lead DWVD (DWVDa, DWVDb).For memory cell MCa and MCb, unit ground wire ARVS extends configuration at column direction.This unit ground wire ARVS is shared by two adjacent memory cells at line direction.Unit power lead ARVDa and ARVDb are coupled to the high side power supply node VH of memory cell MCa, the MCb of respective column respectively, and have stray capacitance CP0.Decline power lead DWVDa and DWVDb have the stray capacitance CP1 that is produced by its wiring capacitance equally respectively.

Decline power lead DWVDa and DWVDb are by the public connection of per two row.Connect the high side power supply VH node of the memory cell of respective column on unit power lead ARVD, on the other hand, decline power lead DWD is coupled to the ground connection node when reading and when standby, is free of attachment to memory cell.Therefore, the wiring capacitance of unit power lead ARVD, the stray capacitance of the load transistor by memory cell is bigger than the wiring capacitance of decline power lead DWDV.In order to fill up the poor of this wiring capacitance, when the selected cell power lead, reduce its voltage level, a plurality of decline power lead DVDW as a group, are coupled with the unit power lead ARVD that selects row.

Write auxiliary array power circuit 108, write fashionablely in data, regulate the voltage level of this unit power lead by each memory cell columns.That is this writes auxiliary array power circuit 108 and comprises: write the indicator signal WE[n that falls in lines in non-selection] time conducting, make P channel MOS transistor (insulated-gate type field effect transistor) 110a of unit power lead ARVDa and power supply node coupling; Selecting to write the indicator signal WE[n that falls in lines] time conducting, N-channel MOS transistor 111a that unit power lead ARVDa and decline power lead DWVDa and DWVDb are coupled; Write the indicator signal WE[n+1 that falls in lines in non-selection] time conducting, make the P channel MOS transistor 110b of unit power lead ARVDb and power supply node coupling; Selecting to write the indicator signal WE[n+1 that falls in lines] time conducting, N-channel MOS transistor 111b that unit power lead ARVDb and decline power lead DWVDa and DWVDb are coupled; When reading (when standby and data) conducting when disactivation writes indicator signal WEZ, make the N-channel MOS transistor 112 of decline power lead DWVDa and DWVDb and the coupling of ground connection node.

Write the indicator signal WE[n that falls in lines] and WE[n+1], write in data fashionable, select corresponding memory cell columns (bit line BLa ,/BLa, BLb ,/BLb) time, be driven to selection mode respectively, (being driven to the H level).Write indicator signal WEZ, when writing pattern, be set at the L level.Therefore, when writing pattern, decline power lead DWVDa and DWVDb maintain quick condition under ground voltage level.On the other hand, write the unit power lead ARVD (ARVDa and ARVDb) that falls in lines and be coupled to decline power lead DWVDa and DWVDb.Therefore, the electric capacity of stray capacitance CP0 by the electric charge put aside on unit power lead ARVD and the condenser network of 2CP1 is cut apart, and (ARVDa, voltage level ARVDb) reduces to select the unit power lead ARVD of row.

Figure 41 illustrates the action that writes auxiliary array power circuit 108 that this is shown in Figure 40.

At first, in carrying out the readout interval that data read, be driven to selection mode by corresponding word lines driver WDV corresponding to the word line WL that selects row.At this moment, by drop down element PD, selecting the voltage level of word line WL is than the also low voltage level of array power supply voltage (bit-line pre-charge voltage level).After word line WL was driven into selection mode, ((/BL) voltage level reduced access transistor ATr in the memory cell of corresponding row to be connected to the bit line of the memory node of storage L data for NQ3, NQ4) conducting.

In readout interval, write the indicator signal WE[n that falls in lines], WE[n+1] all be the L level, writing indicator signal WEZ is the H level.Therefore, in writing auxiliary array power circuit 108, MOS transistor 110a and 110b are in conducting state, and MOS transistor 111a and 111b are in nonconducting state.Therefore, for each memory cell, by unit power lead ARVD (ARVDa and ARVDb) to high side power supply node VH feed unit supply voltage.The electricity of access transistor is led and is reduced, and current driving capability is correspondingly reduced, and this selects the static noise margin of the memory cell of row to become big, can stably carry out reading of data.

Carrying out in the write cycle that data write, at first, writing indicator signal WEZ becomes the L level, and in writing auxiliary array power circuit 108, MOS transistor 112 becomes nonconducting state.Correspondingly, decline power lead DWVDa and DWVDb become quick condition under ground voltage level.In addition, according to from the array selecting signal of column select circuit with write indicator signal, writing of each row indicator signal (WE[n]) of falling in lines is driven to the H level, and wherein array selecting signal is according to not shown column address signal and from the array selecting signal of column select circuit.Correspondingly, MOS transistor 110a becomes nonconducting state, and MOS transistor 111a becomes conducting state, separates from power supply node for the unit power lead ARVDa of memory cell MCa, in addition, is electrically connected with decline power lead DWVDa and DWVDb.The electric charge of on the stray capacitance CP0 of this unit power lead ARVDa, putting aside, stray capacitance CP1 to decline power lead DWVDa and DWVDb distributes, and proportional with the volume ratio of these stray capacitances CP0 and CP1, the voltage level of unit power lead ARVDa reduces.

In Figure 41, the state that the voltage level of expression unit power lead ARVDa and decline power lead DWVDa is kept under different mutually voltage levels.This is because produce the cause that voltage distributes by means of the conducting resistance of switch mos transistor 111a and 111b.The stray capacitance CP0 of unit power lead ARVD is fully bigger than the stray capacitance CP1 of decline power lead DVDW, even making the voltage level of these power leads ARVD and DWDV is identical voltage level, the current potential reduction amount of unit power lead ARVD is also fully little, can not destroy the preservation data of non-selection memory unit.Getting unit power lead ARVD under the situation of same potential and the voltage Vs of decline power lead DWDV represents with following formula.

Vs＝CP0·VDD·(CP0+CP1)

Conducting resistance at MOS transistor 111a that switch is used and 111b is bigger, and make consciously under the different situation of the voltage level of unit power lead ARVD and decline power lead DWDV, can suppress the reduction of the voltage level of unit power lead ARVDa reliably, and can reduce the static noise margin of non-selection memory unit, suppress to produce the state that keeps data reversal.

The drop-out voltage level of unit power lead, the driving force that can compensate the access transistor that the reduction owing to the voltage level of selecting word line causes reduces the reduction that writes tolerance limit that causes, and so long as can fully keep the voltage level of the static noise margin of non-selection memory unit and get final product.

The supply voltage of the first power lead ARVDa in ground is connected to the high side power supply node VH of memory cell MCa.Therefore, the current driving capability of load mos transistor PQ1 and PQ2 diminish (, accepting voltage decreases between the grid-grid of load transistor of L data on the grid) because source voltage reduces.(NQ3, current driving capability NQ4) is identical when reading with data, does not change for access transistor ATr.Therefore, select the tolerance limit that writes of the memory cell MCa of row to increase, the memory node of storage H data discharges into the L level according to writing data high-speed.Thus, for the selection memory unit, according to bit line BL ,/data of BL transmission, can carry out writing of data at high speed.

After data write end, bit line BL and/BL, by the bit-line load circuit, reset into the array power supply voltage level, in addition, word line WL is driven to nonselection mode., write array selecting signal WE[n thereafter] also become nonselection mode, MOS transistor 111a becomes nonconducting state, and MOS transistor 110a becomes conducting state, and in addition, MOS transistor 112 becomes conducting state.Correspondingly, decline power lead DWVDa and DWDVb are driven to ground voltage level once more, and on the other hand, unit power lead ARVDa resets into the array power supply voltage level.

Figure 42 is the figure that amplifies the signal waveform of expression dashed region I shown in Figure 41.In Figure 42, the longitudinal axis is represented voltage (V of unit), transverse axis express time (ns of unit).As shown in Figure 42, writing array selecting signal WE[n] be driven to selection mode after, the voltage level of unit power lead ARVD descends at a high speed, this is not the charging of carrying out from power supply node, but only is that electric charge between electric capacity moves.Because the electric charge that carries out between conductor wire (power lead) moves at a high speed, so can reduce the voltage level of the unit power lead ARVDa that selects row at a high speed.For example, after write activity begins, during through 0.3ms, reduce the voltage level of the unit power lead of about 100mV.

In addition, only be to use should the decline power lead and the electric charge of the stray capacitance of unit power lead move, when the power lead that uses other writes and reads, do not need to switch the voltage of this unit power lead, can simplify the structure of power circuit.In addition, only be that the electric charge between capacity cell moves, when this write cycle, perforation electric current can not take place flow to path between unit power lead and the ground connection node, can reduce power consumption.

This unit power lead ARVDa writes fashionable voltage level, can pass through unit power lead ARVD (ARVDa, ARVDb) (DWVDa, the volume ratio of stray capacitance CP1 DWVDb) is defined as suitable value and adjusts for stray capacitance CP0 and decline power lead DWVD.Corresponding to the voltage level of the selection word line that is determined by drop down element, the voltage level of setting the unit power lead of writing fashionable selection row is only voltage level.

In addition, in configuration shown in Figure 40, the decline power lead DWVDa and the DWVDb of 2 row configurations write unit power lead ARVD (ARVDa, ARVDb) short circuit or electrical couplings fashionable and the selection row in data.But corresponding to fashionable voltage level of writing of this unit power lead and the capability value of stray capacitance CP0 and CP1, these decline power lead 4 row are provided with one, select the unit power lead of row also can be coupled to corresponding decline power lead.In addition, select the unit power lead of row also can be coupled to a decline power lead.

Figure 43 is that shown in Figure 40 writing indicator signal WEZ and write the indicator signal WE[n that falls in lines takes place in expression] the figure of a routine structure of part.In Figure 43, write indicator signal WEZ and generate by the NAND120 that is included in the main control circuit shown in Figure 38 7.This NAND120 accepts write-enable signal WE and the chip enable signal CE next from the outside, when the both is in activated state (H is flat), will write the L level that indicator signal WEZ is set at activated state.

Write the indicator signal WE[n that falls in lines] by accept by phase inverter 124 supply with write indicator signal WEZ and from the array selecting signal CSL[n of column decoding 122] AND circuit 126 generate.This AND circuit 126, each row of pressing memory cell array are provided with, and write fashionablely, generate with respect to respective column and according to array selecting signal CSLi and to write the indicator signal WE[i that falls in lines].

Column decoding 4 is included in the column select circuit shown in Figure 38 4, column address signal CA from main control circuit 7 supplies, when chip enable signal CE activate, the column address signal CA of this supply of decoding will the array selecting signal CSL[n corresponding with selecting row] driving is the H level of selection mode.

This writes the indicator signal WE[n that falls in lines], be the L level writing indicator signal WEZ, expression writes pattern, and array selecting signal CSL[n] be the H level, specified corresponding row (bit line is to BLa ,/BLa) time, become the H level of activated state.

As mentioned above,, constitute drop down element, optionally be set at conducting state according to control signal with a plurality of unit transistors (duplicating access transistor) according to the 7th example of the present invention.Therefore, in when design, before its word line voltage level is set at only value, the word line voltage level when can inching reading, and word line voltage level that can accomplished only acting characteristic.In addition, when reality was produced in batches, according to each product, discrete corresponding to the threshold voltage of memory cell adjusted the conducting state of duplicating access transistor, thereby can be set at only voltage level.

In addition, use writes the auxiliary array power circuit, by with the electrical couplings of decline power lead, thereby move by means of the electric charge between stray capacitance and to reduce the voltage level of unit power lead that is arranged on behind each row, even under the situation that the voltage level of selecting word line reduces, write fashionablely in data, also can reduce the level of the high side supply voltage of selection memory unit at high speed, and enlarge and write tolerance limit.Thus, even under low supply voltage, also can realize can be stably to carry out the semiconductor storage that writes and read of data at a high speed.

In addition, in the above description, word line WL has the non-layered structure.But as shown in previous example, this word line WL also can have the layering word line structure that is divided into main word line and sub-word line.Drop down element PD is with respect to each sub-word line setting.

[layout of drop down element]

By the drop down element PD that each word line is provided with, use the replica transistor (have identical layout, and have identical threshold voltage characteristic) of the access transistor that in memory cell, comprises to realize.Replica transistor for the access transistor of configuration memory units, the situation of illustrated use dummy cell in the example formerly (the 5th example of Figure 22) is identical, adopts with same manufacturing process of the manufacturing process of memory cell and forms the replica transistor identical with the access transistor layout of memory cell.The following describes the layout of duplicating access transistor of formation drop down element and the layout of memory cell.

Figure 44 be expression from the active region of memory cell array the figure to the layout of first metal line.In Figure 44, linearly extended on column direction, N type active region 130a-130e configuration spaced apart.These N types active region 130a-130e is respectively formed in the P well area.In these N types active region 130a-130e, form access transistor and the driving transistors (N-channel MOS transistor) of memory cell MC.

In the layout of this memory cell array shown in Figure 44, the borderline region of memory cell MC is in line direction and column direction mirror image repeated configuration symmetrically.Therefore, in Figure 40, numerous and diverse for fear of picture given reference marks for wiring and the contact of memory cell MC.In memory cell MC zone, column direction is P type active region 132a and the mutual staggered positions of 132b and the configuration separated from one another of long rectangular shape.In these P types active region 132a and 132b, form load transistor (P channel MOS transistor).

Grid 133a extends configuration in the mode that intersects with N type active region 130b at line direction.This grid 133a is electrically connected to the first metal line FM1 by contact CC1.This metal line FM1 forms the long rectangular shape of column direction, and uses as the middle layer that contacts that is used to obtain with the upper strata wiring.

Active region 130b and 132 passes through contact CC3 and common contact SCTa electrical couplings respectively by means of the first metal line FM3.Common contact SCTa is electrically connected and is following the grid 133b that direction is extended, the other and grid 133b coupling with active region 132a.This grid 133b extends and is configured in the memory cell MC zone at line direction in the mode that intersects with active region 132b and 132c.

In this memory cell MC borderline region, adjacent with grid 133a and 133b, form first metal line FM2 and the FM4.These first metal line FM2 and FM4 are connected to active region 130b and 132b by contact CC2 and CC4 respectively.

Active region 132b is coupled to active region 130c by the first metal line FM7 in addition.That is the first metal line FM7 is coupled to extrinsic region 130c by contact CC7, in addition, is coupled to impurity activity zone 132b and grid 133c by common contact 132b.Grid 133c extends and is configured in the memory cell MC at line direction in the mode that intersects with active region 132a and 130b in addition.

133c is adjacent with grid, and disposes first metal line FM5 and the FM6.The first metal line FM5 is by contact CC5 and extrinsic region 130b electrical couplings, and the first metal line FM6 is by contact CC6 and active region 132a coupling.

Follow direction adjusting to a line with this grid 133c and separate, and dispose grid 133d in the mode that intersects with extrinsic region 130c and 130d.This grid 133d is coupled to the first metal line FM9 by contact CC9.

Equally, relative with this first metal line FM9 with grid 133b, dispose the first metal line FM10.This first metal line FM10 is connected electrically to active region 130c by contact CC10, and in addition, (CC) is coupled to active region 130b by the contact.

The configuration of this memory cell MC is expert at and column direction mirror image repeated configuration symmetrically, disposes the first metal line FM, common contact SCT, P type active region 132, contact CC, and memory cell MC is configured to rectangular.

As shown in figure 44, grid all forms the long rectangular shape of line direction, in each active region 132a-132e, disposes grid and contact with uniform distances on column direction.Therefore, can dispose access transistor and driving transistors with identical figure, and it is discrete to suppress these characteristics of transistor.

In addition, the active region also is in line at column direction and extends configuration.Therefore, in layout, all be in line laying-out and wiring and active region, and can simplify the layout of memory cell, in addition, can eliminate the influence of the edge effect of wiring.

Figure 45 is the figure of layout of second metal line on expression grid, first metal line and upper strata shown in Figure 44.In Figure 45,, extend as the crow flies and dispose the second metal line 134a-134g respectively at column direction corresponding to the P type active regions of each N type active region and 2 row.Correspond respectively to second metal line 134b and the 134d of N type active region 134b shown in Figure 44 and 134c configuration, constitute respectively bit line BL and/BL, the second metal line 134c corresponding to P type active region 132a shown in Figure 44 and 132b configuration constitutes unit power lead ARVD, the load transistor transmission unit supply voltage in the memory cell MC of respective column.

In this Figure 45, for the distributing of memory cell MC also because be expert at and column direction mirror image repeated configuration symmetrically, so only give reference marks for the wiring of memory cell MC.

In Figure 45, grid 133a-133d corresponds respectively to grid wiring 133a-133d shown in Figure 44.The first metal line FM1 that is provided with respect to grid wiring 133a is coupled to the second metal line SM1 by path VV1.Equally, the first metal line FM5 is coupled to the second metal line SM2 by path VV2.This second metal line SM2 is used for transmission unit ground voltage ARVSS.

The first metal line FM2 passes through path VV3 electrical couplings to the second metal line 134b.Equally, the first metal line FM4 is coupled by vinyl by the path VV5 and second metal wiring 134.In addition, the first metal line FM6 is coupled to the second metal line 134c by path VV3.

The first metal line FM8 is coupled to the second metal line 134d by path VV6.Equally, the first metal line FM9 that is coupled to grid 133d is by the path VV8 second metal line SM4 that is coupled.

The first metal line FM10 is coupled to the second metal line SM3 by path VV7.Be used for the transmission unit ground voltage with the path VV3 second metal line SM3 that is coupled.These second metal lines SM1-SM4 uses as the middle layer respectively, and this middle layer is used to obtain and being electrically connected of connecting up in the upper strata of the 1st corresponding metal line.

The first metal line FM3, FM7 form in the inside of memory cell MC the transistorized of memory node are interconnected, and are free of attachment to the upper strata metal line.

In addition, path VV, the first metal line FM and the second metal line SM also and the configuration in this memory cell MC same, in memory cell array, follow and the column direction mirror image disposes symmetrically.

Figure 46 is the figure that summarily represents the layout of second metal line in the memory cell array and the 3rd metal line with the layout of grid together.In Figure 46, expression is with respect to the grid 133a-133d of memory cell MC configuration.

In Figure 46, the 3rd metal line 136a-136c extends configuration at line direction respectively at intervals continuously as the crow flies.These the 3rd metal lines 136a-136c, along column direction with the coupling part of access transistor in have the mirror image symmetry distributing.

In this Figure 46, also give reference marks to the inscape of memory cell MC, do not give reference marks for other parts.Distributing among this memory cell MC becomes mirror image to dispose symmetrically at line direction and column direction.

In the zone of memory cell MC, the 3rd metal line 136b is by path VW1 and the second metal line SM1 coupling of being coupled to grid 133a.Equally, the 3rd metal line 136b is coupled by path VW4 and the second metal line SM4 that is coupled to grid 133b.The second metal line SM2 is by path VW2 and the 3rd metal line TM1 coupling.In memory cell MC, the second metal line SM3 that is positioned at the point-symmetric position of the second metal line SM2 is coupled by path VW3 and the 3rd metal line TM2.

The 3rd metal line 136a-136c constitutes word line WL respectively, and the transmission row selection signal.Therefore, the 3rd metal line 136a-136c respectively in each contact part with the grid electrical couplings of two access transistors.

Figure 47 is the figure that represents the layout of the 3rd metal line of memory cell array of the 7th example according to the present invention and the 4th metal line with the distributing of grid together.In Figure 47, give reference marks 133a-133d for the grid in the memory cell MC.The distributing of memory cell MC is expert at and column direction mirror image repeated configuration symmetrically.

In Figure 47, extend and the 4th metal line 140a-140h to be set in plane figure with mode that second metal line shown in Figure 46 almost overlaps at the column direction straight line.For memory cell MC, the 4th metal line 140b is coupled to the 3rd metal line TM1 by path VX1.The 3rd metal line TM1 and active region 130b shown in Figure 44 coupling, and be coupled with the source node of the driving transistors of memory cell.The 4th metal line 140b is as the unit ground wire ARVS use of transmission unit ground voltage.

The 4th metal line 140d is to dispose with mode that the second metal line 134c shown in Figure 46 almost overlaps in plane figure.The 4th metal line 140d uses as decline power lead DWVD, and the inscape with memory cell MC is not connected.With the unit power lead (with reference to Figure 45) that is formed on lower floor, write in data and fashionablely optionally to be electrically connected.

The 4th metal line 140f is coupled by path VX2 and the 3rd metal line TM2 in memory cell MC equally.The 3rd metal line TM2 as shown in figure 44, is coupled to active region 130c, is coupled to the source node of the driving transistors of memory cell MC.The 4th metal line 140a uses as unit ground wire ARVS.

The 4th metal line 140a, 140c, 140e and 140g are not coupled with memory cell MC especially.These the 4th metal lines 140a, 140c, 140e and 140g for example write fashionablely in data, also can be used as the control signal (writing array selecting signal) of voltage level of transmission adjustment unit power lead or the signal wire that writes indicator signal and use.In addition, the wiring layer that also can be used as other control signals of transmission uses.Moreover, also can only use as shield wiring for bit line.

Figure 48 is the figure of expression Figure 44 to the electrical equivalent circuit of memory cell MC shown in Figure 47.In Figure 48, in memory cell MC, in N type active region 130b, N-channel MOS transistor NQ3 and NQ1 are set, constitute access transistor and driving transistors respectively.In P type active region 132a and 132b, form P channel MOS transistor PQ1 and the PQ2 that constitutes load transistor respectively.In N type active region 130c, form N-channel MOS transistor NQ2 and the NQ4 that constitutes driving transistors and access transistor respectively.

The grid of MOS transistor NQ3 and word line WL coupling, an one conducting node and bit line BL coupling, the drain electrode of another conducting node and MOS transistor NQ1 and PQ1 is coupled.The source-coupled of MOS transistor NQ1 is to unit ground wire ARVS.The source electrode of MOS transistor 132a and unit power lead ARVD coupling.

The grid of these MOS transistor NQ1 and PQ1 is coupled by the drain electrode at the common contact shown in Figure 44 and first metal line and MOS transistor PQ2, NQ2 and NQ4 before.The drain electrode of the grid of MOS transistor PQ2 and NQ2 and MOS transistor NQ3, NQ1 and PQ1 is coupled.The source electrode of MOS transistor PQ2 and NQ2 is coupled with unit power lead ARVD and unit ground wire ARVS respectively.Source electrode and the bit line/BL of MOS transistor NQ4 are coupled.

Therefore, by in this memory cell MC, extending the configuration active region continuously along column direction, and be in line at column direction and extend ground dispensing unit power lead and unit ground wire, thereby the adjustment of unit power lead is become easy with the memory cell unit of classifying as.Especially, as shown in figure 47, by the decline power lead DWVD that uses the 4th metal line to extend continuously in the column direction configuration, thereby can be, and can easily write fashionable voltage level with the adjustment unit power lead ARDV of the unit of classifying as with being connected of the unit's of classifying as control module power lead and decline power lead.

Figure 49 is the figure of the plane figure of the expression unit transistor (duplicating access transistor) that constitutes drop down element.In Figure 49, the voltage of expression active region and the grid and first metal line.

In Figure 49, configuration is extended at the column direction straight line in N type active region 152 spaced apartly.Grid 150 is expert at and column direction adjusting to a line configuration.Each grid 150 disposes in the mode that intersects with two active regions 152.Each grid is listed as by per two active regions and is provided with.

For grid 150, two grids adjacent at each column direction are connected to first metal line 154 by contact 156a and 156b respectively.In each active region 152 and grid 150 first metal line 155 alternately is set.This first metal line 155 is provided with respect to two active regions 152 in the line direction adjacency, and is connected electrically to corresponding active region 152 by contact 157a and 157b respectively.

These active regions 152 and grid 150, collateral elaboration when N type active region 130 of making memory cell and grid 133.

The distance L b that the width La of the line direction of active region 152 and the active region adjacent with line direction are 152, (130a, 130b) width and spacing are identical with the active region of the access transistor of memory cell boundary shown in Figure 44.In addition, about the width Lc of the column direction of this grid 150 also with grid 133 shown in Figure 44 (133a, 133b) identical.In addition, also the spacing with the adjacent access transistor of memory cell shown in Figure 44 is identical for the spacing Le of grid 150.Have, the distance L d of grid 150 and adjacent contacts and the Lf also condition with the access transistor that is configured in the memory cell borderline region shown in Figure 44 are identical again.In addition, also the length with the line direction of the grid 133 of memory cell is identical for the length of the line direction of grid 150.

Therefore, the unit transistor of the drop down element that disposes in this Figure 49 (duplicating access transistor) has form parameter identical with the access transistor of memory cell shown in Figure 44 and layout figure.In addition, active region 152 adopts the impurity concentration identical with active region 130a shown in Figure 44 and 130b to constitute.Thus, the electrical specification of the unit transistor of drop down element (duplicating access transistor) is identical with the access transistor electrical specification of memory cell.Thus, can be corresponding to the change of the discrete caused electrical specification of the Fabrication parameter of the access transistor of memory cell and automatically adjust the conducting resistance of drop down element, and can will select the voltage level of word line to be set at only value corresponding to the characteristic of memory cell.

In addition, can in active region 152, dispose grid with same spacing, and can dispose the drop-down unit transistor of using to high-density along column direction.Therefore,, also can suppress the increase of the layout area of memory cell array, the drop-down unit transistor of using of configuration in memory cell array even disposing for each word line under the situation of a plurality of unit transistors.

Figure 50 is the figure of expression layout of second metal line of the drop down element of the 7th example according to the present invention.In Figure 50, merge the layout of expression grid 150.In Figure 50, extend at the column direction straight line, dispose second metal line 160 every two active regions 152.This second metal line 160 passes through path 161, is electrically connected be formed on first metal line 154 of its lower floor.Path 161 is configured by per two grids 150 at column direction.By a path 161, select 4 transistors of configuration up and down concurrently.

In addition, first metal line 155 corresponding to being electrically connected adjacent active region 152 is provided with second metal line 162.This second metal line 162 is connected to first metal line 155 that forms in lower floor by path 163.These second metal lines 160 and 162, collateral elaboration when the manufacturing of the bit line of memory cell and unit power lead.

Therefore, as shown in figure 50, by second metal line 160 and 162, first metal line 154 and 155 formation for configuration disconnected from each other are electrically connected respectively, and this is electrically connected the path 161 and 163 that forms usefulness and disposes in line direction adjusting to a line.Path 163 forms by every row corresponding to first metal line 155.Thus, can make the coupling of transistorized source electrode of constituent parts and ground connection node.

Figure 51 is the figure of expression layout of the 3rd metal line of the drop down element of the 7th example according to the present invention.In Figure 51, and the merging expression grid 150 and second metal line 160 (160a, 160b, 160c).

In Figure 51, extend continuously at line direction, by capable the 3rd metal line 165 that disposes of per two grids.The 3rd metal line 165, the mode with the 3rd metal line (136a-136c) of the word line that connects and composes memory cell array in same operation forms.The 3rd metal line 165 is connected to second metal line 162 shown in Figure 50 by path 166 respectively.This second metal line 162 is connected electrically to adjacent active region.Therefore, by a path 166, connect two transistor drain zones with respect to the 3rd metal line 165 that constitutes corresponding word lines.

Between second metal line 160 (160a-160c) and the 3rd metal line 165 at column direction the 3rd metal line 167 is set alternately.The 3rd metal line 167 is provided with respect to second metal line 162 respectively, and is electrically connected by path 168 and the second corresponding metal line 162.The 3rd metal line 167 uses as the contact that is used for the transmission unit ground voltage.

Constitute the 3rd metal line 165 of this word line WL, be provided with by per two grids 150 at column direction.Therefore, can with before disposed the 3rd metal line 165 at the identical wire distribution distance Lw1 of the 3rd metal line 136a-136c shown in Figure 46, for the unit transistor (duplicating access transistor) of memory cell and drop down element, straight line extends the 3rd metal line that the ground configuration constitutes word line WL continuously.

Respectively to the second metal line 160a, 160b and 160c transmission of control signals SM＜0 〉, SM＜1 and LSM.

In the second metal line 160a-160c, each root word line is selected 4 unit transistors (duplicating access transistor) UATr.That is, with respect to the 3rd metal line 165 that constitutes word line and constitute control signal wire second metal line 160 (160a-160c) cross section and up and down 4 unit transistors (duplicating access transistor) UATr of configuration selected by parallel.By increasing the number of control signal wire, can further increase the number of the unit transistor that each word line selects simultaneously.Here,, illustrate by each control signal SM＜0 as an example 〉, SM＜1 and LSM, each word line is selected the distributing of 4 unit transistors (duplicating access transistor) UATr.Use is arranged in rectangular a plurality of grids, by a contact/path, can select signal to a plurality of grid transmission, and each word line can be selected a plurality of unit transistors concurrently by a control signal wire.

Figure 52 is the figure of expression layout of the 3rd and the 4th metal line of the drop down element of the 7th example according to the present invention.In Figure 52, merge the layout of expression grid 150.

In Figure 52, in plane figure and the second metal line 160a-160c shown in Figure 51 alternately, extend and the 4th metal line 170 be set along the column direction straight line.The 4th metal line 170 is electrically connected by path 172 and the 3rd metal line 167 that is configured in respective column.The 3rd metal line 170 is transmission unit ground voltage VSS respectively.Therefore, in this each the 4th metal line 170, for the path 166 of the 3rd metal line 165 with for the path 172 of the 3rd metal line 167, along column direction adjusting to a line and alternately configuration.At column direction, by this path 166 and 172, dispose 4 unit transistor UATr, at column direction, between adjacent path 172, dispose two unit transistors (duplicating access transistor).

Therefore, comprise the connection of upper strata wiring, can be with the unit transistor of the layout configurations drop-down usefulness identical with the layout essence of the access transistor of memory cell, and can correctly form the duplicating of access transistor of memory cell.In addition and the layout of memory cell same, wiring also only is expert at or the column direction straight line extends, layout is easier to, can correctly carry out during fabrication graphical, thereby produce the replica transistor of the access transistor of memory cell.

Figure 53 is the figure that the electrical equivalent circuit of the electrical equivalent circuit of this drop down element PD and memory cell MCa and MCb is merged expression.In Figure 53, the configuration of the unit transistor in the drop down element PD that expression is disposed corresponding to two control signal wire SMa and SMb, word line WLa and WLb.

In Figure 53, in drop down element PD, carry out adjusting to a line with 1 row and dispose the N-channel MOS transistor RQ0-RQ2 that is coupled with common ground wire 170a, in addition, carry out adjusting to a line with 1 row and dispose MOS transistor RQ3 and RQ5, in addition, carry out adjusting to a line with 1 row and dispose MOS transistor RQ2 and RQ8.

On the grid of each MOS transistor RQ0-RQ5, accept control signal SMs by control signal wire 160s.On the grid of each MOS transistor RQ6-RQ8, accept control signal SMt by control signal wire 160t.

The MOS transistor RQ1 that between word line WLa and WLb, is provided with, RQ2, RQ4 and RQ5, be coupled to control signal wire 160s by common contact and path, in addition, MOS transistor RQ7 and RQ8 are coupled to control signal wire 160t by common contact and path.In this case, MOS transistor RQ1 and RQ2 are coupled to ground wire 170a by common contact and path, and MOS transistor RQ4, RQ5 and RQ7 and RQ8 are coupled to unit ground wire 170b by common path and contact.

These MOS transistor RQ0-RQ8 with the rectangular configuration of necessary number, and supplies with corresponding control signal to these transistors respectively.

In addition, control signal SMs and SMt are included in the control signal among the control signal group SMG.Control signal SMs and SMt, if identical control signal, then each root word line can walk abreast and select 8 unit transistors.

Memory cell MCa, according to the signal on the word line WLa and conducting, comprise with the trigger FF of inside and bit line BL and/ access transistor ATaa and ATab that BL is coupled.Memory cell MCb, the signal potential on the response word line WLb and conducting, comprise with trigger FF and bit line BL and/ access transistor ATba and ATbb that BL is coupled.

MOS transistor RQ0-RQ8 has identical layout with the grid of access transistor ATaa, ATba, ATab and ATbb.Therefore, these access transistors A TAa, ATab, ATba and A TBb and MOS transistor RQ0-RQ8 have same electrical specification.In memory cell MCa and MCb, because the discrete grade of Fabrication parameter causes under the discrete situation of its threshold value, in MOS transistor RQ0-RQ8, can reflect that also (for example mask position departs from for identical Fabrication parameter discrete, impurity concentrations etc. are discrete), produce same threshold voltage change, and can adjust the voltage level of selecting word line corresponding to the acting characteristic of these memory cells.

As mentioned above, use the replica transistor of the access transistor of memory cell to form drop down element.The unit transistor (duplicating access transistor) of this drop down element PD is made by same manufacturing process when memory cell manufacturing process.Thus, can correctly form with layout identical and grid condition and duplicate access transistor with the access transistor of memory cell.Even the Fabrication parameter of generation memory cell is discrete, also can in duplicating access transistor, reflect identical dispersing.Therefore, the voltage level of selecting word line can be set at the discrete voltage level that has reflected Fabrication parameter.Thus, tolerance limit can be guaranteed to read, and writing and reading of data can be stably carried out.

In addition, in drop down element PD, do not use dummy cell, only dispose the replica transistor of access transistor, and can reduce the configuration area of this drop down element PD.

In addition, in the above description, use to improve the drop down element PD that reads tolerance limit together and write the auxiliary auxiliary array power circuit that writes.Thus, in the structure of the voltage level of drop-down selection word line, also can stably guarantee to write tolerance limit.But, this write the auxiliary array power circuit also can be separately as with drop down element embodiment and being provided with independently.Can enlarge reliably and write tolerance limit.

[the 8th example]

Figure 54 is the figure of expression structure of the pith of the semiconductor storage of the 8th example according to the present invention.Semiconductor storage shown in this Figure 54, its structure is different in the following areas with the structure of semiconductor storage shown in Figure 28.That is, the drive power supply line DPL0-DPLi that is provided with respect to corresponding respectively to word line group WG0-WGi, be provided with a plurality of level shifter LSFN0, LSFN1 ...These level shifters LSFN0, LSFN1 ... comprise one or more transistor identical (duplicating access transistor UATr) respectively with the access transistor of memory cell MC.These level shifters LSFN0, LSFN1 ... the constituent parts transistor, under resistance mode, move, and the voltage level (cutting apart) of the drive power supply line of drop-down correspondence by resistance.

In drive power supply line pre-charge circuit DPG0-DPGi, according to the output signal of the NAND circuit NG10 that accepts high-order predecoding signal, optionally conducting of P channel MOS transistor PQ32 makes the coupling of corresponding drive power supply line DPL and power supply node.

Other structures of semiconductor storage shown in this Figure 54, identical with the structure of semiconductor storage shown in Figure 28, give identical reference marks for corresponding part, omit its detailed description.

Word line group WG0-WGi is selected when the high-order predecoding signal XH of correspondence and XM are the H level respectively.Therefore, to power supply node, for non-selection word line group, drive power supply line DPL separates from power supply node, maintains ground voltage level by level shifter LSFN0, LSFN1 for the drive power supply line electrical couplings of selecting word line group.Thus, can prevent from non-selection word line group, to flow through leakage current, and can reduce the consumption electric current, in addition, can reduce the consumption electric current when standby by word line driver.

By the level shifter of drop-down usefulness is set in the drive power supply line, thus with in each word line, drop down element is set and compares, can reduce component number, and can suppress array area and increase.

Figure 55 A and Figure 55 B are the figure of the routine structure of level shifter LSFN0, the LSFN1 shown in expression Figure 54.In Figure 55 A, (LSFN0 LSFN1) is connected between corresponding the drive power supply line DPLs and ground connection node level shifter LSFN, has the N-channel MOS transistor RQ10 of its gate coupled to power supply node.This MOS transistor RQ10 is made of transistor (the duplicating access transistor) UATr identical with the access transistor layout of memory cell, and the change of the threshold voltage of the access transistor of reflection memory cell.Gate coupled becomes through normally on to power supply node, moves as resistive element by its channel resistance (conducting resistance).

The grid of level shifter LSFN shown in Figure 55 B and drain electrode all are coupled with corresponding drive power supply line DPLs, have the N-channel MOS transistor RQ11 that its source electrode and ground connection node are coupled.This MOS transistor RQ11 also constitutes by having the transistor identical with the access transistor layout of memory cell, and the change of the transistorized threshold voltage of N-channel MOS of reflection memory cell.Grid and the drain electrode of MOS transistor RQ11 interconnect, and move under resistance mode, reduce the voltage level of corresponding drive power supply line DPL.

Figure 56 is drive power supply line pre-charge circuit DPG, the level shifter LSFN of the expression respective drivers power lead DPL that selects word line group and the figure that is electrically connected of word line driver.In Figure 56, the MOS transistor PQ32 in the drive power supply line pre-charge circuit has conducting resistance Rp.MOS transistor in level shifter (RQ10 or RQ11) has conducting resistance Rn.Drive power supply line DPLi, the MOS transistor PQ30 by word line driver is coupled to word line WL.The current potential V (ND10) of the transistorized source node ND10 of word line driver (drive power supply line) represents with following formula.

V(ND10)＝VDD·Rn/(Rp+Rn)＝VDD/(1+(Rp/Rn))

Threshold voltage at the access transistor of memory cell raises, current driving capability diminishes, when correspondingly electricity is led and is diminished, the resistance value of resistance R n raises.Correspondingly, the current potential of the source node ND10 of driver transistor (ND10) raises, and selects the current potential of word line WL to raise.Under the higher state of the threshold voltage of the access transistor of this memory cell, the current driving capability of access transistor is little, can fully guarantee the static noise margin of memory cell, even improve the storage data that the current potential of selecting word line also can stably keep memory cell.At this moment, in addition, can improve the conducting resistance of the MOS transistor of level shifter LSFN, and suppress excessively to reduce the voltage level of selecting word line.

Otherwise, reduce at the threshold voltage of the access transistor of memory cell, current driving capability become big, when electricity is led and is become big, the resistance value of resistance R n reduces.Correspondingly, the current potential of the source node ND10 of driver transistor reduces, and selects the current potential of word line WL to reduce.The current driving capability of the access transistor of memory cell is diminished, increase the static noise margin of memory cell.

Therefore, the resistance partitioning circuitry of the conducting resistance by having utilized MOS transistor PQ32 and RQ10 or RQ11 reduces the supply voltage of word line driver, adjust these transistorized conduction resistance value Rp and Rn, thereby can will select word line to be set at optimal voltage level corresponding to the static noise margin of memory cell, even under low supply voltage, also can stably carry out reading of data.

Write fashionable in data, under the lower situation of the threshold voltage of the access transistor of memory cell, even under the state of the voltage that writes tolerance limit, reduction selection word line that increases memory cell, also can fully guarantee to write tolerance limit, can carry out writing of data at a high speed.Under the threshold voltage condition with higher of the access transistor of memory cell,, write tolerance limit thereby reduce by reducing the voltage level of selecting word line, and under this state, can suppress to select the reduction of the voltage level of word line, suppress to write tolerance limit and worsen, realize writing at a high speed.

In addition, in the above description, use as the transistor of the inscape of level shifter LSFN and to duplicate access transistor.But, also can use the transistor (duplicating access transistor) that the driver transistor layout that has with memory cell is identical, have the characteristic that the flutter with driver transistor links.In this case, also can access same effect.

In addition,, also can in each level shifter LSFN, a plurality of accesses/driver replica transistor be set, make these replica transistor selectively and regularly be in conducting state by control signal or main wiring as Figure 38 and shown in Figure 39.

Have again, also can be provided with and write auxiliary power circuit, with level shifter and the combination that writes auxiliary power circuit, the adjustment of carrying out the static noise margin of memory cell and writing tolerance limit.

As mentioned above,, the level shifter of drop-down usefulness is set on the drive power supply line, moves down voltage the drive power supply line of selecting word line group according to the 8th example of the present invention.Therefore, can need not to increase area and improve the static noise margin of memory cell and write tolerance limit, even under low supply voltage, also can realize to stablize and carrying out at high speed the semiconductor storage of reading and writing of data.

The present invention generally can be applicable to the semiconductor storage with static type memory cell.Especially, by being applicable to the static semiconductor memory device of the low-power consumption of using low supply voltage, can realize the static semiconductor memory device of low-power consumption and operating stably.

This explanation is had been described in detail, but this only is expression for example, and is not considered as limiting that the spirit and scope of the present invention are only limited by the scope of claims.

Claims (31)

1. semiconductor storage has:

Become a plurality of static type memory cells of rectangular arrangement;

Corresponding to each described column of memory cells configuration, connect a plurality of word lines of the memory cell of corresponding row respectively; And

Configuration corresponding with each described word line, according to word line selection signal corresponding word lines is driven into a plurality of word line drivers of selection mode,

Each described word line driver has the level moving meter that the voltage level of actuator electrical source node is moved to the voltage level lower than the voltage of described actuator electrical source node, when corresponding word lines is selected, corresponding word lines is driven into the voltage level of having implemented after level moves by this level moving meter.

2. the described semiconductor storage of claim 1, wherein,

Each described memory cell comprises in data store: be connected to the load transistor of unit power supply node and the driving transistors that is connected in series with described load transistor,

Described level moving meter constitutes by having with same transistor unit threshold voltage characteristic and the same conductivity type of load transistor of described load transistor.

3. the described semiconductor storage of claim 2, wherein, described transistor unit is made of the unit transistors of a plurality of configurations in parallel.

4. the described semiconductor storage of claim 3, wherein,

The load transistor of described memory cell is made of insulated-gate type field effect transistor,

The ratio of the channel width of described unit transistor and channel length is between 0.5 times to 5 times of the ratio of the channel width of described load transistor and channel length.

5. the described semiconductor storage of claim 1, wherein,

Each described memory cell comprises in data store: be connected to the load transistor of unit power supply node and the driving transistors that is connected in series with described load transistor,

The load transistor of described memory cell is made of insulated-gate type field effect transistor,

Described level element comprises: the transistor unit of the ratio of channel width and channel length between 0.5 times to 5 times of the ratio of the channel width of described load transistor and channel length.

6. the described semiconductor storage of claim 1, wherein,

Described memory cell has the first conducting node and the unit power supply node is coupled and grid is connected to the load transistor of inner memory node,

Described level moving meter comprises such transistor unit, and this transistor unit has the grid that extends configuration with the grid of described load transistor along identical direction.

7. the described semiconductor storage of claim 1 wherein, further has:

A plurality of array power leads, dispose respectively corresponding to each memory cell columns, be coupled to the unit power supply node of the memory cell of respective column respectively; With

Write auxiliary circuit, data are write fashionable, reduce the voltage level of the unit power lead that disposes corresponding to the memory cell of selecting row.

8. semiconductor storage has:

Become a plurality of static type memory cells of rectangular arrangement;

A plurality of word lines dispose corresponding to each described column of memory cells, and connect the memory cell of corresponding row respectively;

A plurality of word line drivers are driven into selection mode with the corresponding configuration of each described word line and according to word line selection signal with corresponding word lines; With

A plurality of drop down element are provided with corresponding to each described word line, and reduce the voltage level of corresponding word lines when selected respectively.

9. the described semiconductor storage of claim 8, wherein,

Each described memory cell comprises in data store: be connected to the load transistor of unit power supply node and the driving transistors that is connected in series with this load transistor,

Described drop down element is made of the transistor unit that has with the same conductivity type of the same threshold voltage characteristic of described driving transistors.

10. the described semiconductor storage of claim 8, wherein,

Each described memory cell comprises in data store: be connected to the load transistor of unit power supply node and the driving transistors that is connected in series with this load transistor,

The driving transistors of described memory cell is made of insulated-gate type field effect transistor,

Described drop down element comprises: the transistor unit of the ratio of channel width and channel length between 0.5 times to 5 times of the ratio of the channel width of described driving transistors and channel length.

11. the described semiconductor storage of claim 8, wherein, each described drop down element constitutes by writing the fashionable transistor unit that becomes nonconducting state according to the data write control signal in data.

12. the described semiconductor storage of claim 8, wherein, described drop down element is configured between the memory cell of corresponding word lines driver and corresponding row.

13. the described semiconductor storage of claim 8, wherein, each described drop down element is made of the unit transistor of a plurality of configurations in parallel.

14. the described semiconductor storage of claim 13, wherein,

The driving transistors of described memory cell is made of insulated-gate type field effect transistor,

The ratio of the channel width of described unit transistor and channel length is between 0.5 times to 5 times of the ratio of the channel width of described driving transistors and channel length.

15. the described semiconductor storage of claim 8, wherein,

Described memory cell comprises such driving transistors: this driving transistors and the load transistor that is connected to the unit power supply node are connected in series and have a grid of the grid that is connected to described load transistor,

Described drop down element comprises: have the transistor unit that extends the grid of configuration with the grid of described driving transistors along same direction.

16. the described semiconductor storage of claim 8, wherein,

Described memory cell comprises: have the grid that is coupled with corresponding word lines and the access transistor of conducting according to the current potential of described corresponding word lines and optionally.

Described drop down element comprises: have the transistor unit that extends the grid of configuration with the grid of described access transistor along same direction.

17. the described semiconductor storage of claim 8, wherein,

Each described memory cell has according to the current potential of the corresponding word lines access transistor of conducting optionally,

Described drop down element is made of the transistor unit of the same conductivity type with threshold voltage characteristic identical with described access transistor.

18. the described semiconductor storage of claim 8, wherein,

Each described memory cell has according to the current potential of the corresponding word lines access transistor of conducting optionally,

The access transistor of described memory cell is made of insulated-gate type field effect transistor,

Described drop down element comprises: the transistor of the ratio of channel width and channel length between 0.5 times to 5 times of the ratio of the channel width of described access transistor and channel length.

19. the described semiconductor storage of claim 8, wherein,

Described memory cell comprises: be connected to the load transistor of unit power supply node, be connected in series with described load transistor and grid is connected to the optionally access transistor of conducting of the driving transistors of grid of described load transistor and the current potential that has the grid that is coupled with corresponding word lines and respond described corresponding word lines

Described drop down element comprises the transistor unit with described access transistor and the same conductivity type of driving transistors, and the ratio of the channel width of this transistor unit and channel length is between the ratio of the channel width of the ratio of the channel width of described driving transistors and channel length and described access transistor and channel length.

20. the described semiconductor storage of claim 8, wherein,

Each described drop down element has a plurality of transistor units that are coupled with corresponding word lines,

Described a plurality of transistor unit optionally is set at conducting state according to control signal.

21. the described semiconductor storage of claim 20, wherein,

Each described memory cell has the access transistor that becomes conducting state according to the voltage on the corresponding word lines,

Described transistor unit has the gate layout identical with described access transistor.

22. the described semiconductor storage of claim 8 wherein, further has:

A plurality of array power leads dispose respectively, and are coupled to the unit power supply node of the memory cell of respective column respectively corresponding to each memory cell columns;

Write auxiliary circuit, data are write fashionable, reduce the voltage level of the unit power lead of the memory cell of configuration corresponding to selecting row.

23. a semiconductor storage, comprising:

A plurality of static type memory cells, become rectangular arrangement, and comprise respectively access transistor and the storage data driving transistors;

A plurality of word lines are corresponding to each described column of memory cells configuration, and connect the access transistor of the memory cell of corresponding row respectively;

A plurality of word line drivers are with the corresponding configuration of each described word line, and according to word line selection signal corresponding word lines is driven into selection mode respectively;

A plurality of active regions, disconnected from each other and along the memory cell column direction extend continuously and and each word line disposes with intersecting and and each described word line in the cross section electrical couplings;

A plurality of grids that duplicate, with respect to each active region, on the memory cell column direction, be configured with spacing and the layout identical with the grid of described access transistor, described a plurality of duplicate that grid is expert at and column direction on the adjusting to a line configuration, each word line is coupled with corresponding active region in first side of the column direction that respectively duplicates grid;

A plurality of control signal wires, with described duplicate mode that grid intersects along column direction dispose continuously and with respective column duplicate the grid electrical couplings, respectively to the corresponding grid transmission of control signals that duplicates; And

A plurality of unit ground wire, electrical couplings is to second side and transmit ground voltage respectively, and this second side is faced mutually with first side of the column direction that respectively duplicates grid of each described active region.

24. the described semiconductor storage of claim 23 wherein, further has and is interconnected on the adjacent conductor wire that duplicates grid of column direction, by a control signal wire, each word line is supplied with control signals to a plurality of grids that duplicate jointly.

25. the described semiconductor storage of claim 23 wherein, further has:

A plurality of array power leads dispose respectively, and are coupled to the unit power supply node of the memory cell of respective column respectively corresponding to each memory cell columns;

Write auxiliary circuit, data are write fashionable, reduce the voltage level of the unit power lead that disposes corresponding to the memory cell of selecting row.

26. a semiconductor storage has:

Become a plurality of static type memory cells of rectangular arrangement;

A plurality of word lines dispose corresponding to each described column of memory cells, and connect the memory cell of corresponding row respectively;

A plurality of word line drivers are driven into selection mode with the corresponding configuration of each described word line and according to word line selection signal with corresponding word lines;

A plurality of array power leads, corresponding to each memory cell columns respectively configuration, the unit power supply node with the memory cell of respective column is coupled respectively;

A plurality of draw power lines, corresponding to the configuration of each memory cell columns, when data are read, maintain ground voltage level and write the fashionable quick condition that becomes in data; With

A plurality of auxiliary elements that write, will corresponding to the configuration of each unit power lead, stop to unit power lead feed unit supply voltage that selecting row, will be coupled with the draw power line of respective column at least corresponding to the unit power lead of selecting the row configuration simultaneously according to writing the indicator signal of falling in lines.

27. the described semiconductor storage of claim 26, wherein,

Described draw power line, according to the draw power line grouping of each defined amount, the draw power line interconnects in each group,

Described semiconductor storage further has on-off element, writes indicator signal corresponding to the configuration of draw power line and response data in each group the draw power line and the ground connection node of corresponding group are coupled.

28. a semiconductor storage has:

Become a plurality of static type memory cells of rectangular arrangement;

A plurality of word lines, corresponding to each described column of memory cells setting, connected the memory cell of corresponding row respectively;

A plurality of word line drivers, corresponding with each described word line that be provided with, when having specified the corresponding word lines address, this corresponding word lines is driven into selection mode;

A plurality of driver pre-charge circuits, the word line group that corresponds respectively to the defined amount of described a plurality of word lines dispose, respectively when the corresponding word lines group is selected, supply with the voltage of first voltage level to the word line driver of corresponding word lines group; With

A plurality of level shift circuits, the voltage of first voltage level that is provided with corresponding to each described driver pre-charge circuit, also respectively the driver pre-charge circuit of correspondence is exported moves to than its low voltage level.

29. the described semiconductor storage of claim 28, wherein,

Each described static type memory cell comprises: be coupled to the access transistor of corresponding word lines and the driving transistors of storage data,

Each described level shift circuit has such transistor, and this transistor has the characteristic that at least one the flutter with the access transistor of described static type memory cell and driving transistors links.

30. the described semiconductor storage of claim 29, wherein, the transistor of described level shift circuit is the insulated-gate type field effect transistor with the resistance mode action.

31. the described semiconductor storage of claim 28, wherein, in each described driver pre-charge circuit, except the word line of corresponding word lines group designated during the address, the node of supplying with the voltage of described first voltage level separates with the corresponding word lines driver.

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