CN116879705A - Method and system for testing durability of semiconductor device - Google Patents
Method and system for testing durability of semiconductor device Download PDFInfo
- Publication number
- CN116879705A CN116879705A CN202311152317.2A CN202311152317A CN116879705A CN 116879705 A CN116879705 A CN 116879705A CN 202311152317 A CN202311152317 A CN 202311152317A CN 116879705 A CN116879705 A CN 116879705A
- Authority
- CN
- China
- Prior art keywords
- level value
- level
- value
- drain
- field effect
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000012360 testing method Methods 0.000 title claims abstract description 87
- 238000000034 method Methods 0.000 title claims abstract description 25
- 239000004065 semiconductor Substances 0.000 title claims abstract description 23
- 230000005669 field effect Effects 0.000 claims abstract description 121
- 239000003990 capacitor Substances 0.000 claims abstract description 43
- 230000014759 maintenance of location Effects 0.000 claims abstract description 40
- 230000009471 action Effects 0.000 claims description 16
- 238000010998 test method Methods 0.000 claims description 2
- 238000011156 evaluation Methods 0.000 abstract description 4
- 238000012545 processing Methods 0.000 abstract description 2
- 230000008859 change Effects 0.000 description 30
- 230000015556 catabolic process Effects 0.000 description 5
- 238000006731 degradation reaction Methods 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 230000010354 integration Effects 0.000 description 4
- 210000003127 knee Anatomy 0.000 description 3
- 230000008569 process Effects 0.000 description 3
- 238000013459 approach Methods 0.000 description 2
- 238000012417 linear regression Methods 0.000 description 2
- 239000004973 liquid crystal related substance Substances 0.000 description 2
- 238000005259 measurement Methods 0.000 description 2
- 238000001514 detection method Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/26—Testing of individual semiconductor devices
- G01R31/2642—Testing semiconductor operation lifetime or reliability, e.g. by accelerated life tests
Abstract
The invention provides a method and a system for testing durability of a semiconductor device, which relate to the technical field of electric signal processing, wherein the method comprises the following steps: setting the gate level to a first level value in two test phases; setting the drain level to a second level value and a sixth level value respectively, and measuring a drain current; the drain electrode and the source electrode are connected to the capacitor, the level of the drain electrode is set to be a third level value, the drain electrode is kept stand for a first preset time period, and a fifth level value and a seventh level value of the drain electrode in two testing stages are obtained; obtaining performance stability scores according to the first level value, the second level value, the drain current and the sixth level value; obtaining a data retention rating according to the fifth level value, the third level value and the seventh level value; a durability score is obtained from the performance stability score and the data retention score. According to the invention, the durability of the field effect tube can be determined from multiple dimensions, and the accuracy of durability evaluation is improved.
Description
Technical Field
The present invention relates to the field of electrical signal processing technologies, and in particular, to a method and a system for testing durability of a semiconductor device.
Background
In the related art, when testing semiconductor devices, the yield and performance parameters of the semiconductor devices can be usually tested, and when the electronic products are used for a long time, performance degradation occurs frequently, for example, a phenomenon such as operation jam occurs, which may be caused by poor durability and performance degradation of the semiconductor devices in the electronic products, but durability testing is usually difficult, because the semiconductor devices which are not manufactured newly are usually good in performance, and the performance degradation occurs greatly in a short time, so that it is difficult to test the degradation condition by only means of testing the performance parameters in the related art, and thus it is difficult to test the durability of the semiconductor devices.
Disclosure of Invention
The invention provides a method and a system for testing the durability of a semiconductor device, which can determine the durability of a field effect transistor from multiple dimensions and solve the problem that the durability of the semiconductor device is difficult to test.
The invention provides a durability test method of a semiconductor device, which comprises the following steps:
setting the grid level of the field effect transistor to a plurality of first level values in a first test stage;
Setting the drain level as a plurality of second level values under the action of each first level value respectively, and measuring the corresponding drain current;
the drain electrode and the source electrode of the field effect transistor are respectively connected to two ends of a preset capacitor, the drain electrode level is set to be a third level value, the grid electrode level is set to be a fourth level value, and the first preset time period is kept stand, wherein the fourth level value is higher than the third level value;
setting the grid level to 0V, disconnecting the power supply of the drain electrode, and obtaining a fifth level value of the drain electrode after standing for a second preset time period;
connecting the field effect tube to a preset circuit, and operating for a third preset time period, wherein in the preset circuit, the voltage at the connection part of the grid electrode and the drain electrode of the field effect tube changes according to preset frequency and amplitude;
setting the grid level of the field effect transistor to a plurality of first level values in a second testing stage after the third preset time period;
setting the drain level to a plurality of sixth level values under the action of each first level value respectively, and measuring the corresponding drain current;
the drain electrode and the source electrode of the field effect transistor are respectively connected to two ends of a preset capacitor, the level of the drain electrode is set to be a third level value, the level of the grid electrode is set to be a fourth level value, and the first preset time period is kept stand;
Setting the grid level to 0, disconnecting the power supply of the drain electrode, and obtaining a seventh level value of the drain electrode after standing for a second preset time period;
obtaining a performance stability score of the field effect transistor according to the first level value, the second level value, the drain current corresponding to the second level value, the sixth level value and the drain current corresponding to the sixth level value;
obtaining a data retention rating of the field effect tube according to the fifth level value, the third level value and the seventh level value;
and obtaining the durability score of the field effect tube according to the performance stability score and the data retention score.
A semiconductor device endurance test system, comprising:
the first setting module is used for setting the grid level of the field effect transistor to a plurality of first level values in a first test stage;
the first measuring module is used for setting the drain electrode level to a plurality of second level values under the action of each first level value respectively and measuring the corresponding drain electrode current;
the first charging module is used for respectively connecting the drain electrode and the source electrode of the field effect transistor to two ends of a preset capacitor, setting the level of the drain electrode as a third level value, setting the level of the grid electrode as a fourth level value, and standing for a first preset time period, wherein the fourth level value is higher than the third level value;
The first acquisition module is used for setting the grid level to 0V, disconnecting the power supply of the drain electrode, and acquiring a fifth level value of the drain electrode after standing for a second preset time period;
the operation module is used for connecting the field effect transistor to a preset circuit and operating for a third preset time period, wherein in the preset circuit, the voltage at the junction of the grid electrode and the drain electrode of the field effect transistor changes according to preset frequency and amplitude;
the second setting module is used for setting the grid level of the field effect transistor to a plurality of first level values in a second testing stage after the third preset time period;
the second measuring module is used for setting the drain level to a plurality of sixth level values under the action of each first level value respectively and measuring the corresponding drain current;
the second charging module is used for respectively connecting the drain electrode and the source electrode of the field effect transistor to two ends of a preset capacitor, setting the level of the drain electrode as a third level value, setting the level of the grid electrode as a fourth level value, and standing for a first preset time period;
the second acquisition module is used for setting the grid level to 0, disconnecting the power supply of the drain electrode, and acquiring a seventh level value of the drain electrode after standing for a second preset time period;
A performance stability scoring module, configured to obtain a performance stability score of the fet according to the first level value, the second level value, a drain current corresponding to the second level value, the sixth level value, and a drain current corresponding to the sixth level value;
the data retention rating module is used for obtaining the data retention rating of the field effect transistor according to the fifth level value, the third level value and the seventh level value;
and the durability scoring module is used for obtaining the durability score of the field effect tube according to the performance stability score and the data retention score.
The invention can respectively acquire the drain current under the condition that the grid level is a plurality of level values before and after the field effect tube is connected into the preset circuit, thereby determining the change of the drain current before and after the field effect tube is connected into the preset circuit, further determining whether the performance of the field effect tube is changed, rapidly determining the performance change condition of the field effect tube, determining the durability of the field effect tube based on the performance change condition, and determining whether the charge leakage condition of the field effect tube under the condition of being disconnected is changed before and after the field effect tube is connected into the preset circuit based on the voltage change of the capacitor connected between the drain and the source, so as to judge the data retention capacity of the field effect tube, and determining the durability of the field effect tube from a plurality of dimensions, thereby improving the accuracy of durability evaluation. When the performance stability of the field effect tube is determined, the inflection point stability score can be determined, the average similarity of inflection points corresponding to each first level value can be determined, and weighting can be carried out through the preset level and the first level value, so that the performance stability of the field effect tube in most use scenes can be accurately reflected, the overall performance stability of the field effect tube can be represented through the approaching degree of the first slope and the second slope, and the accuracy and objectivity of the inflection point stability score can be improved. The output difference score can be determined, the total difference of the relation between the drain current and the drain level in two test stages can be determined, and the total difference can be weighted, so that the stability of the field effect transistor in most use scenes can be reflected more accurately, and the accuracy and objectivity of the output difference score are improved. When the data retention of the field effect tube is determined, the retention of the field effect tube on the charges in the preset capacitor in two test stages can be respectively determined, so that whether the retention of the field effect tube on the charges is obviously changed or not is judged, and the accuracy and objectivity of the data retention scoring are improved.
Drawings
Fig. 1 exemplarily shows a flow diagram of a method for testing endurance of a semiconductor device according to an embodiment of the present invention;
fig. 2 schematically illustrates a schematic diagram of a semiconductor device endurance test system according to an embodiment of the present invention.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is apparent that the described embodiments are only some embodiments of the present invention, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
The technical scheme of the invention is described in detail below by specific examples. The following embodiments may be combined with each other, and some embodiments may not be repeated for the same or similar concepts or processes.
Fig. 1 exemplarily shows a flow diagram of a method for testing endurance of a semiconductor device according to an embodiment of the present invention, the method including:
Step S101, in a first test stage, setting the grid level of a field effect transistor to a plurality of first level values;
step S102, setting the drain level as a plurality of second level values under the action of each first level value respectively, and measuring the corresponding drain current;
step S103, connecting a drain electrode and a source electrode of the field effect transistor to two ends of a preset capacitor respectively, setting a drain electrode level to be a third level value, setting a grid electrode level to be a fourth level value, and standing for a first preset time period, wherein the fourth level value is higher than the third level value;
step S104, setting the grid level to 0, disconnecting the power supply of the drain electrode, and obtaining a fifth level value of the drain electrode after standing for a second preset time period;
step S105, connecting the field effect transistor to a preset circuit, and operating for a third preset time period, wherein in the preset circuit, the voltage at the junction of the grid electrode and the drain electrode of the field effect transistor changes according to preset frequency and amplitude;
step S106, setting the grid level of the field effect transistor as a plurality of first level values in a second test stage after the third preset time period;
step S107, setting the drain level to a plurality of sixth level values under the action of each first level value respectively, and measuring the corresponding drain current;
Step S108, connecting the drain electrode and the source electrode of the field effect transistor to two ends of a preset capacitor respectively, setting the level of the drain electrode as a third level value, setting the level of the grid electrode as a fourth level value, and standing for a first preset time period;
step S109, setting the grid level to 0, disconnecting the power supply of the drain electrode, and obtaining a seventh level value of the drain electrode after standing for a second preset period of time;
step S110, obtaining a performance stability score of the field effect transistor according to the first level value, the second level value, the drain current corresponding to the second level value, the sixth level value and the drain current corresponding to the sixth level value;
step S111, obtaining a data retention rating of the field effect transistor according to the fifth level value, the third level value and the seventh level value;
and step S112, obtaining the durability score of the field effect tube according to the performance stability score and the data retention score.
According to the method for testing the durability of the semiconductor device, the drain current under the condition that the grid level is a plurality of level values can be obtained before and after the field effect tube is connected into the preset circuit, so that the change of the drain current before and after the grid level is connected into the preset circuit is determined, further whether the performance of the field effect tube is changed is determined, the performance change condition of the field effect tube can be rapidly determined, the durability of the field effect tube can be determined based on the performance change condition, and further whether the charge leakage condition of the field effect tube is changed before and after the grid level is connected into the preset circuit can be determined based on the voltage change of the capacitor connected between the drain and the source, so that the data retention force of the field effect tube is judged, the durability of the field effect tube can be determined from a plurality of dimensions, and the accuracy of durability evaluation is improved.
According to an embodiment of the present invention, the field effect transistor may be an N-channel enhancement type MOS transistor, and the present invention is not limited to the specific type of the field effect transistor. The gate level of the fet may have an effect on the impedance between the source and drain, assuming a source level of 0 (e.g., ground), in which case different gate level values are set, and different relationships between the drain level and the drain current may occur.
According to an embodiment of the present invention, in step S101, a plurality of first level values, for example, 0V, 2V, 4V, 6V, 8V, etc., may be set for the gate of the field effect transistor, and the specific values of the first level values are not limited in the present invention.
According to an embodiment of the present invention, in step S102, after each determination of the first level value, the drain level may be continuously changed, that is, the drain level is set to a plurality of second level values, and the corresponding drain current is measured, for example, the gate level is set to 0V, and the drain currents in the case where the drain level is set to a plurality of second level values of 0.5V, 1V, 1.5V, 2V, etc. are detected, respectively. Subsequently, the first level value may be changed, for example, the gate level is set to 2V, and drain currents in the case where the drain levels are a plurality of second level values of 0.5V, 1V, 1.5V, 2V, etc. are detected, respectively. The above-described detection method may be iteratively performed such that the drain level is continuously changed by a plurality of first level values, and the drain current corresponding to each drain level (i.e., the second level value) is detected.
In step S103, the fet is considered to be kept in a completely new state during the first test phase, where the fet performs optimally, and the drain and source are close to open circuit (or only a small current) when the fet is turned off (e.g., when the gate level is set to 0V), according to an embodiment of the present invention. The gate level may be set to a fourth level value and the drain level may be set to a third level value, with the fourth level value being higher than the third level value, such that the drain and source are conductive (i.e., there is some impedance between the drain and source, but current is allowed to flow normally). And a preset capacitor is connected between the source electrode and the drain electrode, and can be charged in a first preset period of time when the capacitor is kept still, so that the voltage at two ends of the preset capacitor is equal to the third level value, for example, the voltage at one end of the preset capacitor connected with the drain electrode is equal to the third level value, and the voltage at one end of the preset capacitor connected with the source electrode is 0V.
According to an embodiment of the present invention, in step S104, after the first preset period of time is completed, the preset capacitor is charged, and the gate level may be set to 0V, that is, the drain and the source are cut off, and the drain and the source are close to the open circuit state. And the power supply connection of the drain electrode can be disconnected, so that the drain electrode is only connected with one end of the preset capacitor. The potential difference between the drain and the source is equal to the voltage of the preset capacitance, i.e., the third level value. In the second preset period of rest, the drain electrode and the source electrode are in a cut-off state, but weak current may exist, the weak current may reduce the charge quantity at two ends of the preset capacitor, so that the voltage at two ends of the preset capacitor is reduced, and after the second preset period of rest, a fifth level value of the drain electrode may be detected, wherein the fifth level value is smaller than the third level value.
According to one embodiment of the present invention, in step S105, to test the durability of the fet, the fet may be connected to a preset circuit, in which the source of the fet may be grounded, the voltages of the gate and the drain may be continuously changed according to a preset frequency and amplitude, for example, the voltage of the drain may be changed at a higher frequency and not necessarily lower than the voltage of the gate, so that the fet may experience multiple conditions in a third preset time period, so that the fet may experience multiple use scenarios in a shorter time period with a faster change frequency of the voltage,
according to one embodiment of the invention, in step S106, after a third preset period of time, a test of the second test phase may be performed. The test conditions are consistent with those of the first test stage, and various performance parameters of the field effect transistor in the second test stage are obtained, so that the performance parameters in the first test stage and the performance parameters in the second test stage can be compared to determine the change of the performance parameters of the field effect transistor, and further determine whether the durability of the field effect transistor is good.
According to one embodiment of the present invention, since the test conditions are consistent with the first stage, in step S106, a plurality of first level values may be set for the gate of the field effect transistor as in step S101. In step S107, the drain level may be continuously changed after each determination of the first level value, that is, the drain level may be set to a plurality of sixth level values (the sixth level value may be equal to the second level value) in the same manner as in step S102, and the corresponding drain current may be measured. The drain current of the second test stage may deviate from the drain current of the first test stage. In step S108, the gate level may be set to a fourth level value and the drain level may be set to a third level value, so that the drain and the source are turned on, a preset capacitor is connected between the source and the drain, and the preset capacitor is charged for a first preset period of time during which the capacitor is stationary, as in step S103. In step S109, the same as step S104, after the first preset period of time is completed, the preset capacitor is charged, the gate level may be set to 0V, that is, the drain and the source may be disconnected, the power connection of the drain may be disconnected, and the drain may be connected to only one end of the preset capacitor, so that the potential difference between the drain and the source is equal to the voltage of the preset capacitor, that is, the third level value, and the second preset period of time is allowed to stand. After the second preset period of time is over, a seventh level value of the drain electrode may be detected, the seventh level value may be lower than the third level value, and the seventh level value may be different from the fifth level value due to a degradation of the performance of the field effect transistor.
According to one embodiment of the invention, the performance parameters of the field effect transistor in the first test stage and the performance parameters in the second test stage are obtained, and the durability of the field effect transistor can be evaluated based on the performance parameters.
In step S110, it may be determined whether the performance of the fet is stable, for example, whether the performance of the fet is severely degraded. For example, it may be determined whether the performance of the field effect transistor is severely degraded based on the difference between the detected drain currents in the two test phases.
According to one embodiment of the present invention, step S110 may include: fitting a plurality of second level values under the action of each first level value and drain currents corresponding to the second level values respectively to obtain a first relation function of the drain currents corresponding to each first level value and the second level values; fitting a plurality of sixth level values under the action of each first level value and drain currents corresponding to the sixth level values respectively to obtain a second relation function of the drain currents corresponding to each first level value and the sixth level values; determining a first derivative function of the first relation function and determining a second derivative function of the second relation function; determining a second target level value of which the derivative value is equal to a first threshold value in each first derivative function, and determining a sixth target level value of which the derivative value is equal to the first threshold value in each second derivative function; determining a first target drain current value corresponding to the second target level value in each first relation function, and determining a second target drain current value corresponding to the sixth target level value in each second relation function; fitting a coordinate position formed by a second target level value and a first target drain current value in the plurality of first relation functions to obtain a third relation function, and fitting a coordinate position formed by a sixth target level value and a second target drain current value in the plurality of second relation functions to obtain a fourth relation function; determining an inflection point stability score according to a second target level value and a first target drain current value in a first relation function corresponding to each first level value and a sixth target level value and a second target drain current value in a second relation function corresponding to each first level value, wherein the third relation function and the fourth relation function; determining an output difference score according to the first relation function corresponding to each first level value and the second relation function corresponding to each first level value; and determining the performance stability score according to the inflection point stability score and the output difference score.
According to one embodiment of the present invention, as described above, in the first test stage, after the first level value is set, the second level value is continuously changed, so that different drain currents can be detected, and the drain currents and the second level value can be fitted to obtain a first relationship function of the drain currents and the second level value, where the first relationship function is a first relationship function corresponding to the set first level value. The above steps may be iteratively performed to obtain a first relationship function corresponding to each first level value.
Similarly, in the second test stage, after the first level value is set, the sixth level value is continuously changed, so that different drain currents can be detected, and the drain currents can be fitted with the sixth level value to obtain a second relation function of the drain currents and the sixth level value, wherein the second relation function is a second relation function corresponding to the set first level value. The above steps may be iteratively performed to obtain a second relationship function corresponding to each of the first level values.
According to one embodiment of the present invention, the first relation function and the second relation function may be derived, respectively, to obtain a first derivative function and a second derivative function, respectively, the first derivative function representing a rate of change of the drain current with respect to the second level value, and the second derivative function representing a rate of change of the drain current with respect to the sixth level value. In the case of field effect transistor source and drain conduction, the relationship between drain current and drain level is approximately linear (i.e., there is approximately a fixed resistance value between source and drain), however, the drain level increases to some extent, the rate of increase of drain current slows down, and even no longer increases, in which case the resistance value equivalent to that between source and drain increases. The first threshold value of the first derivative function may be set, after the derivative value of the first derivative function (that is, the first derivative function represents the rate of change of the drain current with respect to the second level value) is equal to the first threshold value, the derivative value is continuously reduced, even equal to 0, and when the derivative value is equal to the first threshold value, the corresponding second level value is the second target level value, so that the second level value is greater than or equal to the second target level value, the linear relationship between the drain current and the drain level is no longer maintained, and the impedance between the source and the drain is no longer fixed, so that the second target level value and the corresponding first target drain current value are inflection points of the first relationship function, and the above manner of determining the inflection points of all the first relationship function may be based on the above manner. Similarly, the inflection points of all the second relationship functions can also be obtained. That is, the second target level value and its corresponding first target drain current value in each first relation function and the sixth target level value and its corresponding second target drain current value in each second relation function are determined.
According to one embodiment of the present invention, the inflection points of the first relationship functions may be set in the same coordinate system (for example, the coordinate system with the abscissa being the drain level and the ordinate being the drain current), and the inflection points of the first relationship functions may be fitted to obtain a third relationship function, and when fitting the inflection points of the first relationship functions, the fitting may be performed using a linear regression method to obtain the third relationship function in the form of a unitary polynomial. Similarly, the inflection points of the second relationship functions may be set in the coordinate system, and the inflection points of the second relationship functions may be fitted by using a linear regression method to obtain a fourth relationship function in the form of a unitary polynomial.
According to one embodiment of the present invention, after obtaining the above multiple relationship functions, performance stability of the fet during the two-stage test may be analyzed to determine whether the performance of the fet in the second test stage is severely degraded relative to the performance of the fet in the first test stage.
According to an embodiment of the present invention, the inflection point is an inflection point in which the impedance between the source and the drain changes from an approximately constant state to an increasing state, that is, the properties of the impedance between the source and the drain of the fet change on both sides of the inflection point, and thus the scene where the application can be performed changes, so that if the inflection point changes greatly, it can be considered that the performance of the fet changes greatly. Thus, it can be determined whether the inflection point remains stable in both test phases.
According to one embodiment of the present invention, determining an inflection point stability score according to a second target level value and a first target drain current value in a first relationship function corresponding to each first level value and a sixth target level value and a second target drain current value in a second relationship function corresponding to each first level value, the third relationship function and the fourth relationship function includes: determining a first slope of the third relationship function and a second slope of a fourth relationship function; the third relation function and the fourth relation function are functions in the form of a unitary polynomial, the first slope is the slope of the unitary polynomial corresponding to the third relation function, and the second slope is the slope of the unitary polynomial corresponding to the fourth relation function; obtaining a first inflection point state vector corresponding to each first level value according to a second target level value and a first target drain current value in a first relation function corresponding to each first level value; obtaining a second inflection point state vector corresponding to each first level value according to a sixth target level value and a second target drain current value in a second relation function corresponding to each first level value; and determining the inflection point stability score according to the first slope, the second slope, the first inflection point state vector and the second inflection point state vector.
According to one embodiment of the invention, the third relationship function and the fourth relationship function are functions in the form of a unitary polynomial, and the first slope of the third relationship function and the second slope of the fourth relationship function may be determined. And the first inflection point state vector for each first level value may be constructed using the coordinates of the inflection point of the first relationship function for each first level value (i.e., the second target level value and the first target drain current value). Similarly, the coordinates of the inflection point of the second relationship function of each first level value (i.e., the sixth target level value and the second target drain current value) may be used to construct a second inflection point state vector for each first level value.
According to one embodiment of the invention, determining the corner stability score from the first slope, the second slope, the first corner state vector, and the second corner state vector comprises: obtaining an inflection point stability score according to equation (1)，
(1) Wherein, the method comprises the steps of, wherein,for the first slope to be the same,for the second slope to be the same,for the first inflection state vector corresponding to the i first level value,for the second inflection state vector corresponding to the ith first level value,for the second target level value corresponding to the ith first level value, The i-th first level value corresponds to the first target drain current value,a sixth target level value corresponding to the i-th first level value,a second target drain current value corresponding to the ith first level value,in order to be at the preset level,for the ith first level value, n is the number of the first level values, i is less than or equal to n, and both i and n are positive integers.
According to one embodiment of the present invention, in the formula (1), the cosine similarity between the first inflection point state vector and the second inflection point state vector corresponding to each first level value may be solved, and the cosine similarity corresponding to each first level value may be weighted and averaged, and the obtained weighted average may represent the average similarity between the inflection point in the first relationship function and the inflection point in the second relationship function of each first level value, where the average similarity is high, and if the overall change of the inflection point is considered to be small, the performance of the field-effect transistor is relatively stable in the two-stage test, and otherwise, the average similarity is low,the overall change of the inflection point is considered to be large, and the performance of the field effect transistor is unstable in the two-stage test. In the weighted average process, the weight isWherein, the method comprises the steps of, wherein,for the preset level, the common level of the grid electrode in the use process of the field effect transistor can be used, and in the weight, if the first level value is different from the preset level If the difference between the first level value and the preset level is smaller, the weight is larger, namely, a higher weight can be given to the cosine similarity corresponding to the first level value close to the preset level, so that when the integral change of the inflection point is determined, whether the inflection point corresponding to the common grid level has great change is judged in an important way, and therefore whether the performance of the field effect transistor has great change is reflected in most of use scenes more accurately.
In accordance with one embodiment of the present invention, in equation (1), the coefficient may also be multiplied by a weighted averageThe coefficient may represent the proximity between the first slope and the second slope, the difference between the first slope and the second slopeThe larger the coefficient is, the smaller the coefficient is, and conversely, the smaller the difference between the first slope and the second slope is, the larger the coefficient is. The coefficients may reflect the overall proximity of the inflection point of each first relationship function and the inflection point of each second relationship function. The larger the coefficient is, the higher the overall approach degree of the inflection point is, the performance of the field effect transistor is kept relatively stable in the two-stage test, the smaller the coefficient is, the lower the overall approach degree of the inflection point is, and the performance of the field effect transistor is larger in the two-stage test.
By the method, the average similarity of inflection points corresponding to the first level values can be determined, and the inflection points can be weighted through the preset level values and the first level values, so that the performance stability of the field effect transistor in most use scenes can be accurately reflected, the overall performance stability of the field effect transistor can be represented through the approaching degree of the first slope and the second slope, and the accuracy and objectivity of the inflection point stability scoring can be improved.
According to an embodiment of the present invention, in addition to evaluating the stability of the inflection point, a gap between the first relationship function and the second relationship function may be determined, so as to determine whether the relationship between the drain current and the drain level is stable in the two-stage test.
According to one embodiment of the present invention, determining an output difference score according to a first relationship function corresponding to each first level value and a second relationship function corresponding to each first level value includes: determining an output variance score according to equation (2)，（2）
Where n is the number of first level values,in order to be at the preset level,for the ith first level value, i is less than or equal to n, i and n are positive integers,as a first relation function corresponding to the ith first level value, As a second relation function corresponding to the ith first level value,for the value of the sixth level of the j-th,j is any positive integer less than or equal to the total number of the sixth level values, k is any positive integer less than or equal to the total number of the second level values,for the minimum value of the set of all sixth level values and second level values,for the maximum value in the set of all the sixth level values and the second level values, U is the argument of the first relation function and the second relation function, and≤U≤。
according to one embodiment of the present invention, in the formula (2), the integral value of the gap between the first relation function and the second relation function corresponding to each first level value may be solved, and the total gap of the drain currents corresponding to the drain levels may be obtained, that is, the total gap of the relation between the drain currents and the drain levels. The lower integration limit is the minimum value of the set of the sixth level value and the second level value, and the upper integration limit is the maximum value of the set of the sixth level value and the second level value, and in an example, each sixth level value is equal to each second level value, so the upper integration limit is the maximum value of the second level value, and the lower integration limit is the minimum value of the second level value. Similarly to the above, the total difference of the relationship between the drain current and the drain level corresponding to each first level value may be weighted, so as to obtain a weighted average value of the total difference, so that when determining the overall change of the relationship between the drain current and the drain level, it is important to determine whether the relationship between the drain current and the drain level corresponding to the commonly used gate level has a significant change, so as to more accurately reflect whether the performance of the field effect transistor has a significant change in most usage scenarios. After the weighted summation, an output difference score can be obtained, wherein the higher the output difference score is, the larger the change of the relation between the drain current and the drain level in the two-stage test is, the worse the performance stability of the field effect transistor is, and otherwise, the lower the output difference score is, the smaller the change of the relation between the drain current and the drain level in the two-stage test is, and the better the performance stability of the field effect transistor is.
By the method, the total difference of the relation between the drain current and the drain level in two test stages can be determined, and the total difference can be weighted, so that the stability of the field effect transistor in most use scenes is reflected more accurately, and the accuracy and objectivity of the output difference score are improved.
According to one embodiment of the invention, the knee stability score and the output difference score may be utilized to determine a performance stability score, for example, a difference between 1 and the output difference score may be determined and a weighted sum of the difference and the knee stability score may be determined as the performance stability score, thereby more accurately reflecting the performance stability of the fet in both test phases using both aspects of the stability of the knee and the stability of the relationship between drain current and drain level.
According to an embodiment of the present invention, in addition to the above performance stability score, it may be evaluated whether the data retention of the fet can be kept stable in two test phases in step S111. The first level value includes 0V, and step S111 may include: determining a first theoretical current in the case that the drain level is a third level value according to a first relation function in the case that the first level value is 0V; determining a second theoretical current in the case that the drain level is a third level value according to a second relation function in the case that the first level value is 0V; and determining the data retention rating according to the fifth level value, the third level value, the seventh level value, the first theoretical current and the second theoretical current.
According to an embodiment of the present invention, the drain current in the case where the drain level is the third level value may be determined as the first theoretical current in the first relational function in the case where the first level value is 0V, and similarly, the drain current in the case where the drain level is the third level value may be determined as the second theoretical current in the second relational function in the case where the first level value is 0V.
According to one embodiment of the present invention, when the first level value is 0V, the source and the drain are close to the off state, only weak current (for example, the first theoretical current in the first test stage and the second theoretical current in the second test stage) exists, and when the drain is connected to only the preset capacitor with the voltage equal to the third level value, the weak current releases the charge in the capacitor and reduces the voltage in the capacitor.
According to one embodiment of the present invention, determining the data retention score from the fifth level value, the third level value, the seventh level value, and the theoretical current comprises:
obtaining a data retention score K according to formula (3),
（3）
wherein, the liquid crystal display device comprises a liquid crystal display device,at the value of the seventh level, At the value of the fifth level,at the value of the third level,as a result of the first theoretical current flow,c is the capacitance value of the preset capacitor for the second theoretical current,is the firstTwo preset time periods.
According to one embodiment of the invention, the fifth level value and the seventh level value are respectively the measured level value in the first test phase and the measured level value of the drain in the second test phase, which, in the first test phase,in order that the theoretical voltage value of the capacitor after the second preset period is also the theoretical level value of the drain electrode in the first test stage when the first theoretical current releases the charge in the preset capacitor, the fifth level value may not be equal to the theoretical level value, for example, the current of the drain electrode may be different from the first theoretical current, or other leakage charge exists, so that the fifth level value may not be equal to the theoretical level value. Thus, a ratio between the measured level value and the theoretical level value of the drain of the first test stage may be determined, which may be indicative of the charge retention capability of the field effect transistor in the off state during the first test stage. In a similar manner to that described above,in order that the theoretical voltage value of the capacitor after the second preset period of time is also the theoretical level value of the drain electrode in the second test stage when the second theoretical current releases the charge in the preset capacitor, the seventh level value may not be equal to the theoretical level value, for example, the current of the drain electrode may be different from the second theoretical current, or other leakage charge exists, which results in that the seventh level value may not be equal to the theoretical level value. Thus, a ratio between the measured level value and the theoretical level value of the drain of the second test phase may be determined, which may be indicative of the charge retention capability of the field effect transistor in the off state during the second test phase. Further, the ratio between the charge holding capacity of the field effect transistor in the off state in the second test stage and the charge holding capacity of the field effect transistor in the off state in the first test stage can be solved to obtain a data holding capacity score which can represent the charge holding capacity of the field effect transistor in the two test stages Whether the holding capacity is stable or not, the higher the data holding capacity score, the no obvious change of the holding capacity of the field effect transistor for the electric charge is generated in two test stages, namely, the holding capacity for the electric charge is stable, whereas the lower the data holding capacity score, the obvious change of the holding capacity of the field effect transistor for the electric charge is generated in two test stages, namely, the holding capacity for the electric charge is unstable.
By the method, the holding capacity of the field effect tube to the charges in the preset capacitor in the two test stages can be respectively determined, so that whether the holding capacity of the field effect tube to the charges is obviously changed or not is judged, and the accuracy and objectivity of data holding capacity scoring are improved.
According to one embodiment of the present invention, in step S112, the performance stability score and the data retention score may be weighted and summed to obtain a durability score for the fet, thereby reflecting the durability of the fet from both the performance stability of the fet and the stability of the retention to the charge.
According to the method for testing the durability of the semiconductor device, the drain current under the condition that the grid level is a plurality of level values can be obtained before and after the field effect tube is connected into the preset circuit, so that the change of the drain current before and after the grid level is connected into the preset circuit is determined, further whether the performance of the field effect tube is changed is determined, the performance change condition of the field effect tube can be rapidly determined, the durability of the field effect tube can be determined based on the performance change condition, and further whether the charge leakage condition of the field effect tube is changed before and after the grid level is connected into the preset circuit can be determined based on the voltage change of the capacitor connected between the drain and the source, so that the data retention force of the field effect tube is judged, the durability of the field effect tube can be determined from a plurality of dimensions, and the accuracy of durability evaluation is improved. When the performance stability of the field effect tube is determined, the inflection point stability score can be determined, the average similarity of inflection points corresponding to each first level value can be determined, and weighting can be carried out through the preset level and the first level value, so that the performance stability of the field effect tube in most use scenes can be accurately reflected, the overall performance stability of the field effect tube can be represented through the approaching degree of the first slope and the second slope, and the accuracy and objectivity of the inflection point stability score can be improved. The output difference score can be determined, the total difference of the relation between the drain current and the drain level in two test stages can be determined, and the total difference can be weighted, so that the stability of the field effect transistor in most use scenes can be reflected more accurately, and the accuracy and objectivity of the output difference score are improved. When the data retention of the field effect tube is determined, the retention of the field effect tube on the charges in the preset capacitor in two test stages can be respectively determined, so that whether the retention of the field effect tube on the charges is obviously changed or not is judged, and the accuracy and objectivity of the data retention scoring are improved.
Fig. 2 schematically illustrates a schematic diagram of a semiconductor device endurance test system according to an embodiment of the present invention, the system including:
a first setting module 101, configured to set a gate level of the field effect transistor to a plurality of first level values in a first test stage;
the first measurement module 102 is configured to set the drain level to a plurality of second level values under the action of each first level value, and measure a corresponding drain current;
a first charging module 103, configured to connect a drain electrode and a source electrode of the field effect transistor to two ends of a preset capacitor, respectively, set a drain level to a third level value, set a gate level to a fourth level value, and stand for a first preset period of time, where the fourth level value is higher than the third level value;
a first obtaining module 104, configured to set a gate level to 0V, disconnect a power supply of the drain, and obtain a fifth level value of the drain after standing for a second preset period of time;
an operation module 105, configured to connect the field effect transistor to a preset circuit, and operate for a third preset period of time, where in the preset circuit, a voltage at a connection position of a gate and a drain of the field effect transistor changes according to a preset frequency and amplitude;
A second setting module 106, configured to set the gate level of the fet to a plurality of first level values in a second testing stage after the third preset period;
a second measurement module 107, configured to set the drain level to a plurality of sixth level values under the action of each first level value, and measure a corresponding drain current;
the second charging module 108 is configured to connect the drain and the source of the field effect transistor to two ends of a preset capacitor, set the drain level to a third level value, set the gate level to a fourth level value, and stand for a first preset period of time;
a second obtaining module 109, configured to set the gate level to 0, disconnect the power supply of the drain, and obtain a seventh level value of the drain after standing for a second preset period of time;
a performance stability scoring module 110, configured to obtain a performance stability score of the fet according to the first level value, the second level value, a drain current corresponding to the second level value, the sixth level value, and a drain current corresponding to the sixth level value;
the data retention rating module 111 is configured to obtain a data retention rating of the fet according to the fifth level value, the third level value, and the seventh level value;
And a durability scoring module 112, configured to obtain a durability score of the fet according to the performance stability score and the data retention score.
Claims (8)
1. A method for testing endurance of a semiconductor device, comprising:
setting the grid level of the field effect transistor to a plurality of first level values in a first test stage;
setting the drain level as a plurality of second level values under the action of each first level value respectively, and measuring the corresponding drain current;
the drain electrode and the source electrode of the field effect transistor are respectively connected to two ends of a preset capacitor, the drain electrode level is set to be a third level value, the grid electrode level is set to be a fourth level value, and the first preset time period is kept stand, wherein the fourth level value is higher than the third level value;
setting the grid level to 0V, disconnecting the power supply of the drain electrode, and obtaining a fifth level value of the drain electrode after standing for a second preset time period;
connecting the field effect tube to a preset circuit, and operating for a third preset time period, wherein in the preset circuit, the voltage at the connection part of the grid electrode and the drain electrode of the field effect tube changes according to preset frequency and amplitude;
Setting the grid level of the field effect transistor to a plurality of first level values in a second testing stage after the third preset time period;
setting the drain level to a plurality of sixth level values under the action of each first level value respectively, and measuring the corresponding drain current;
the drain electrode and the source electrode of the field effect transistor are respectively connected to two ends of a preset capacitor, the level of the drain electrode is set to be a third level value, the level of the grid electrode is set to be a fourth level value, and the first preset time period is kept stand;
setting the grid level to 0, disconnecting the power supply of the drain electrode, and obtaining a seventh level value of the drain electrode after standing for a second preset time period;
obtaining a performance stability score of the field effect transistor according to the first level value, the second level value, the drain current corresponding to the second level value, the sixth level value and the drain current corresponding to the sixth level value;
obtaining a data retention rating of the field effect tube according to the fifth level value, the third level value and the seventh level value;
and obtaining the durability score of the field effect tube according to the performance stability score and the data retention score.
2. The method according to claim 1, wherein obtaining the performance stability score of the field effect transistor based on the first level value, the second level value, a drain current corresponding to the second level value, the sixth level value, and a drain current corresponding to the sixth level value, comprises:
fitting a plurality of second level values under the action of each first level value and drain currents corresponding to the second level values respectively to obtain a first relation function of the drain currents corresponding to each first level value and the second level values;
fitting a plurality of sixth level values under the action of each first level value and drain currents corresponding to the sixth level values respectively to obtain a second relation function of the drain currents corresponding to each first level value and the sixth level values;
determining a first derivative function of the first relation function and determining a second derivative function of the second relation function;
determining a second target level value of which the derivative value is equal to a first threshold value in each first derivative function, and determining a sixth target level value of which the derivative value is equal to the first threshold value in each second derivative function;
Determining a first target drain current value corresponding to the second target level value in each first relation function, and determining a second target drain current value corresponding to the sixth target level value in each second relation function;
fitting a coordinate position formed by a second target level value and a first target drain current value in the plurality of first relation functions to obtain a third relation function, and fitting a coordinate position formed by a sixth target level value and a second target drain current value in the plurality of second relation functions to obtain a fourth relation function;
determining an inflection point stability score according to a second target level value and a first target drain current value in a first relation function corresponding to each first level value and a sixth target level value and a second target drain current value in a second relation function corresponding to each first level value, wherein the third relation function and the fourth relation function;
determining an output difference score according to the first relation function corresponding to each first level value and the second relation function corresponding to each first level value;
and determining the performance stability score according to the inflection point stability score and the output difference score.
3. The method of claim 2, wherein determining the inflection point stability score based on the second target level value and the first target drain current value in the first relationship function for each first level value and the sixth target level value and the second target drain current value in the second relationship function for each first level value, the third relationship function and the fourth relationship function comprises:
determining a first slope of the third relationship function and a second slope of a fourth relationship function;
obtaining a first inflection point state vector corresponding to each first level value according to a second target level value and a first target drain current value in a first relation function corresponding to each first level value;
obtaining a second inflection point state vector corresponding to each first level value according to a sixth target level value and a second target drain current value in a second relation function corresponding to each first level value;
and determining the inflection point stability score according to the first slope, the second slope, the first inflection point state vector and the second inflection point state vector.
4. The semiconductor device endurance test method of claim 3, wherein determining the inflection point stability score from the first slope, the second slope, the first inflection point state vector, and the second inflection point state vector comprises:
According to the formulaObtain inflection point stability score +.>Wherein->For the first slope,/>For the second slope, +.>For the first inflection state vector corresponding to the ith first level value, +.>For the second inflection state vector corresponding to the ith first level value, +.>For the second target level value corresponding to the ith first level value,/th>A first target drain current value corresponding to the ith first level value,/for>For the sixth target level value corresponding to the ith first level value,/th>A second target drain current value corresponding to the ith first level value,for a preset level, ++>For the ith first level value, n is the number of the first level values, i is less than or equal to n, and both i and n are positive integers.
5. The method of claim 3, wherein determining the output difference score based on the first relationship function for each first level value and the second relationship function for each first level value comprises:
according to the formula
Determining an output difference score->Wherein n is the number of first level values, +.>For a preset level, ++>For the ith first level value, i is less than or equal to n, i and n are positive integers, +.>For the first relation function corresponding to the ith first level value, +. >For the second relation function corresponding to the ith first level value, +.>For the j sixth level value, +.>J is any positive integer less than or equal to the total number of the sixth level values, k is any positive integer less than or equal to the total number of the second level values,for all the sets of sixth level values and second level valuesMinimum of the value of the sum of the values,for the maximum value in the set of all sixth level values and second level values, U is the argument of the first and second relation functions, and +.>≤U≤/>。
6. The method for testing endurance of a semiconductor device as claimed in claim 2, wherein the first level value includes 0V,
wherein obtaining the data retention rating of the fet according to the fifth level value, the third level value, and the seventh level value, comprises:
determining a first theoretical current in the case that the drain level is a third level value according to a first relation function in the case that the first level value is 0V;
determining a second theoretical current in the case that the drain level is a third level value according to a second relation function in the case that the first level value is 0V;
and determining the data retention rating according to the fifth level value, the third level value, the seventh level value, the first theoretical current and the second theoretical current.
7. The method of claim 6, wherein determining the data retention score based on the fifth level value, the third level value, the seventh level value, and the theoretical current comprises:
according to the formula
Obtaining a data retention ratingDivide K, wherein->At the value of the seventh level,for the fifth level value, +.>For the third level value, +.>For the first theoretical current, +.>For the second theoretical current, C is the capacitance value of the preset capacitor, +.>For a second preset period of time.
8. A durability test system for a semiconductor device, comprising:
the first setting module is used for setting the grid level of the field effect transistor to a plurality of first level values in a first test stage;
the first measuring module is used for setting the drain electrode level to a plurality of second level values under the action of each first level value respectively and measuring the corresponding drain electrode current;
the first charging module is used for respectively connecting the drain electrode and the source electrode of the field effect transistor to two ends of a preset capacitor, setting the level of the drain electrode as a third level value, setting the level of the grid electrode as a fourth level value, and standing for a first preset time period, wherein the fourth level value is higher than the third level value;
The first acquisition module is used for setting the grid level to 0V, disconnecting the power supply of the drain electrode, and acquiring a fifth level value of the drain electrode after standing for a second preset time period;
the operation module is used for connecting the field effect transistor to a preset circuit and operating for a third preset time period, wherein in the preset circuit, the voltage at the junction of the grid electrode and the drain electrode of the field effect transistor changes according to preset frequency and amplitude;
the second setting module is used for setting the grid level of the field effect transistor to a plurality of first level values in a second testing stage after the third preset time period;
the second measuring module is used for setting the drain level to a plurality of sixth level values under the action of each first level value respectively and measuring the corresponding drain current;
the second charging module is used for respectively connecting the drain electrode and the source electrode of the field effect transistor to two ends of a preset capacitor, setting the level of the drain electrode as a third level value, setting the level of the grid electrode as a fourth level value, and standing for a first preset time period;
the second acquisition module is used for setting the grid level to 0, disconnecting the power supply of the drain electrode, and acquiring a seventh level value of the drain electrode after standing for a second preset time period;
A performance stability scoring module, configured to obtain a performance stability score of the fet according to the first level value, the second level value, a drain current corresponding to the second level value, the sixth level value, and a drain current corresponding to the sixth level value;
the data retention rating module is used for obtaining the data retention rating of the field effect transistor according to the fifth level value, the third level value and the seventh level value;
and the durability scoring module is used for obtaining the durability score of the field effect tube according to the performance stability score and the data retention score.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311152317.2A CN116879705B (en) | 2023-09-08 | 2023-09-08 | Method and system for testing durability of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311152317.2A CN116879705B (en) | 2023-09-08 | 2023-09-08 | Method and system for testing durability of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN116879705A true CN116879705A (en) | 2023-10-13 |
| CN116879705B CN116879705B (en) | 2023-11-07 |
Family
ID=88272200
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202311152317.2A Active CN116879705B (en) | 2023-09-08 | 2023-09-08 | Method and system for testing durability of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN116879705B (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117269711A (en) * | 2023-11-20 | 2023-12-22 | 江苏摩派半导体有限公司 | IGBT module performance test method and system |
Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2001289904A (en) * | 2000-04-06 | 2001-10-19 | Fujitsu Ltd | Evaluating method and evaluating device for semiconductor device |
| CN1956098A (en) * | 2005-08-02 | 2007-05-02 | 株式会社瑞萨科技 | Semiconductor storage device |
| CN101223640A (en) * | 2005-07-14 | 2008-07-16 | 美光科技公司 | High density nand non-volatile memory device |
| CN107345996A (en) * | 2017-07-11 | 2017-11-14 | 北京华峰测控技术有限公司 | FET test circuit and method of testing |
| US20180067512A1 (en) * | 2015-02-17 | 2018-03-08 | Vanchip (Tianjin) Technology Co., Ltd. | Adaptive low-dropout regulator having wide voltage endurance range, chip and terminal |
| US20190056448A1 (en) * | 2017-08-16 | 2019-02-21 | Infineon Technologies Ag | Testing mos power switches |
| CN113092975A (en) * | 2021-03-10 | 2021-07-09 | 上海华虹宏力半导体制造有限公司 | Source-drain breakdown voltage testing method of power MOS device |
| CN114414974A (en) * | 2022-01-17 | 2022-04-29 | 长鑫存储技术有限公司 | Method, apparatus, device and storage medium for testing semiconductor device |
| CN116540044A (en) * | 2022-01-26 | 2023-08-04 | 华为数字能源技术有限公司 | Semiconductor test circuit and method |
-
2023
- 2023-09-08 CN CN202311152317.2A patent/CN116879705B/en active Active
Patent Citations (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2001289904A (en) * | 2000-04-06 | 2001-10-19 | Fujitsu Ltd | Evaluating method and evaluating device for semiconductor device |
| CN101223640A (en) * | 2005-07-14 | 2008-07-16 | 美光科技公司 | High density nand non-volatile memory device |
| CN1956098A (en) * | 2005-08-02 | 2007-05-02 | 株式会社瑞萨科技 | Semiconductor storage device |
| JP2012053982A (en) * | 2005-08-02 | 2012-03-15 | Renesas Electronics Corp | Semiconductor memory device |
| US20180067512A1 (en) * | 2015-02-17 | 2018-03-08 | Vanchip (Tianjin) Technology Co., Ltd. | Adaptive low-dropout regulator having wide voltage endurance range, chip and terminal |
| CN107345996A (en) * | 2017-07-11 | 2017-11-14 | 北京华峰测控技术有限公司 | FET test circuit and method of testing |
| US20190056448A1 (en) * | 2017-08-16 | 2019-02-21 | Infineon Technologies Ag | Testing mos power switches |
| CN113092975A (en) * | 2021-03-10 | 2021-07-09 | 上海华虹宏力半导体制造有限公司 | Source-drain breakdown voltage testing method of power MOS device |
| CN114414974A (en) * | 2022-01-17 | 2022-04-29 | 长鑫存储技术有限公司 | Method, apparatus, device and storage medium for testing semiconductor device |
| CN116540044A (en) * | 2022-01-26 | 2023-08-04 | 华为数字能源技术有限公司 | Semiconductor test circuit and method |
Non-Patent Citations (1)
| Title |
|---|
| 曹钟林;: "MOS场效应管特性与参数测试实验电路设计", 无锡商业职业技术学院学报, vol. 16, no. 03, pages 86 - 89 * |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117269711A (en) * | 2023-11-20 | 2023-12-22 | 江苏摩派半导体有限公司 | IGBT module performance test method and system |
| CN117269711B (en) * | 2023-11-20 | 2024-01-30 | 江苏摩派半导体有限公司 | IGBT module performance test method and system |
Also Published As
| Publication number | Publication date |
|---|---|
| CN116879705B (en) | 2023-11-07 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN116879705B (en) | Method and system for testing durability of semiconductor device | |
| CN106646256B (en) | Battery capacity calculating method | |
| US20220393515A1 (en) | Wireless charging circuit, wireless charging method, device, and system | |
| CN106529102B (en) | AlGaN/GaN HEMT small signal model and parameter extraction method thereof | |
| WO2019242472A1 (en) | Method and device for estimating battery charge status | |
| US10734689B2 (en) | Method and system for reconstructing complete charging-discharging data based on partial charging-discharging data of battery | |
| US20120065920A1 (en) | Evaluation method, evaluation apparatus, and simulation method of semiconductor device | |
| EP0887654A2 (en) | Method for detecting working condition of non-aqueous electrolyte secondary batteries | |
| US11774470B2 (en) | Load detection system and load detection method thereof | |
| CN113359044B (en) | Method, device and equipment for measuring residual capacity of battery | |
| US20210293891A1 (en) | Method of determining an aging level of a battery | |
| CN101303390B (en) | Method for judging MOS device performance degeneration | |
| CN110456152B (en) | Method and system for testing resistivity of epitaxial layer and terminal equipment | |
| US7548067B2 (en) | Methods for measuring capacitance | |
| US6377067B1 (en) | Testing method for buried strap and deep trench leakage current | |
| US11353505B2 (en) | Differential clock cross point detection circuit and detection method | |
| KR101166077B1 (en) | Method for generating state-of-charge standard information of secondary battery and method for estimating state-of-charge of secondary battery using state-of-charge standard information | |
| WO2021030934A1 (en) | Battery pack, battery current measurement circuit system, and battery current measurement apparatus | |
| CN116068362B (en) | Test method and device | |
| JP3385780B2 (en) | Method for deriving regression equation for estimating capacity of Ni-Cd battery for trickle | |
| CN116243132B (en) | Detection method, device and equipment | |
| US11703537B2 (en) | Method and apparatus for analysis of interface state of MIS-HEMT device | |
| CN117269711B (en) | IGBT module performance test method and system | |
| CN107228986A (en) | A kind of capacitor mismatch detection circuit and method | |
| CN112366148B (en) | Substrate concentration determination method, substrate concentration determination device, computer equipment and readable storage medium |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |