CN105336360B - The control circuit and SRAM memory of SRAM storage arrays - Google Patents
The control circuit and SRAM memory of SRAM storage arrays Download PDFInfo
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Abstract
A kind of control circuit and SRAM memory of SRAM storage arrays, control circuit include：First PMOS tube, conducting control unit and at least one drop-down metal-oxide-semiconductor；The source electrode of first PMOS tube is suitable for input first voltage；The drain electrode of the drop-down metal-oxide-semiconductor is all connected with the drain electrode of first PMOS tube, and the source electrode of the drop-down metal-oxide-semiconductor is adapted to input second voltage, and the voltage value of the second voltage is less than the voltage value of first voltage；The conducting control unit is suitable for before the SRAM storage arrays enter working condition and execute write operation, and it is in the conduction state in the given time to control all or part of drop-down metal-oxide-semiconductor.
Description
Technical field
The present invention relates to memory area more particularly to a kind of control circuits and SRAM memory of SRAM storage arrays.
Background technology
Static RAM (SRAM), which has, is not needing the newer advantageous refinements for keeping data.Figure
1 is a kind of existing storage array power consumption management and control circuit diagram.2nd PMOS closes the grid of P2 and drain electrode connects, and is equivalent to diode work(
Energy.When Sleep signals and Shut Down signals are all logical zero, the first PMOS tube P1 and third PMOS tube P3 are all in conducting
The conducting of state, the first PMOS tube P1 may make the voltage of VA points to be equal to or very close to supply voltage VDD, store battle array at this time
Row 101 enter working condition, can perform read-write operation.
When Sleep signals are logic 1, and Shut Down signals are logical zero, the first PMOS tube P1 is in cut-off state, the
Three PMOS tube P3 are in the conduction state.Storage array 101 in a dormant state, can keep the data of its storage at this time, but not
Read-write operation can be executed.
When Sleep signals and Shut Down signals are all logic 1, the first PMOS tube P1 and third PMOS tube P3 locate
In cut-off state, storage array 101 loses voltage/current supply, and into closed state, under the state, storage array 101 is not
Can read-write operation and its storage data can all lose.
SRAM memory cell may include the transistor of different number, and usually be named by the quantity of transistor, for example,
Six transistors (6T) SRAM, eight transistors (8T) SRAM etc..Transistor is usually formed for storing the data latches of position.It can be with
Extra transistor is added to control the access to transistor.SRAM memory cell is generally arranged to the array with row and column.
In general, the often row of SRAM memory cell is connected to wordline, determine that current sram cell is selected and unselected.SRAM is deposited
The each column of storage unit is connected to bit line (or a pair of bit lines), be used to store position to SRAM memory cell or deposit from SRAM
Storage unit reads position.
Negative bit line technology be used to improve the unit write capability in low supply voltage, especially when inhibition word line voltage
When.It is the 6T SRAM memory cells for being connected to negative-voltage generator 120 with reference to figure 2.Assuming that shown in logical zero will be written to
SRAM memory cell 100 in, to which bit line BL carrying indicates that the low-voltage of logic low and bit line BLB carryings indicate logic
High high voltage.Before executing write operation, node 110 is in high voltage, while node 112 is in low-voltage.In order to patrol
0 write-in SRAM memory cell is collected, negative voltage (for example, -100mV) is added on bit line BL.Negative voltage leads to node 110 and bit line
The increase of voltage difference between BL.To which write operation becomes easier to.
Negative-voltage generator 120 generate shown in negative voltage, negative-voltage generator 120 include receive supply voltage VDD and
Generate the charge pump of negative voltage.The negative bit line that Fig. 3 diagrammatically illustrates supply voltage VDD and generated by negative-voltage generator 120
Relationship between voltage.If supply voltage VDD is lower, the amplitude of negative voltage can also reduce.In order to generate lower negative electricity
It presses, the capacitor in negative-voltage generator 120 needs bigger, thus it requires the chip area of bigger.Also, it realizes and bears bit line skill
Art cost is very high.
Invention content
Problems solved by the invention be needed for the execution write operation of existing SRAM storage arrays it is of high cost, difficulty is big.
To solve the above problems, the present invention provides a kind of control circuit of SRAM storage arrays, including：First PMOS tube,
Control unit and at least one drop-down metal-oxide-semiconductor is connected；
The source electrode of first PMOS tube is suitable for input first voltage；
The drain electrode of the drop-down metal-oxide-semiconductor is all connected with the drain electrode of first PMOS tube, and the source electrode of the drop-down metal-oxide-semiconductor is suitable
In input second voltage, the voltage value of the second voltage is less than the voltage value of first voltage；
The conducting control unit is suitable for before the SRAM storage arrays enter working condition and execute write operation, control
All or part of drop-down metal-oxide-semiconductor is in the conduction state in the given time.
Optionally, the quantity and size of the drop-down metal-oxide-semiconductor in the conduction state are executed with the SRAM storage arrays
Program voltage needed for write operation is related.
Optionally, the predetermined time is related to the program voltage needed for SRAM storage arrays execution write operation.
Optionally, the conducting control unit includes：Signal generation unit；
The signal generation unit is suitable for before the SRAM storage arrays enter working condition and execute write operation, generates
The pulse signal for keeping the drop-down metal-oxide-semiconductor in the conduction state
The grid of the drop-down metal-oxide-semiconductor is suitable for inputting the pulse signal that the signal generation unit generates.
Optionally, the conducting control unit includes：Signal generation unit and at least one storbing gate pipe, the storbing gate
Quantity it is identical as the drop-down quantity of metal-oxide-semiconductor；
The signal generation unit is suitable for before the SRAM storage arrays enter working condition and execute write operation, generates
The pulse signal for keeping the drop-down metal-oxide-semiconductor in the conduction state；
The output end of the storbing gate and the grid of the drop-down metal-oxide-semiconductor connect one to one, the input of the storbing gate
End is suitable for inputting the pulse signal that the signal generation unit generates.
Optionally, the conducting control unit further includes selecting unit, and the selecting unit is suitable for control section storbing gate
In can transmission state.
Optionally, the conducting control unit includes：Signal generation unit and at least one switch metal-oxide-semiconductor, the switch
The quantity of metal-oxide-semiconductor is identical as the drop-down quantity of metal-oxide-semiconductor；
Each drop-down metal-oxide-semiconductor inputs the second voltage by a switch metal-oxide-semiconductor；
The signal generation unit is suitable for before the SRAM storage arrays enter working condition and execute write operation, generates
The pulse signal for keeping the drop-down metal-oxide-semiconductor in the conduction state；
The grid of the drop-down metal-oxide-semiconductor is suitable for inputting the pulse signal that the signal generation unit generates.
Optionally, the conducting control unit further includes selecting unit, and the selecting unit is suitable for control section switch MOS
It manages in the conduction state.
Optionally, the signal generation unit includes：Phase inverter, delay circuit and OR-NOT circuit；
The input terminal of the phase inverter connects the grid of the input terminal and first PMOS tube of the delay circuit, described
The output end of phase inverter connects the first input end of the OR-NOT circuit；
The output end of the delay circuit connects the second input terminal of the OR-NOT circuit, and the delay circuit is suitable for prolonging
When time be the predetermined time；
The output end of the OR-NOT circuit connects the grid of the drop-down metal-oxide-semiconductor.
The embodiment of the present invention also provides a kind of SRAM memory, including the control circuit of above-mentioned SRAM storage arrays and
SRAM storage arrays, the control circuit of the SRAM storage arrays are adapted to provide for the SRAM storage arrays and execute needed for write operation
Program voltage.
Optionally, the storage array includes the storage unit being arranged in array, and the storage unit is 6T storage units
Or 8T storage units.
Compared with prior art, the control circuit of the SRAM storage arrays of technical scheme of the present invention can reduce execution and write
The program voltage of operation, not only reduces energy consumption, also improves the program capability of storage array, and without using bearing bit line skill
Art reduces cost, reduces chip area.
Description of the drawings
Fig. 1 is existing storage array power consumption management and control circuit diagram；
Fig. 2 is the structural schematic diagram of existing SRAM memory；
Fig. 3 is that existing bit line writes V diagram；
Fig. 4 is the control circuit schematic diagram of SRAM storage arrays of the present invention；
Fig. 5 is a structural schematic diagram of present invention conducting control unit；
Fig. 6 is the waveform correlation schematic diagram of the present invention；
Fig. 7 is another structural schematic diagram of present invention conducting control unit；
Fig. 8 is the another structural schematic diagram of present invention conducting control unit.
Specific implementation mode
To make the above purposes, features and advantages of the invention more obvious and understandable, below in conjunction with the accompanying drawings to the present invention
Specific embodiment be described in detail.
As shown in figure 4, the embodiment of the present invention provides a kind of control circuit of SRAM storage arrays 1, including：First PMOS tube
P11, conducting control unit 2 and at least one drop-down metal-oxide-semiconductor.The present embodiment is that m is done for example, m with the quantity for pulling down metal-oxide-semiconductor
A drop-down metal-oxide-semiconductor includes m-th of drop-down metal-oxide-semiconductor Nm of the 1st drop-down metal-oxide-semiconductor N1.....
The source electrode of first PMOS tube P11 is suitable for input first voltage VDD.
All the drain electrode of drop-down metal-oxide-semiconductor is all connected with the drain electrode of the first PMOS tube P11, and the source electrode for all pulling down metal-oxide-semiconductor is suitable
It is less than the voltage value of first voltage VDD in the voltage value of input second voltage GND, second voltage GND.That is, the 1st drop-down MOS
The drain electrode of pipe N1 to m-th drop-down metal-oxide-semiconductor Nm is all connected with the drain electrode of the first PMOS tube P11, and the 1st pulls down metal-oxide-semiconductor N1 to m-th
The source electrode of drop-down metal-oxide-semiconductor Nm is adapted to input second voltage GND.The first voltage VDD can be supply voltage, second voltage
GND can be ground voltage.
Be connected control unit 2 be suitable for SRAM storage arrays 1 enter working condition and execute write operation before, control all or
Part drop-down metal-oxide-semiconductor is in the conduction state in the given time.
SRAM storage arrays 1 include the storage unit being arranged in array, and Fig. 1 is said by taking the storage unit of a 6T structure as an example
The connection type of bright storage unit and control circuit.Storage unit includes：Second PMOS tube MP11, third PMOS tube MP12,
One NMOS tube MN1, the second NMOS tube MN2, third NMOS tube MN3 and the 4th NMOS tube MN4.
The source electrode of the source electrode connection third PMOS tube MP12 of second PMOS tube MP11 is simultaneously suitable for inputting SRAM storage arrays 1
The program voltage (VDDC) that control circuit provides.The grid of second PMOS tube MP11 connects the grid of the first NMOS tube MN1, third
The drain electrode of PMOS tube MP12, the drain electrode of the 4th NMOS tube MN4 and the second NMOS tube MN2 drain electrode.The grid of third PMOS tube MP12
Pole connects the drain electrode of grid, the second PMOS tube MP11, the drain electrode of the first NMOS tube MN1 and the first NMOS of the 4th NMOS tube MN4
The source electrode of pipe MN1.The source electrode of first NMOS tube MN1 connects the source electrode of the 4th NMOS tube MN4.The grid of first NMOS tube MN1 and
The drain electrode of grid connection the wordline WL, the first NMOS tube MN1 of second NMOS tube MN2 connect the first bit line BL, the second NMOS tube MN2
Source electrode connect the second bit line BLB.
The data of the drain electrode of second PMOS tube MP11 and the drain electrode of third PMOS tube MP12 for preserving write-in.Assuming that second
The drain electrode of PMOS tube MP11 has saved logic 1, and the logical zero of the drain electrode preservation of third PMOS tube MP12 now needs to execute write operation,
Logical zero is written to the drain electrode of the second PMOS tube MP11.
When executing write operation, the voltage on wordline WL makes the first NMOS tube MN1 conductings, the drain electrode of third PMOS tube MP12
The logical zero of preservation makes the second PMOS tube MP11 conducting, electric current be flowed into from VA nodes, the second PMOS tube MP11 by conducting,
First NMOS tube MN1 and the first bit line BL.The influence of the resistance of third NMOS tube MN3 when not considering initial, the first bit line BL's
Voltage value VDL=[RN1/(RN1+RP1)]*VVA, RN1For the conduction resistance value of the first NMOS tube MN1, RP1For the second PMOS tube MP11
Conduction resistance value, VVAFor the voltage value of VA nodes.
From the voltage value V of the first bit line BLDLFormula can be seen that the conduction resistance value R of the first NMOS tube MN1N1Smaller,
The conduction resistance value R of second PMOS tube MP11P1Bigger, VA nodes voltage value VVA(voltage value of program voltage) is smaller more to be had
Help the logic 1 that the drain electrode of the second PMOS tube MP11 preserves becoming logical zero, can more improve write operation ability.And reduce VA sections
The voltage value V of pointVAThe conduction resistance value R of the second PMOS tube MP11 can be increasedP1, so, reduce the voltage value V of VA nodesVAIt can
To improve the write operation ability of storage array.
The conducting control unit 2 of the present embodiment can SRAM storage arrays 1 enter working condition and execute write operation before,
The all or part of drop-down metal-oxide-semiconductor of control is in the conduction state in the given time.When Sleep signals are logical zero, the first PMOS
Pipe P11 is in the conduction state, and the voltage of VA points is equal to the voltage value of first voltage VDD, and storage array 101 enters working condition.
Storage array 101 enters working condition, all or part of to pull down metal-oxide-semiconductor drop-down MOS in the conduction state, in the conduction state
Pipe can drag down the voltage value of VA points.So the voltage value of VA points is dragged down before executing write operation so that program voltage is less than electricity
Source voltage VDD improves the write operation ability of storage array.
The size and number of the drop-down metal-oxide-semiconductor and the predetermined time can influence the reduction width of the voltage value of VA points
Degree.Specifically, the size of drop-down metal-oxide-semiconductor is bigger, quantity is more, and the predetermined time in the conduction state is longer, the voltage of VA points
Value reduces more, and the program voltage for being provided to storage array is smaller.The voltage value of program voltage can be decreased to supply voltage
The voltage value 70% of VDD.
As shown in figure 5, conducting control unit 2 may include signal generation unit 21.Signal generation unit 21 is suitable for
Before SRAM storage arrays enter working condition and execute write operation, the pulse signal for keeping drop-down metal-oxide-semiconductor in the conduction state is generated；
The grid of the drop-down metal-oxide-semiconductor is suitable for inputting the pulse signal that the signal generation unit generates.
Specifically, signal generation unit 21 may include phase inverter 211, delay circuit 212 and OR-NOT circuit 213.Instead
The grid of the input terminal and the first PMOS tube MP11 of the input terminal connection delay circuit 212 of phase device 211, the output of phase inverter 211
The first input end of end connection OR-NOT circuit 213.The second of the output end connection OR-NOT circuit 213 of delay circuit 212 is defeated
Enter end.The output end of OR-NOT circuit 213 connects the grid of each drop-down metal-oxide-semiconductor.Delay circuit 212 be suitable for delay time be
The predetermined time.
Assuming that drop-down metal-oxide-semiconductor is NMOS tube, as shown in fig. 6, Sleep signals become logic 1 at the t1 moment from logical zero,
SRAM storage arrays 1 enter working condition.Signal generation unit 21 generates pulse signal Vc according to Sleep signals at the t1 moment,
The pulsewidth of pulse signal Vc is predetermined time T.The pulse signal Vc of high level makes whole pull-down NMOS pipes in the conduction state,
Pull-down NMOS pipe in the conduction state is by VA point voltage pull-downs.Logical zero is inputted in the form of low pulse on the first bit line on BL,
Low pulse terminates at the t2 moment, and the write operation that the end mark of low pulse logical zero starts.Since VA points voltage has been drawn
Low, so during executing write operation, program voltage is always less than supply voltage VDD.When Sleep signals become low from high level
When level, the first PMOS tube MP11 reenters conducting state, and VA point voltages are pulled to supply voltage VDD again.
Be connected control unit 2 can also control section drop-down metal-oxide-semiconductor it is in the conduction state, as shown in fig. 7, conducting control is single
Member 2 includes signal generation unit 21 and m storbing gate.Signal generation unit 21 is suitable for entering work in the SRAM storage arrays
Before state and execution write operation, the pulse signal for keeping the drop-down metal-oxide-semiconductor in the conduction state is generated；The output of the storbing gate
The grid with the drop-down metal-oxide-semiconductor is held to connect one to one, it is single that the input terminal of the storbing gate is suitable for inputting the signal generation
The pulse signal that member generates.
M storbing gate includes m-th of storbing gate Gm of the 1st storbing gate G1.......The output end of signal generation unit 21
Connect the input terminal of the 1st storbing gate G1 to m-th storbing gate Gm, the output end of the 1st storbing gate G1 to m-th storbing gate Gm
It is separately connected the grid of metal-oxide-semiconductor N1 to m-th drop-down metal-oxide-semiconductor Nm of the 1st drop-down.
It can also include selecting unit that control unit 2, which is connected, and the selecting unit is in suitable for control section storbing gate and leads
Logical state.By the control of positive control terminal and Reverse Turning Control end to storbing gate, may be implemented to part storbing gate predetermined
Control in the conduction state in time.
Fig. 8 additionally provides another and control section drop-down metal-oxide-semiconductor technical solution in the conduction state may be implemented.Such as
Shown in Fig. 8, conducting control unit 2 includes signal generation unit 21 and m switch metal-oxide-semiconductor.Signal generation unit 21 is suitable in institute
It states before SRAM storage arrays enter working condition and execute write operation, generating makes drop-down metal-oxide-semiconductor arteries and veins in the conduction state
Rush signal；The grid of the drop-down metal-oxide-semiconductor is suitable for inputting the pulse signal that the signal generation unit 21 generates.Each drop-down
Metal-oxide-semiconductor inputs the second voltage by a switch metal-oxide-semiconductor.
M switch metal-oxide-semiconductor includes m-th of switch metal-oxide-semiconductor N2m of the 1st switch metal-oxide-semiconductor N21.......Signal generation unit
21 output end connects the grid of metal-oxide-semiconductor N1 to m-th drop-down metal-oxide-semiconductor Nm of the 1st drop-down.1st drop-down metal-oxide-semiconductor N1 to m
The source electrode of a drop-down metal-oxide-semiconductor Nm inputs second voltage by metal-oxide-semiconductor N21 to m-th switch metal-oxide-semiconductor N2m of the 1st switch respectively
GND.That is, the 1st drop-down metal-oxide-semiconductor N1 connects the drain electrode of the 1st switch metal-oxide-semiconductor N21, the source electrode of the 1st switch metal-oxide-semiconductor N21 is suitable
In the drain electrode of m-th of drop-down metal-oxide-semiconductor Nm connection of input second voltage GND......, m-th of switch metal-oxide-semiconductor N2m, m-th of switch
The source electrode of metal-oxide-semiconductor N2m is suitable for input second voltage GND.
It can also include selecting unit that control unit 2, which is connected, and the selecting unit is suitable for control section switch metal-oxide-semiconductor and is in
Conducting state.By the control of the grid voltage to switching metal-oxide-semiconductor, may be implemented to part drop-down metal-oxide-semiconductor in the given time
Control in the conduction state.
Although present disclosure is as above, present invention is not limited to this.Any those skilled in the art are not departing from this
It in the spirit and scope of invention, can make various changes or modifications, therefore protection scope of the present invention should be with claim institute
Subject to the range of restriction.
Claims (11)
1. a kind of control circuit of SRAM storage arrays, which is characterized in that including：First PMOS tube, conducting control unit and extremely
Few drop-down metal-oxide-semiconductor；
The source electrode of first PMOS tube is suitable for input first voltage, and the drain electrode of first PMOS tube is suitable for depositing with the SRAM
Store up the power end connection of storage unit in array；
The drain electrode of the drop-down metal-oxide-semiconductor is all connected with the drain electrode of first PMOS tube, and the source electrode for pulling down metal-oxide-semiconductor is adapted to defeated
Enter second voltage, the voltage value of the second voltage is less than the voltage value of first voltage；
The conducting control unit is suitable for before the SRAM storage arrays enter working condition and execute write operation, and control is all
Or part drop-down metal-oxide-semiconductor is in the conduction state in the given time.
2. the control circuit of SRAM storage arrays as described in claim 1, which is characterized in that the drop-down in the conduction state
The quantity and size of metal-oxide-semiconductor are related to the program voltage needed for SRAM storage arrays execution write operation.
3. the control circuit of SRAM storage arrays as described in claim 1, which is characterized in that the predetermined time and the SRAM
It is related that storage array executes the program voltage needed for write operation.
4. the control circuit of SRAM storage arrays as described in claim 1, which is characterized in that the conducting control unit includes：
Signal generation unit；
The signal generation unit is suitable for before the SRAM storage arrays enter working condition and execute write operation, and generation makes institute
State drop-down metal-oxide-semiconductor pulse signal in the conduction state；
The grid of the drop-down metal-oxide-semiconductor is suitable for inputting the pulse signal that the signal generation unit generates.
5. the control circuit of SRAM storage arrays as described in claim 1, which is characterized in that the conducting control unit includes：
Signal generation unit and at least one storbing gate, the quantity of the storbing gate are identical as the drop-down quantity of metal-oxide-semiconductor；
The signal generation unit is suitable for before the SRAM storage arrays enter working condition and execute write operation, and generation makes institute
State drop-down metal-oxide-semiconductor pulse signal in the conduction state；
The output end of the storbing gate and the grid of the drop-down metal-oxide-semiconductor connect one to one, and the input terminal of the storbing gate is suitable
In the pulse signal for inputting the signal generation unit generation.
6. the control circuit of SRAM storage arrays as claimed in claim 5, which is characterized in that the conducting control unit further includes
Selecting unit, the selecting unit is in suitable for control section storbing gate can transmission state.
7. the control circuit of SRAM storage arrays as described in claim 1, which is characterized in that the conducting control unit includes：
The quantity of signal generation unit and at least one switch metal-oxide-semiconductor, the switch metal-oxide-semiconductor is identical as the drop-down quantity of metal-oxide-semiconductor；
Each drop-down metal-oxide-semiconductor inputs the second voltage by a switch metal-oxide-semiconductor；
The signal generation unit is suitable for before the SRAM storage arrays enter working condition and execute write operation, and generation makes institute
State drop-down metal-oxide-semiconductor pulse signal in the conduction state；
The grid of the drop-down metal-oxide-semiconductor is suitable for inputting the pulse signal that the signal generation unit generates.
8. the control circuit of SRAM storage arrays as claimed in claim 7, which is characterized in that the conducting control unit further includes
Selecting unit, it is in the conduction state that the selecting unit is suitable for control section switch metal-oxide-semiconductor.
9. the control circuit of SRAM storage arrays as described in claim 4,5 or 7, which is characterized in that the signal generation unit
Including：Phase inverter, delay circuit and OR-NOT circuit；
The input terminal of the phase inverter connects the grid of the input terminal and first PMOS tube of the delay circuit, the reverse phase
The output end of device connects the first input end of the OR-NOT circuit；
The output end of the delay circuit connects the second input terminal of the OR-NOT circuit, and the delay circuit is suitable for delay
Time is the predetermined time；
The output end of the OR-NOT circuit connects the grid of the drop-down metal-oxide-semiconductor.
10. a kind of SRAM memory, which is characterized in that store battle array including the SRAM described in claim 1 to 8 any claim
The control circuit of the control circuit and SRAM storage arrays of row, the SRAM storage arrays is adapted to provide for the SRAM storages battle array
Row execute the program voltage needed for write operation.
11. SRAM memory as claimed in claim 10, which is characterized in that the storage array includes depositing of being arranged in array
Storage unit, the storage unit are 6T storage units or 8T storage units.
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| CN111863070B (en) * | 2020-07-23 | 2022-07-12 | 南京低功耗芯片技术研究院有限公司 | Circuit for reducing SRAM memory array leakage current and control method |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1956098A (en) * | 2005-08-02 | 2007-05-02 | 株式会社瑞萨科技 | Semiconductor storage device |
| CN102779549A (en) * | 2011-05-11 | 2012-11-14 | 台湾积体电路制造股份有限公司 | SRAM write assist apparatus |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN1956098A (en) * | 2005-08-02 | 2007-05-02 | 株式会社瑞萨科技 | Semiconductor storage device |
| CN102779549A (en) * | 2011-05-11 | 2012-11-14 | 台湾积体电路制造股份有限公司 | SRAM write assist apparatus |
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