JP4598459B2 - Input circuit - Google Patents

Description

  The present invention relates to an input circuit, and more particularly to an input circuit that adjusts input impedance.

  In a system having an analog transmission line, distortion of the waveform of a transmission signal in the transmission line directly affects the accuracy of the entire system. For this reason, for example, in a compact disc (CD) player or video system, it is necessary to suppress at least harmonic distortion to -60 dB or less.

  In order to realize this requirement, impedance matching (impedance matching) must be taken from the signal transmission side to the reception side via the transmission line. That is, the output impedance on the transmission side, the transmission path impedance, and the input impedance on the reception side must match. If impedance matching is not achieved, the signal is reflected, and as a result, the signal waveform is disturbed and normal data transfer cannot be performed.

  For this reason, on the receiving side, the impedance is adjusted by an input circuit or the like to which a transmission signal is input, and then the signal is received by the receiving circuit. This input circuit can be configured, for example, by inserting a termination resistor between the input terminal of the receiving circuit and the ground potential GND. When the termination resistor is used, when the receiving circuit is formed by the CMOS process on the P substrate, the best signal transmission can be realized although the current consumption increases. However, in such a configuration with only a terminating resistor, the common voltage (in the middle of the signal amplitude) of the input signal input from the transmission line becomes the ground potential GND level.

  Therefore, a level shift circuit that converts this common voltage to a high level is used as an input circuit. By level-shifting the input signal, for example, the input stage of the receiving circuit can be configured by an N-channel MOSFET (Metal Oxide Semiconductor Field Effect Transistor, hereinafter referred to as a MOS transistor) differential circuit. Since the N-channel MOS transistor has a large mutual conductance and good frequency characteristics, the characteristics on the receiving side can be improved.

  For example, the circuit of Patent Document 1 is known as a conventional input circuit. FIG. 6 is a circuit diagram of a conventional input circuit, and this conventional input circuit is a circuit similar to the circuit described in Patent Document 1.

  As shown in the figure, the conventional input circuit includes a capacitor C1 and transistors J2 and J3. The capacitor C1 has one end connected to the input terminal IN and the other end connected to the output terminal OUT. In the transistor J2, the power supply potential Vdd is supplied to the drain, the gate potential VL is applied to the gate, and the source is connected to the output terminal OUT. The transistor J3 has a drain connected to the output terminal OUT, a gate applied with a gate potential Vb, and a source connected to the ground potential GND.

  In the conventional input circuit, a signal is input from the input terminal IN, and the level-shifted output voltage VOUT is output from the output terminal OUT. Here, the common voltage V_CM of the output voltage VOUT is a value obtained by lowering the gate-source voltage Vgs (J2) of the transistor J2 from the gate potential VL of the transistor J2, as shown in the following equation (1).

また、終端抵抗値（入力インピーダンス）Ｚｉは、次の数２により与えられる。

Further, the termination resistance value (input impedance) Zi is given by the following equation 2.

ここで、ｇｍ（Ｊ２）は、トランジスタＪ２の相互コンダクタンスである。数１及び数２より、従来の入力回路では、Ｖｇｓやｇｍを最適化することで、コモン電圧Ｖ＿ＣＭと終端抵抗値Ｚｉを所望の値に設定することができる。

Here, gm (J2) is the mutual conductance of the transistor J2. From Equations 1 and 2, in the conventional input circuit, the common voltage V_CM and the termination resistance value Zi can be set to desired values by optimizing Vgs and gm.

  However, in the conventional input circuit, when a large signal having a large amplitude is input, the output signal may be distorted. For example, when the termination resistance value Zi is set to 50Ω according to the above equation 2 under a certain bias condition and a certain small signal input level, if a large signal is input, the termination resistance value Zi is shifted from 50Ω and the output signal is distorted.

  7 and 8 show spurious characteristics (distortion characteristics) of a conventional input circuit. 7 and 8 show transient simulation results when a Sin wave having a frequency of 12.5 MHz is input after setting a termination resistance value Zi = 50Ω using a model having a CMOS process of 0.5 μm. 7 and 8, the horizontal axis represents frequency, and the vertical axis represents a transformed signal obtained by Fourier transforming the output signal in decibels. FIG. 7 shows the spurious characteristic when a small signal of ± 0.1 V is inputted, and FIG. 8 shows the spurious characteristic when a large signal of ± 1.0 V is inputted.

  When a small signal is input, as shown in FIG. 7, only 12.5 MHz has a large value, and a higher harmonic than 12.5 MHz has a small value. On the other hand, when a large signal is input, as shown in FIG. 8, not only 12.5 MHz but also harmonic distortion of 12.5 MHz has a large value. For example, as in the dotted line portion, many of frequency components higher than 12.5 MHz show values larger than −60 dB. Therefore, it can be seen that the spurious characteristic at the time of the large signal input shown in FIG. 8 is deteriorated compared to the case of the small signal input shown in FIG.

  This is because the gate-source voltage Vgs (J2) of the transistor J2 cannot be sufficiently secured when a large signal is input. When a large signal is input, the source potential of the transistor J2 greatly fluctuates and the gate-source voltage Vgs (J2) greatly fluctuates according to the amplitude of the input signal. Therefore, the gate-source voltage Vgs (J2) necessary for turning on the transistor J2 cannot be secured, and the transistor J2 is repeatedly turned on and off according to the input signal.

  For example, it is assumed that the power supply potential Vdd is 3 V and the common voltage V_CM is set to 1.5 V which is half the power supply potential Vdd according to the above equation 1 when a large signal of ± 1 V is input. At this time, 1.5V ± 1V is ideally output as the output voltage VOUT, but in reality, when 2.5V is output as the output voltage VOUT, the gate-source voltage Vgs (J2) is In other words, the linearity deteriorates and the input signal cannot be tracked, so that the spurious characteristics are deteriorated.

At the same time, this means that the termination resistance value Zi cannot be determined in the above equation (2). As described above, when a large signal is input, the transistor J2 is turned on / off according to the input signal, so that the drain current changes and the output resistance (impedance between the drain and source) of the transistor J2 changes. Therefore, for example, when a small signal is input, even if the impedance matching is performed with a termination resistance value Zi of 50Ω, it is difficult to realize transmission without reflection because the termination resistance value Zi is out of 50Ω when a large signal is input. Become.
JP-A-5-206781

  As described above, in the conventional input circuit, when a large signal is input, there is a problem that the spurious characteristic is deteriorated and the input impedance fluctuates.

  The present invention has been made to solve such problems, and an object of the present invention is to provide an input circuit in which spurious characteristics do not deteriorate and input impedance does not fluctuate even when a large signal is input. .

  An input circuit according to the present invention includes a first input terminal to which an input signal is input, a first output terminal that outputs a signal based on the input signal, the first input terminal, and the first output. And a first input impedance adjustment circuit for adjusting an input impedance to a predetermined impedance regardless of a level of the input signal, and a first input for supplying a predetermined current to the first input impedance adjustment circuit. 1 current source. As a result, it is possible to suppress deterioration of spurious characteristics and fluctuation of input impedance when a large signal is input.

  In the above-described input circuit, the first input impedance adjustment circuit sets the potential of a predetermined node between the first current source and the first input impedance adjustment circuit regardless of the level of the input signal. A first stabilization circuit that stabilizes to a predetermined potential and a first setting circuit that sets the input impedance to a predetermined impedance may be included. Thereby, the fluctuation | variation of input impedance can be suppressed more.

  In the input circuit described above, the first stabilization circuit is supplied from the first transistor connected between the first current source and the first output terminal, and the first current source. And a first operational amplifier that outputs a control signal to the first transistor based on the first current and the first reference potential. Thereby, it is possible to effectively suppress the deterioration of the spurious characteristics and the fluctuation of the input impedance.

  In the above input circuit, the first transistor has a first terminal connected to the first output terminal, a second terminal connected to an output terminal of the first current source, and the first transistor. The operational amplifier has one input terminal connected to the output terminal of the first current source, the other input terminal to which the first reference potential is input, and an output terminal connected to the gate of the first transistor. It may be a thing. Thereby, it is possible to further suppress the deterioration of the spurious characteristics and the fluctuation of the input impedance.

  In the input circuit described above, the first current source may include a second transistor that outputs a predetermined current based on an input control signal. As a result, it is possible to efficiently suppress deterioration of spurious characteristics and fluctuations in input impedance.

  The input circuit described above may include a third transistor that is mirror-connected to the second transistor, and a second current source that generates a predetermined current that flows through the third transistor. . Thereby, it is possible to further suppress the deterioration of the spurious characteristics and the fluctuation of the input impedance.

  In the above input circuit, the first setting circuit may be a resistance element. Thereby, input impedance can be adjusted easily.

  In the above-described input circuit, the first input impedance adjustment circuit is connected between the first input terminal and the first output terminal, and shifts the level of the input signal to the first output terminal. A first shift circuit that outputs the signal may be provided. Thereby, the input signal can be shifted to a desired level.

  In the above input circuit, the first shift circuit may be a resistance element. Thereby, the level shift amount of the input signal can be easily adjusted.

  The above input circuit may include a second operational amplifier that controls an output current of the first current source based on a potential of the first output terminal and a second reference potential. Good. Thereby, it is possible to further suppress the deterioration of the spurious characteristics and the fluctuation of the input impedance.

  The input circuit described above includes the first input terminal, the first output terminal, the first input impedance adjustment circuit, and the first current source as a first input stage, and a second input terminal. And a second input stage having a second output terminal, a second input impedance adjustment circuit, and a third current source, wherein the first input stage and the second input stage include a first power source. The first output terminal and the second output terminal may be connected in parallel between a potential and a second power supply potential, and the first output terminal and the second output terminal may be connected to each input terminal of the differential circuit, respectively. Thereby, spurious characteristics can be further improved.

  The input circuit controls the output currents of the first current source and the third current source based on the potentials of the first output terminal and the second output terminal and the second reference potential. It is also possible to have a second operational amplifier. Thereby, spurious characteristics can be further improved.

  The input circuit includes first and second resistance elements connected in series between the first output terminal and the second output terminal, and the second operational amplifier includes one of the first operational amplifiers. The second reference potential may be input to an input terminal, and a node between the first resistance element and the second resistance element may be connected to the other input terminal. Thereby, spurious characteristics can be further improved.

  An input circuit according to the present invention has one end connected to a first input terminal and the other end connected to a first power supply potential, a first impedance circuit having a predetermined impedance, and one end connected to the first input A second impedance circuit having a predetermined impedance, a second transistor connected to the first output terminal, a drain connected to the first output terminal, and a drain connected to the first output terminal. A second transistor connected to the source of the first transistor, the source connected to the second power supply potential, one input terminal connected to the drain of the second transistor, and the other input terminal connected to the first transistor Is connected to the gate of the first transistor, one end is connected to the second input terminal, and the other end is connected to the first power source. A third impedance circuit having a predetermined impedance and a fourth impedance having one end connected to the second input terminal and the other end connected to the second output terminal and having a predetermined impedance A circuit, a third transistor whose drain is connected to the second output terminal, and a fourth transistor whose drain is connected to the source of the third transistor and whose source is connected to the second power supply potential. A second operation in which one input terminal is connected to the drain of the fourth transistor, a second reference potential is input to the other input terminal, and an output terminal is connected to the gate of the third transistor. The third reference potential is input to the amplifier and one input terminal, and the output terminal is connected to the gate of the second transistor and the gate of the fourth transistor. A third operational amplifier, one end connected to the first output terminal, the other end connected to the other input terminal of the third operational amplifier, and one end connected to the second output terminal. And a second resistance element having the other end connected to the other input terminal of the third operational amplifier. As a result, it is possible to suppress deterioration of spurious characteristics and fluctuation of input impedance when a large signal is input.

  According to the present invention, it is possible to provide an input circuit in which spurious characteristics do not deteriorate and input impedance does not fluctuate even when a large signal is input.

Embodiment 1 of the Invention
First, the configuration of the input circuit according to the first exemplary embodiment of the present invention will be described with reference to FIG. This input circuit is a circuit for terminating the transmission path on the receiving side in a transmission system, for example. The input circuit is a circuit that shifts the level of an input signal input from a transmission line and outputs the signal to a subsequent receiving circuit and the like, and is a circuit that adjusts impedance by a desired termination resistor (input impedance).

  As shown in the figure, the input circuit includes a constant current source Iref, MOS transistors MP1, MP2, and MP3, an OP amplifier AMP1, and resistance elements R1 and R2. In the figure, 1 is a GND terminal to which a GND potential is supplied, 2 is a power supply terminal to which a power supply potential is supplied, 3 is a reference voltage input terminal to which a reference potential is supplied, 4 is an input terminal to which an input signal is input, 5 Is an output terminal for outputting a signal based on the input signal, for example, a signal obtained by level shifting the input signal.

  The constant current source Iref is a circuit that generates a predetermined current Iref. The constant current source Iref is preferably configured to flow a constant current, but may be, for example, a resistance element. One end of the constant current source Iref is connected to the GND terminal 1.

  The MOS transistor MP1 is a circuit that outputs the current Iref generated by the constant current source Iref from the MOS transistor MP2. In this example, the MOS transistor MP1 forms a current mirror together with the MOS transistor MP2, that is, the MOS transistor MP1 and the MOS transistor MP2 are mirror-connected to output a current proportional to the current Iref from the MOS transistor MP2. In the following description, the proportional coefficient is assumed to be 1. The MOS transistor MP1 is, for example, a P-channel type MOS transistor, and has a source connected to the power supply terminal 2 and a gate and a drain connected to the other end of the constant current source Iref.

  The constant current source Iref and the MOS transistor MP1 are circuits for controlling the gate potential of the MOS transistor MP2, and are also circuits for outputting the current Iref from the MOS transistor MP2.

  The MOS transistor MP2 is a first current source, and is a circuit that generates a current Iref and outputs the current Iref to the resistor element R2 and the like. The MOS transistor MP2 outputs a current Iref based on the gate potential input from the MOS transistor MP1 or the like. The MOS transistor MP2 outputs a constant current in the saturation region, and has a large output resistance (resistance between the drain and source). The MOS transistor MP2 is, for example, a P-channel type MOS transistor, and has a source connected to the power supply terminal 2 and a gate connected to the gate of the MOS transistor MP1.

  For example, the MOS transistor MP3, the OP amplifier AMP1, and the resistance element R1 are a first input impedance adjustment circuit that adjusts the input impedance. In particular, the input impedance adjustment circuit is a circuit that can set the input impedance to a predetermined impedance regardless of the level of the input signal.

  The MOS transistor MP3 and the OP amplifier AMP1 are a first stabilization circuit and a circuit that stabilizes the drain potential of the MOS transistor MP2 to a predetermined potential. In the present embodiment, the stabilization circuit can keep the drain potential of the MOS transistor MP2 constant even when a large signal having a large amplitude is input. Further, by setting the drain potential of the MOS transistor MP2 to a predetermined potential, the output resistance of the MOS transistor MP2 becomes a predetermined resistance value.

  The MOS transistor MP3 varies the drain potential of the MOS transistor MP2 based on the input gate potential. The MOS transistor MP3 is, for example, a P-channel type MOS transistor, and the source is connected to the drain of the MOS transistor MP2.

  The OP amplifier AMP1 controls the gate potential of the MOS transistor MP3 so that the reference potential of the reference voltage input terminal 3 is substantially equal to the drain potential of the MOS transistor MP2. The OP amplifier AMP1 has an inverting input terminal connected to the drain of the MOS transistor MP2, a normal rotation input terminal connected to the reference voltage input terminal 3, and an output terminal connected to the gate of the MOS transistor MP3.

  For example, when the drain potential of the MOS transistor MP2 is lower than the reference potential, the output of the OP amplifier AMP1, that is, the gate potential of the MOS transistor MP3 increases. Then, the gate-source voltage Vgs of the MOS transistor MP3 decreases and the output resistance (1 / gds) of the MOS transistor MP3 increases. The drain potential of the MOS transistor MP2 is defined by the current Iref and the output resistance of the MOS transistor MP3. Therefore, the drain potential of the MOS transistor MP2 increases due to the increase in the output resistance of the MOS transistor MP3. When the drain potential of the MOS transistor MP2 is higher than the reference potential, the output of the OP amplifier AMP1, that is, the gate potential of the MOS transistor MP3 is lowered. As a result, the gate-source voltage Vgs of the MOS transistor MP3 increases, and the output resistance of the MOS transistor MP3 decreases. As the output resistance of the MOS transistor MP3 decreases, the drain potential of the MOS transistor MP2 decreases.

  The MOS transistors MP2 and MP3 and the OP amplifier AMP1 are also circuits for preventing the resistance value of the resistance element R2 and the like from affecting the terminal resistance value. In this example, the output resistance of the MOS transistor MP2 is made much larger than that of the resistance element R1, so that the resistance value of the resistance element R2 or the like is not affected by the termination resistance value.

  The resistance element R2 is a first shift circuit, and is a circuit that shifts the level of the signal input from the input terminal 4 and outputs the signal to the output terminal 5. In the present embodiment, the shift amount by which the level of the input signal is shifted can be adjusted by the resistance element R2 and the current Iref. The resistance element R2 has one end connected to the drain of the MOS transistor MP3 and also connected to the output terminal 5.

  The resistance element R1 is a first setting circuit, and is a circuit that sets the termination resistance value Zi to a predetermined impedance. In the present embodiment, the termination resistance value Zi can be adjusted only by the resistance element R1. In addition, one end of the resistance element R1 is connected to the other end of the resistance element R2 and is also connected to the input terminal 4, and the other end is connected to the GND terminal 1.

  Here, the common voltage V_CM and the termination resistance value Zi of the input circuit according to the present embodiment will be described. The common voltage V_CM is a potential difference between the common potential of the output signal at the output terminal 5 and the GND potential. The common potential is the common mode level of the signal.

  The drain potential of the MOS transistor MP2 becomes the same potential as that of the reference voltage input terminal 3 regardless of the level of the signal input to the input terminal 4 by the OP amplifier AMP1 as described above. Therefore, the MOS transistor MP2 always operates in the saturation region, and the output resistance of the MOS transistor MP2 has a very large value.

ここで、出力電圧ＶＯＵＴは出力端子５における出力信号の電位とＧＮＤ電位との電位差であり、入力電圧Ｖｉｎは入力端子４における入力信号の電位とＧＮＤ電位との電位差であり、Ｒ２は抵抗素子Ｒ２の抵抗値である。そして、入力信号のコモン電圧Ｖｉｎ＿ＣＭは、次の数４によって与えられる。 For example, if the MOS transistor MP2 and the MOS transistor MP3 have the same gate length L / gate width W, a current Iref equal to the constant current source Iref flows into the resistance element R2. As a result, the output voltage VOUT is given by the following equation (3).

Here, the output voltage VOUT is the potential difference between the potential of the output signal at the output terminal 5 and the GND potential, the input voltage Vin is the potential difference between the potential of the input signal at the input terminal 4 and the GND potential, and R2 is the resistance element R2. Resistance value. The common voltage Vin_CM of the input signal is given by the following equation (4).

ここで、Ｖｉｎ＿ＣＭは入力端子４における入力信号のコモン電位とＧＮＤ電位との電位差である。さらに、出力端子５のコモン電圧Ｖ＿ＣＭは次の数５によって与えられる。

Here, Vin_CM is a potential difference between the common potential of the input signal at the input terminal 4 and the GND potential. Further, the common voltage V_CM of the output terminal 5 is given by the following equation (5).

尚、出力信号の最小ピーク電位（振幅の最小値）が０（ＧＮＤ電位）の場合、コモン電圧Ｖ＿ＣＭは、出力信号の振幅ＶＯＵＴ＿ｐｐの１／２となる。

When the minimum peak potential (minimum amplitude value) of the output signal is 0 (GND potential), the common voltage V_CM is ½ of the amplitude VOUT_pp of the output signal.

  The termination resistance value Zi is an input impedance viewed from the input terminal 4, and is regarded as an impedance of a circuit in which the three elements of the MOS transistors MP2 and MP3 and the resistance element R2 and the resistance element R1 are connected in parallel. Therefore, the termination resistance value Zi is given by Equation 6.

ここで、Ｒ１は抵抗素子Ｒ１の抵抗値、１／ｇｄｓ（Ｐ２）はＭＯＳトランジスタＭＰ２の出力抵抗、１／ｇｄｓ（Ｐ３）はＭＯＳトランジスタＭＰ３の出力抵抗である。そして、上記のように、ＭＯＳトランジスタＭＰ２の出力抵抗は、非常に大きくなるため、Ｒ１＜＜１／ｇｄｓ（Ｐ２）の関係が成り立ち、１／ｇｄｓ（Ｐ２）＝∞とみなすことができる。よって、この関係を数６に代入すると、終端抵抗値Ｚｉは次の数７のように、Ｒ１とみなすことができる。

Here, R1 is the resistance value of the resistance element R1, 1 / gds (P2) is the output resistance of the MOS transistor MP2, and 1 / gds (P3) is the output resistance of the MOS transistor MP3. As described above, since the output resistance of the MOS transistor MP2 becomes very large, the relationship R1 << 1 / gds (P2) is established, and can be regarded as 1 / gds (P2) = ∞. Therefore, if this relationship is substituted into Equation 6, the termination resistance value Zi can be regarded as R1 as shown in Equation 7 below.

したがって、信号レベルによらずたとえ大信号が入力されても、抵抗素子Ｒ１のみでインピーダンスマッチングが可能となるので、入力信号に対する出力信号の線形性が保たれ反射による歪みもなくなる。

Therefore, even if a large signal is input regardless of the signal level, impedance matching can be performed only with the resistor element R1, so that the linearity of the output signal with respect to the input signal is maintained, and distortion due to reflection is eliminated.

  Next, the spurious characteristic (distortion characteristic) of the input circuit according to the present embodiment will be described with reference to FIGS.

  2 and 3 use a model with a CMOS process of 0.5 μm, set the common voltage V_CM of the output signal to 1.75 V according to Equation 4, and set the termination resistance value Zi = R1 = 50Ω according to Equation 7. After that, the transient simulation result when a Sin wave having a frequency of 12.5 MHz is input. 2 and 3, the horizontal axis represents frequency, and the vertical axis represents a transformed signal obtained by Fourier transforming the output signal in decibels. FIG. 2 shows spurious characteristics when a small signal of ± 0.1 V is input, and FIG. 3 shows spurious characteristics when a large signal of ± 1.0 V is input.

  When a small signal is input, as shown in FIG. 2, only 12.5 MHz is a large value, and a higher harmonic than 12.5 MHz is a small value of −60 dB or less. This is the same characteristic as that of the conventional example shown in FIG.

  When a large signal is input, as shown in FIG. 3, only 12.5 MHz is a large value, and higher harmonics than 12.5 MHz are a small value of −60 dB or less. The characteristics are the same as in FIG. That is, it can be seen that the deterioration of the spurious characteristics when a large signal is input as shown in FIG. 8 of the conventional example is improved.

  With such a configuration, the drain potential of the MOS transistor MP2, which is the first current source, is kept constant regardless of the level of the input signal, so that even if a large signal is input, it is output without distortion and the characteristics are improved. can do.

  In addition, since the terminal resistance value Zi is determined only by the resistance element R1 between the input terminal and the GND terminal by increasing the resistance value from the input terminal to the power supply terminal side, it is reflected even when a large signal is input. Transmission is possible, and impedance adjustment can be easily performed.

  Furthermore, since the level shift amount of the input signal can be set by the resistance element R2 and the constant current source Iref, the level shift amount can be easily adjusted.

Embodiment 2 of the Invention
Next, the configuration of the input circuit according to the second exemplary embodiment of the present invention will be described with reference to FIG. In FIG. 4, the same reference numerals as those in FIG. 1 denote the same elements, and a description thereof will be omitted.

  This input circuit includes MOS transistors MP4 and MP5, an OP amplifier AMP2, and resistance elements R3 and R4 in addition to the configuration shown in FIG. In the figure, 6 is a reference voltage input terminal, 7 is an input terminal, and 8 is an output terminal.

  The MOS transistors MP4 and MP5, the OP amplifier AMP2, and the resistance elements R3 and R4 are the same circuits as the MOS transistors MP2 and MP3, the OP amplifier AMP1, and the resistance elements R1 and R2, and a circuit that handles differential signals is configured by them. The In the circuit that handles this differential signal, for example, the differential signal is input to the input terminals 4 and 7, and the output terminals 5 and 8 are connected to the input terminal of the differential amplifier AMP3 (differential circuit). By inputting the output signal of the circuit that handles the differential signal to the differential circuit, the in-phase noise component of the signal is removed.

  That is, the MOS transistors MP2 and MP3, the OP amplifier AMP1, and the resistance elements R2 and R3 constitute a first input stage, and the MOS transistors MP4 and MP5, the OP amplifier AMP2, and the resistance elements R3 and R4 constitute a second input stage. The circuit which handles a differential signal is comprised by the 1st input stage and the 2nd input stage.

  The MOS transistor MP4 is, for example, a P-channel MOS transistor, the source is connected to the power supply terminal 2, and the gate is connected to the gates of the MOS transistors MP1 and MP2. That is, the MOS transistor MP1 and the MOS transistors MP2 and MP4 are mirror-connected. The MOS transistor MP5 is, for example, a P-channel type MOS transistor, and the source is connected to the drain of the MOS transistor MP4.

  The OP amplifier AMP2 has an inverting input terminal connected to the drain of the MOS transistor MP4, a normal input terminal connected to the reference voltage input terminal 6, and an output terminal connected to the gate of the MOS transistor MP5. One end of the resistance element R3 is connected to the drain of the MOS transistor MP5 and also to the output terminal 8. The resistor element R4 has one end connected to the other end of the resistor element R3 and the input terminal 7, and the other end connected to the GND terminal 1.

  Since the MOS transistors MP4 and MP5, the OP amplifier AMP2, and the resistance elements R3 and R4 are circuits similar to the MOS transistors MP2 and MP3, the OP amplifier AMP1, and the resistance elements R2 and R3, they have the same functions and operations. The MOS transistor MP4 outputs the current Iref of the constant current source Iref to the resistor element R3 and the like. The OP amplifier AMP2 and the MOS transistor MP5 are controlled so that the drain potential of the MOS transistor MP4 becomes a predetermined potential. The resistance element R4 shifts the level of the signal input from the input terminal 7 and outputs it to the output terminal 8. The resistance element R3 adjusts the termination resistance value Zi_2 of the second input stage.

  And by comprising the input terminal 4 and the input terminal 7, and the output terminal 5 and the output terminal 8 in this way, a differential signal can be handled. Therefore, for example, if signals having opposite phases (differential signals) are input to the input terminal 4 and the input terminal 7 respectively, even if noise is applied to the power supply terminal 2, both the output terminal 5 and the output terminal 8 are in-phase noise. Will be canceled when transmitting. As a result, spurious characteristics (distortion characteristics) are significantly improved over the single transmission type described in the first embodiment. That is, high-quality transmission with a smaller distortion than in the first embodiment is possible.

Embodiment 3 of the Invention
Next, the configuration of the input circuit according to the third embodiment of the present invention will be described with reference to FIG. In FIG. 5, the same reference numerals as those in FIGS. 1 and 4 are the same elements, and the description thereof is omitted.

  This input circuit includes a common mode feedback amplifier CMFB_AMP1 and resistance elements R5 and R6 instead of the MOS transistor MP1 and the constant current source Iref configured as shown in FIG.

  Similar to the MOS transistor MP1 and the constant current source Iref in FIG. 4, the common mode feedback amplifier CMFB_AMP1 and the resistance elements R5 and R6 are circuits that control the gate potentials of the MOS transistors MP2 and MP4. This is a circuit for outputting Iref.

  In the first and second embodiments, the current Iref is generated by the constant current source Iref, and the current Iref is output from the MOS transistors MP2 and MP4 by the configuration of the current mirror. In the present embodiment, the gate potential of the MOS transistors MP2 and MP4 is controlled by the feedback of the common mode feedback amplifier CMFB_AMP1, and the current Iref is output.

  The resistance element R5 is, for example, a resistance whose resistance value is much larger than the resistance elements R1 and R2. For example, the resistance value of the resistance element R5 is about 100 times larger than the resistance elements R1 and R2. That is, the relationship R1 / R5 << 1 is established. The resistor element R5 has one end connected to the output terminal 5. Similarly to the resistor element R5, the resistor element R6 is a resistor having a resistance value much larger than that of the resistor elements R3 and R4, for example, and one end thereof is connected to the output terminal 8.

  The common mode feedback amplifier CMFB_AMP1 has a non-inverting input terminal connected to the other end of the resistor element R5 and the other end of the resistor element R6, an inverting input terminal connected to the common potential input terminal 9, and an output terminal connected to the other end of the resistor element R6. It is connected to the gate of the MOS transistor MP2 and is also connected to the gate of the MOS transistor MP2.

  Since the resistance values of the resistance elements R5, R6 are much larger than those of the resistance elements R1, R2, R3, R4, almost no current flows through the resistance elements R5, R6, and the common node between the resistance elements R5 and R6 The voltage and the voltage at the output terminals 5 and 8 are substantially equal. Therefore, the common mode feedback amplifier CMFB_AMP1 operates so that the voltage of the common potential input terminal 9 and the common voltage V_CM of the output terminals 5 and 8 become substantially the same voltage.

  That is, for example, the common mode feedback amplifier CMFB_AMP1 configured by an OP amplifier amplifies a potential difference between the potential of the common potential input terminal 9 and the common potential of the output terminals 5 and 8, and each gate of the MOS transistors MP2 and MP4. Output to. A drain current Ids flows through the MOS transistors MP2 and MP4 in response to the gate-source voltage Vgs. Since Ids is the current Iref flowing through the resistors R2 and R3, the common potential of the output terminals 5 and 8 changes when the current Iref changes.

  For example, when the common potential of the output terminals 5 and 8 is lower than the potential of the common potential input terminal 9, the output of the common mode feedback amplifier CMFB_AMP1, that is, the gate potential of the MOS transistors MP2 and 4 decreases. As a result, the gate-source voltage Vgs of the MOS transistors MP2 and 4 increases, and the drain current Ids of the MOS transistors MP2 and 4 increases. Therefore, the current Iref flowing through the resistors R2 and R3 increases, and as a result, the common potential at the output terminals 5 and 8 increases.

  When the common potential of the output terminals 5 and 8 is higher than the potential of the common potential input terminal 9, the output of the common mode feedback amplifier CMFB_AMP1, that is, the gate potential of the MOS transistors MP2 and 4 increases. Then, the gate-source voltage Vgs of the MOS transistors MP2 and 4 decreases, and the drain current Ids of the MOS transistors MP2 and 4 decreases. Therefore, the current Iref flowing through the resistors R2 and R3 decreases, and as a result, the common potential at the output terminals 5 and 8 decreases. Thus, the common mode feedback amplifier CMFB_AMP1 operates so as to correct the potential difference between the intermediate potential of the output terminals 5 and 8 and the common potential input terminal 9.

  For example, if the power supply voltage is 3.0 V, the values of the currents Iref and R2 expressed by the above equation 4 are set so that the common voltage V_CM is 1.5 V, which is half of that. This is because the margin of the output voltage VOUT from the power supply potential and the GND potential is taken, and as a result, the spurious characteristics are improved.

  However, in the case of the first and second embodiments, the value of the current Iref generated by the constant current source Iref varies depending on the temperature, the power supply voltage, and the process conditions. Therefore, the common voltage V_CM is reduced to half the power supply voltage under all conditions. Can't control.

  Since the common voltage V_CM in this embodiment is determined only by the potential input to the common potential input terminal 9 connected to the common mode feedback amplifier CMFB_AMP1, the common voltage V_CM is controlled to a value half the power supply voltage under all conditions. Can do. Therefore, in the present embodiment, by mounting the common mode feedback amplifier CMFB_AMP1 in comparison with the first and second embodiments, it is possible to perform transmission with higher quality and less distortion and more stably.

  In the third embodiment, the common mode feedback amplifier CMFB_AMP1 or the like is applied to the input circuit of the second embodiment, but may be applied to the first embodiment.

  In the above example, the resistance elements R2 and R3 may not be provided. In this case, the input signal is not level-shifted, but similar effects can be obtained, such as improvement of characteristics when a large signal is input and adjustment of input impedance is facilitated.

It is a circuit diagram which shows the structure of the input circuit concerning this invention. It is a graph which shows the spurious characteristic of the input circuit concerning this invention. It is a graph which shows the spurious characteristic of the input circuit concerning this invention. It is a circuit diagram which shows the structure of the input circuit concerning this invention. It is a circuit diagram which shows the structure of the input circuit concerning this invention. It is a circuit diagram which shows the structure of the conventional input circuit. It is a graph which shows the spurious characteristic of the conventional input circuit. It is a graph which shows the spurious characteristic of the conventional input circuit.

Explanation of symbols

1 GND terminal 2 Power supply terminal 3 Reference voltage input terminal 4, 7 Input terminal 5, 8 Output terminal 9 Common potential input terminal MP1, MP2, MP3, MP4, MP5 MOS transistors R1, R2, R3, R4, R5, R6 Resistance element AMP1, AMP2 OP amplifier CMFB_AMP1 Common mode feedback amplifier

Claims (13)

A first input terminal to which an input signal is input;
A first output terminal for outputting a signal based on the input signal;
A first setting circuit which is connected between the first input terminal and a first power supply potential and sets an input impedance viewed from the first input terminal;
A first shift circuit that is connected between the first input terminal and the first output terminal, shifts the level of the input signal, and outputs the level to the first output terminal;
A first current source connected between the first output terminal and a second power supply potential and supplying a current to the first setting circuit and the shift circuit;
A first stabilization circuit connected between the first current source and the first output terminal and stabilizing the drain potential of the first current source at a predetermined potential;
An input circuit comprising: The first stabilization circuit includes:
A first transistor connected between the first current source and the first output terminal;
A first operational amplifier that outputs a control signal to the first transistor based on a current supplied from the first current source and a first reference potential;
The input circuit according to claim 1 . The first transistor has a first terminal connected to the first output terminal, a second terminal connected to an output terminal of the first current source,
The first operational amplifier has one input terminal connected to the output terminal of the first current source, the other input terminal to which the first reference potential is input, and an output terminal to the first transistor. Connected to the gate,
The input circuit according to claim 2 . The first current source includes a second transistor that outputs a predetermined current based on an input control signal.
Input circuit according to any one of claims 1 to 3. A third transistor mirror-connected to the second transistor;
A second current source for generating a predetermined current flowing through the third transistor,
The input circuit according to claim 4 . The first setting circuit is a resistance element.
Input circuit according to any one of claims 1 to 5. The first shift circuit is a resistance element.
The input circuit according to claim 1 . A second operational amplifier that controls an output current of the first current source based on a potential of the first output terminal and a second reference potential;
Input circuit according to any one of claims 1 to 7. The first input terminal, the first output terminal, the first setting circuit, the first shift circuit, the first stabilization circuit, and the first current source are defined as a first input stage. ,
A second input terminal, a second output terminal, a second setting circuit, a second shift circuit, a second stabilization circuit, and a third current source, each having a configuration corresponding to the first input stage ; A second input stage having:
The first input stage and the second input stage are connected in parallel between a first power supply potential and a second power supply potential;
The first output terminal and the second output terminal are connected to input terminals of a differential circuit, respectively.
Input circuit according to any one of claims 1 to 7. A second operational amplifier that controls output currents of the first current source and the third current source based on a potential of the first output terminal and the second output terminal and a second reference potential; Having
The input circuit according to claim 9 . Between the first output terminal and the second output terminal, there are first and second resistance elements connected in series,
In the second operational amplifier, the second reference potential is input to one input terminal,
A node between the first resistance element and the second resistance element is connected to the other input terminal;
The input circuit according to claim 10 . A first impedance circuit having one end connected to the first input terminal and the other end connected to the first power supply potential and having a predetermined impedance;
  A second impedance circuit having one end connected to the first input terminal and the other end connected to the first output terminal and having a predetermined impedance;
  A first transistor having a drain connected to the first output terminal;
  A second transistor having a drain connected to a source of the first transistor and a source connected to a second power supply potential;
  A first operational amplifier having one input terminal connected to the drain of the second transistor, a first reference potential input to the other input terminal, and an output terminal connected to the gate of the first transistor; ,
  An input circuit comprising: A first impedance circuit having one end connected to the first input terminal and the other end connected to the first power supply potential and having a predetermined impedance;
A second impedance circuit having one end connected to the first input terminal and the other end connected to the first output terminal and having a predetermined impedance;
A first transistor having a drain connected to the first output terminal;
A second transistor having a drain connected to a source of the first transistor and a source connected to a second power supply potential;
A first operational amplifier having one input terminal connected to the drain of the second transistor, a first reference potential input to the other input terminal, and an output terminal connected to the gate of the first transistor; ,
A third impedance circuit having one end connected to the second input terminal and the other end connected to the first power supply potential and having a predetermined impedance;
A fourth impedance circuit having one end connected to the second input terminal and the other end connected to the second output terminal and having a predetermined impedance;
A third transistor having a drain connected to the second output terminal;
A fourth transistor having a drain connected to the source of the third transistor and a source connected to the second power supply potential;
A second operational amplifier having one input terminal connected to the drain of the fourth transistor, a second reference potential input to the other input terminal, and an output terminal connected to the gate of the third transistor; ,
A third operational amplifier in which a third reference potential is input to one input terminal, and an output terminal is connected to the gate of the second transistor and the gate of the fourth transistor;
A first resistance element having one end connected to the first output terminal and the other end connected to the other input terminal of the third operational amplifier;
A second resistance element having one end connected to the second output terminal and the other end connected to the other input terminal of the third operational amplifier;
An input circuit comprising:

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