JP5012412B2 - Amplifying device and bias circuit - Google Patents

Description

  The present invention relates to an amplification device and a bias circuit.

  FIG. 1 shows an example of an amplification device. The amplifying device has an amplifier and a bias circuit. The amplifier includes a first FET, a second FET and a load resistor in series connection. The drain of the first FET is connected to the output terminal of the amplifier via the second FET. The source of the first FET is connected to a low potential source. The gate of the first FET is connected to the signal source S through a capacitor. Further, the gate is given a bias from the Gm compensation bias circuit.

The change ΔI _{amp in the} current flowing through the first FET is proportional to the change in the gate voltage Vin, and the proportionality coefficient Gm is called mutual conductance:
ΔI _amp = Gm × ΔVin.
Therefore, the voltage change ΔVout applied to the load resistance R is
ΔVout = R × ΔIamp = R × Gm × ΔVin
Can be written. The gain of the amplifier is defined as R × Gm. The Gm compensation bias circuit provides an appropriate bias to the gate of the FET to ensure that the transconductance Gm of the first FET is inversely proportional to the load resistance R. By making the gain R × Gm take a constant value, it is possible to suppress variations in amplification characteristics due to FET manufacturing processes and temperature fluctuations during operation. This is because, in general, in the integrated circuit LSI, the same type of resistance R changes in the same way with respect to manufacturing process variations and the like. An example of a bias circuit in which the mutual conductance Gm of the FET is inversely proportional to the load resistance R is described, for example, in Patent Document 1 (paragraph 0030, FIG. 9).
JP 2002-185288 A

FIG. 2 shows the relationship between the drain current and drain voltage of the first FET of FIG. If the resistance R _DS between the source and the drain of the FET is relatively large, the drain current hardly changes even if the drain voltage fluctuates to some degree. That is, ΔI with respect to ΔV is quite small and can be ignored. Therefore, even if the drain voltage V1 of the first FET changes slightly, the current I _amp flowing through each FET is not significantly affected. When the current Iamp flowing through the FET varies, the mutual conductance Gm of the FET also varies. However, when Rds is relatively large, Iamp is difficult to vary as described above, so that the gain variation is small.

By the way, if the resistance R _DS between the source and the drain becomes relatively small as the transistor becomes finer, the drain current fluctuation according to the drain voltage fluctuation cannot be ignored. That is, ΔI with respect to ΔV becomes relatively large. For this reason, the current Iamp changes according to the state of the second FET, and the drain voltage and current of the first FET also easily change. When the drain current Iamp changes due to manufacturing process fluctuations, operating temperature, etc., the gain of the amplifier also changes. In particular, if the threshold voltage Vth of the second FET varies due to a manufacturing process or the like, there is a concern that the gain of the amplifier also varies considerably.

  An object of the present invention is to provide a bias circuit that stabilizes the bias of a field-effect transistor connected in series that constitutes an amplifier in order to stabilize the gain of the amplifier.

The amplification device used in the present invention is:
The load resistor and the drain of the second FET are connected,
An amplifier having a structure in which the source of the second FET and the drain of the first FET are connected;
A first bias circuit for supplying a first bias current to the first FET; and a second bias circuit for supplying a second bias voltage to the gate of the second FET. The second bias circuit applies a control signal to the gate of the second FET so that the bias voltage at the connection node of the first and second FETs is equal to or interlocked with the output voltage of the first bias circuit. Have

  According to the present invention, it is possible to stabilize the bias of the field-effect transistors connected in series constituting the amplifier, and to stabilize the gain of the amplifier.

  An amplifying device used in an embodiment of the present invention includes a load resistor, an amplifier having a structure in which a first FET and a second FET are connected in series, a first bias circuit that supplies a first bias current to the first FET, A second bias circuit for supplying a second bias voltage to the gate of the second FET. The second bias circuit applies a control signal to the gate of the second FET so that the bias voltage at the connection node of the first and second FETs is equal to or interlocked with the output voltage of the first bias circuit. Have

  The second bias circuit includes a first auxiliary FET having a gate connected to the output of the first bias circuit, a second auxiliary FET connected in series to the first auxiliary FET via a connection node, and A comparator that compares the output voltage of the first bias circuit and the voltage of the connection node and supplies a signal indicating the comparison result to the gate of the second FET and to the gate of the second auxiliary FET.

Alternatively, the second bias circuit compares a low-pass filter having an input connected to a connection node of the first and second FETs with an output voltage of the first bias circuit and an output voltage of the low-pass filter, and compares the result. And a comparator for supplying a signal indicating the above to the gate of the second FET.
The first bias circuit includes:
A third FET having a first electrode and a second electrode through which a first current flows and having a gate connected to the first electrode;
A fourth FET having a first electrode and a second electrode through which a second current flows and having a gate connected to the gate of the third FET;
A first resistor connected to the second electrode of the third FET or the second electrode of the previous fourth FET;
A comparator that outputs a signal corresponding to a comparison result of a first voltage that is a voltage of the first electrode of the third FET and a second voltage that is a voltage of the first electrode of the fourth FET;
And the first voltage and the second voltage may be controlled to be equal to each other by a signal output from the comparison device.

  The transconductance of the fourth FET is controlled to be inversely proportional to the first resistance of the third FET.

  The third and fourth FETs are N-channel FETs, a P-channel FET is provided as the first current source between the first electrode of the third FET and a high potential source, and the first electrode of the fourth FET is A P-channel FET is provided as a second current source in the previous period with the potential source, and the second electrode of the third FET or one second electrode of the fourth FET is connected to the low potential source via the first resistor. The second electrode of the other FET on the side to which the first resistor is not connected may be connected to a low potential source.

  The output of the comparator of the first bias circuit may be provided to the gate of the P-channel FET.

  The comparison device of the first bias circuit may be composed of an operational amplifier.

  The first FET may be connected to a low potential source via a strain relief resistor.

  The first FET and the first auxiliary FET may be connected to a low potential source via a strain relief resistor, respectively.

The first and second auxiliary FETs may be connected in series via a voltage adjusting resistor.
The comparison device may comprise an operational amplifier.

  The amplifier has a first terminal for inputting a first signal and a second terminal for receiving a second signal, and constitutes a Gilbert mixer that outputs a third signal obtained by multiplying the first and second signals. The first bias circuit may supply a bias voltage to the first terminal, and the second bias circuit may supply a bias voltage to the second terminal.

  FIG. 3 shows an amplifying device according to a first embodiment of the present invention. The amplifying device includes an amplifier, a Gm compensation bias circuit, and a stabilization bias circuit.

The amplifier has the same configuration and function as described in FIG. The amplifier includes a load resistor R and a first and second N-channel field effect transistor FET (referred to as a first FET and a second FET) connected in series between a high potential source and a low potential source. The drain of the first FET is connected to the output terminal of the amplifier via the second FET. The source of the first FET is connected to a low potential source. The gate of the first FET is connected to the signal source S through a capacitor. In the FET (at least the first FET) used in the present embodiment, the source / drain resistance R _DS is small enough that the drain current changes substantially linearly according to the drain voltage.
The Gm compensation bias circuit applies a bias to the gate of the first FET.

  In this embodiment, a stabilizing bias circuit is further provided in the amplifier. The stabilizing bias circuit refers to first and second N-channel field effect transistors (first and second auxiliary FETs) connected in series via a connection node A between a high potential source and a low potential source. ). The stabilizing bias circuit further comprises a comparator COM. The comparator COM has a non-inverting input (+) connected to the output of the Gm compensation bias circuit, an inverting input (−) connected to the connection node A, and an output connected to the second FET (and the second auxiliary FET). Have. The comparison device COM may be configured by any circuit known in the art that outputs an output signal corresponding to the magnitude relationship of the input signals. The comparison device may be constituted by an operational amplifier, for example. The first auxiliary FET has the same electrical characteristics as the first FET of the amplifier. The second auxiliary FET has the same electrical characteristics as the second FET of the amplifier. The comparator COM compares the output voltage of the Gm compensation bias circuit and the voltage V1 ′ of the connection node A, and supplies a signal indicating the comparison result to the gate of the second auxiliary FET and to the gate of the second FET.

As described above, the change ΔI _{amp in the} current flowing through the first FET of the amplifier is proportional to the change in the gate voltage Vin, and the proportionality coefficient Gm is called mutual conductance:
ΔI _amp = Gm × ΔVin.
Therefore, the voltage change ΔVout applied to the load resistance R is
ΔVout = R × ΔIamp = R × Gm × ΔVin
Can be written. The gain of the amplifier is defined as R × Gm. The Gm compensation bias circuit provides an appropriate bias to the gate of the FET to ensure that the transconductance Gm of the first FET is inversely proportional to the load resistance R. By making the gain R × Gm a constant value, it is expected that variations in amplification characteristics due to FET manufacturing processes and temperature fluctuations during operation can be reduced. However, the smaller the source drain resistance R _DS of the FET with miniaturization of a transistor, variation in the drain current I _{# 038} and gain may become large. In this regard, the present embodiment attempts to stabilize the bias applied to the gate of the second FET, and thus to stabilize the gain of the amplifier.

  The first and second auxiliary FETs of the stabilizing bias circuit have substantially the same electrical characteristics as the first and second FETs of the amplifier, respectively. Therefore, the drain voltage V1 ′ of the first auxiliary FET which is the connection node A reflects the drain voltage of the first FET. The comparison device COM compares the output voltage of the Gm compensation bias circuit with the voltage V1 ′ of the connection node A, and outputs a signal corresponding to the magnitude relationship of the comparison result. Suppose that the output voltage of the Gm bias circuit is larger. This corresponds to the drain voltage V1 of the first FET being smaller than the original value. In this case, the illustrated comparator COM increases the voltage according to the magnitude relationship, and the voltage is applied to the gate of the second auxiliary FET and to the gate of the second FET. The source voltage of the second auxiliary FET and the second FET, which are N-channel transistors, rises in response to the rise of the gate voltage. As a result, the potential of the connection node A rises, the voltages input to the comparison device COM try to be equal, and the drain voltage of the first FET also rises.

  Conversely, assume that the output voltage of the Gm bias circuit is smaller. This corresponds to the drain voltage of the first FET being larger than the original value. In this case, the comparator COM shown in the figure reduces the voltage according to the magnitude relationship, and the voltage is applied to the gate of the second auxiliary FET and to the gate of the second FET. The source voltage of the second auxiliary FET and the second FET, which are N-channel transistors, is processed in response to the decrease in the gate voltage. As a result, the potential V1 ′ of the connection node A decreases, the voltages input to the comparison device COM try to be equal, and the drain voltage of the first FET also decreases. Thus, the potential V1 ′ of the connection node A is stabilized, and the drain voltage V1 of the first FET corresponding to the potential is also stabilized.

  Note that it is not essential that the voltage at the connection node A and the drain voltage of the first FET be the same. For example, it is assumed that the voltage adjustment resistor Rx is inserted between the connection node A and the source node of the second auxiliary FET (in the vicinity of B in the figure). In this case, the voltage of the inverting input (−) becomes lower by the potential difference applied to the voltage adjustment resistor Rx. Therefore, the comparison device COM outputs a higher voltage than when the voltage adjustment resistor Rx is not provided. By inputting this signal to the gate of the second FET, the drain voltage of the first FET can be further increased. More generally, the polarity change point (zero point) of the control signal sent to the second FET can be changed by applying some offset voltage to the input of the comparator COM.

  Since the amplifier shown in FIGS. 1 and 3 includes the first and second FETs, not only the bias of the second FET but also the stabilization of the bias of the first FET is considered from the viewpoint of stabilizing the gain of the amplifier. You should do it. The second embodiment of the present invention also attempts to stabilize the bias applied to the first FET from the Gm compensation bias circuit. Before describing the Gm compensation bias circuit according to the present embodiment, problems when the conventional Gm compensation bias circuit is used will be pointed out.

  FIG. 4 shows an example of a circuit used in a conventional Gm compensation bias circuit. The Gm compensation bias circuit includes a first P-channel and N-channel FET and a second P-channel and N-channel FET. The first P-channel FET has a source connected to a high potential source, a gate, and a drain connected to the gate. The first N-channel FET is referred to as a third FET and has a drain connected to the drain of the first P-channel FET, a gate, and a source connected to a low potential source via a resistor Rs. The second P-channel FET has a source connected to the high potential source, a gate connected to the gate of the first P-channel FET, and a drain. The second N-channel FET, referred to as the fourth FET, has a drain connected to the drain of the second P-channel FET, a gate connected to the drain, and a source connected to a low potential source.

  Generally, the Gm compensation bias circuit constitutes a current mirror circuit, and the reference current Iref flowing through the first P-channel FET and the third FET is reflected in the bias current Ibi flowing through the second P-channel FET and the fourth FET. In this case, if the reference current Iref and the bias current Ibi are equal, the mutual conductance gm of the fourth FET can be approximated by the following equation.

ここで、Rsは第３ＦＥＴのソースに接続された第１抵抗(Rs)を表す。上記の数式から分かるように、第３ＦＥＴの相互コンダクタンスgmは、Iref=Ibiの場合、第１抵抗Rsに反比例する。従って、バイアス電流Ibiに比例する電流が、後段の増幅器に供給されるならば、バイアスの安定化を図ることができ、増幅器の利得の安定化を図ることができる。

Here, Rs represents the first resistance (Rs) connected to the source of the third FET. As can be seen from the above formula, the mutual conductance gm of the third FET is inversely proportional to the first resistance Rs when Iref = Ibi. Therefore, if a current proportional to the bias current Ibi is supplied to the subsequent amplifier, the bias can be stabilized and the amplifier gain can be stabilized.

As mentioned in connection with FIG. 2, when the resistance R _DS between the source and drain of the FET is relatively large, the drain current does not change much even if the drain voltage varies somewhat. Even if the drain voltages V3 and V4 of the third and fourth FETs are slightly different, the relationship of Iref = Iout can be maintained, and the above approximate expression gm∝1 / Rs holds, and the expected operation is guaranteed. The However, if the resistance R _DS between the source and the drain becomes relatively small as the transistor becomes finer, the drain current fluctuation according to the drain voltage fluctuation cannot be ignored. For this reason, the drain voltages V3 and V4 of the third and fourth FETs are required to be equal. However, in practice, the drain voltages V3 and V4 of the third and fourth FETs may not be the same due to manufacturing process fluctuations, operating temperatures, and the like. In this case, the relationship of Iref = Iout is not maintained, and The approximate expression gm∝1 / Rs of is no longer valid. As a result, the expected operation cannot be guaranteed.

  FIG. 5 shows a Gm compensation bias circuit according to this embodiment. The Gm compensation bias circuit has the same elements as those already described with reference to FIG. 4, and redundant description thereof is omitted. The Gm compensation bias circuit of FIG. 5 further includes a comparator COM, which compares the non-inverting input (+) connected to the drain of the third FET and the inverting input (−) connected to the drain of the fourth FET. And an output connected to the gates of both the first and second P-channel FETs. A phase adjustment circuit is provided between the non-inverting input and the output of the comparator COM. In the illustrated example, the phase adjustment circuit is composed of a capacitor alone. However, the phase adjustment circuit may be composed of any appropriate combination of a capacitor, an inductor, a resistor, and the like (for example, a circuit in which a capacitor and a resistor are connected in series). . The phase adjustment circuit may be provided between the inverting input and the output. This is because it is only necessary to appropriately set the relative phase between the reference current side and the bias current side to prevent oscillation.

  As in the case of the circuit of FIG. 4, the Gm compensation bias circuit of FIG. 5 also forms a current mirror circuit, and the reference current Iref flowing through the third FET is reflected in the bias current Ibi flowing through the fourth FET. If the reference current Iref and the bias current Ibi are equal, the mutual conductance gm of the fourth FET is proportional to 1 / Rs. Therefore, if a current proportional to the bias current Ibi is supplied to the amplifier at the subsequent stage, the bias can be stabilized and the gain of the amplifier can be stabilized.

  The Gm compensation bias circuit is controlled so that the drain voltages V3 and V4 of the third and fourth FETs are always equal. To explain this, consider a model in which the first and second FETs are replaced by equivalent circuits.

As shown in FIG. 6, the third FET in which the gate and the drain are connected can be considered as a resistance circuit having a value of 1 / (2 gm). However, it is assumed that the scale factor K is 4. In this case, the drain voltage change ΔV3 of the third FET is
ΔV3 = (1 / (2gm) + Rs) × ΔIref
Can be written. Therefore,
ΔIref = 2gm / (1 + 2gm × Rs) ΔV1 ≦ gm × ΔV3 (1)
It becomes. However, it is assumed that gm × Rs> 1/2.

  On the other hand, the fourth FET can be considered as a gm × ΔV3 current source.

ΔIbi = gm × ΔV3 (2)
It is. Referring to the equations (1) and (2), it can be seen that the change ΔIref in the reference current is more gradual than the change ΔIbi in the bias current from the viewpoint of the current with respect to the voltage (see the lower graph in FIG. 5). .)

Suppose that Iref <Ibi. If the resistances R _DS between the source and drain of the first and second P-channel FETs are approximately the same, V3> V4, and this potential difference is input to the comparator COM. In the case of the illustrated example, a relatively large voltage is applied to the non-inverting input (+) of the comparison device COM, and a relatively small voltage is applied to the inverting input (−). The comparison device COM outputs a comparison output signal (in the example shown, a high potential corresponding to the potential difference) according to the magnitude relationship of the voltages. The comparison output signal is input to the gates of the first and second P-channel FETs, respectively. Since the first and second P-channel FETs receive a high potential at their gates, the current decreases. The reference current Iref and the bias current Ibi are reduced, and the drain voltages of the third and fourth FETs change in the same direction, and move from the state of V3 ≠ V4 and Iref <Ibi to the state of V3 = V4 and Iref = Ibi.

  Conversely, suppose Iref> Ibi. In this case, V3 <V4, and this potential difference is input to the comparator COM. In the case of the illustrated example, a relatively small voltage is applied to the non-inverting input (+) of the comparison device COM, and a relatively large voltage is applied to the inverting input (−). The comparison device COM outputs a comparison output signal (in this case, a low potential corresponding to the potential difference) according to the magnitude relationship of the voltages. The comparison output signal is input to the gates of the first and second P-channel FETs, respectively. The first and second P-channel FETs tend to increase current. The reference current Iref and the bias current Ibi increase, and the drain voltages of the third and fourth FETs change in the same direction. From the state of V3 ≠ V4 and Iref> Ibi, the state goes to the state of V3 = V4 and Iref = Ibi.

  According to the present embodiment, the reference current Iref and the bias current Ibi are increased or decreased according to the comparison output signal corresponding to the potential difference (including the polarity) input to the comparator COM of the Gm compensation bias circuit. = Ibi is realized, and control is performed so that V3 = V4. Further, in combination with the operation of the stabilizing bias circuit, control is performed so that V1 = V1 ′ = V3 = V4. That is, control is performed so that the drain voltages of the first FET, the first auxiliary FET, the third FET, and the fourth FET are equal. As a result, the bias of both the first and second FETs of the amplifier can be stabilized, and the gain of the amplifier can be extremely stabilized.

  FIG. 7 shows a modification of this embodiment. The output of the Gm compensation bias circuit may be taken from the drain (voltage V3) of the third FET as shown in FIG. 5, or may be taken from the drain (voltage V4) of the fourth FET. This is because they are controlled to be equal. From the viewpoint of stability of operation, the output may be taken out through a current mirror composed of a fifth FET and a sixth FET, as shown in FIG. In the example shown, the fifth FET has a gate connected to the output of the comparator COM, a source connected to the high potential source, and a drain connected to the connection node E. The sixth FET has a drain connected to the connection node E, a gate connected to the drain, and a source connected to a low potential source (typically GND) via a distortion compensation resistor. The gate and drain of the sixth FET are connected to the non-inverting input (+) of the comparator COM of the stabilizing bias circuit. In general, the circuit example shown in FIG. 7 differs from the circuit example of FIG. 5 in that it includes elements surrounded by a wavy frame. By providing a distortion compensation resistor, the amplifier can have a distortion compensation function. Connecting the source or drain to the potential source via the strain compensation resistor may be performed not only in this embodiment but also in other embodiments.

  FIG. 8 shows an amplifying apparatus according to a third embodiment of the present invention. The amplifying device includes an amplifier, a Gm compensation bias circuit, and a stabilization bias circuit. Since the amplifier and the Gm compensation bias circuit have the same configuration and function as those described in the second embodiment, redundant description is omitted. In this embodiment, a stabilizing bias circuit different from that of the second embodiment is used.

  The stabilization bias circuit includes a low-pass filter LPF and a comparison device COM. The LPF has an input connected to the connection node (voltage V1) of the first and second FETs of the amplifier and an output connected to the inverting input (−) of the comparator COM. The comparator COM has a non-inverting input (+) connected to the output of the Gm compensation bias circuit, an inverting input (−) connected to the output of the low-pass filter LPF, and an output connected to the gate of the second FET. Have. The low pass filter LPF removes a high frequency component from the voltage at the connection node of the first and second FETs of the amplifier, and outputs a low frequency component. In other words, the low-pass filter LPF removes a small signal component from V1 of the amplifier and extracts a component corresponding to a DC voltage. For simplicity, the low-pass filter LPF has a resistor and a capacitor, and the resistor is connected between the inverting input (−) of the comparator and the connection node of the first and second FETs, and the capacitor is in parallel with the resistor. It is connected to the. However, any suitable low pass filter circuit known in the art may be used. The output of the low-pass filter LPF and the output of the Gm compensation bias circuit are compared by the comparison device COM, and a signal corresponding to the magnitude relation of the comparison result is output.

  Suppose that the output voltage of the Gm bias circuit is higher than V1. This corresponds to the drain voltage of the first FET being smaller than the original value. In this case, the comparator COM shown increases the voltage according to the magnitude relationship, and the signal is applied to the gate of the second FET. The second FET, which is an N-channel transistor, tries to increase the source voltage as the gate increases. As a result, the drain voltage V1 of the first FET also increases.

  Conversely, assume that the output voltage of the Gm bias circuit is smaller than V1 ′. This corresponds to the drain voltage of the first FET being larger than the original value. In this case, the illustrated comparator COM decreases the voltage according to the magnitude relationship, and the signal is applied to the gate of the second FET. The second FET, which is an N-channel transistor, attempts to decrease the source voltage as the gate voltage decreases. As a result, the drain voltage V1 of the first FET also decreases.

  In both the first and second embodiments, this embodiment is controlled so that the drain voltage V1 of the first FET is equal to the output voltage of the Gm compensation bias circuit. In the first and second embodiments, first and second auxiliary FETs corresponding to replicas of the first and second FETs are prepared, and the voltage V3 corresponding to the drain voltage V1 of the first FET is a comparator COM of the stabilization bias circuit. Has been entered. On the other hand, in the third embodiment, the drain voltage V1 of the first FET is input to the comparator COM of the stabilizing bias circuit via the low pass filter LPF. Since the first and second auxiliary FETs need not be provided, the third embodiment is advantageous in that the circuit configuration is simplified. In the first and second embodiments, since the drain voltage V1 of the first FET to be controlled is not fed back to the comparator side, unnecessary parasitic elements are not formed at the drain of the first FET, and the viewpoint of stable operation of the amplifier Is advantageous.

  FIG. 9 shows an amplifying device according to a fourth embodiment of the present invention. The amplifying device includes a Gm compensation bias circuit, a stabilization bias circuit, and a mixer. Since the Gm compensation bias circuit and the stabilization bias circuit are the same as those already described with reference to FIG. 5, redundant description is omitted. In the fourth embodiment, a portion corresponding to the amplifier of the first to third embodiments constitutes a mixer. The mixer receives the signal S1 and the signal S2, and outputs a signal Sout obtained by multiplying them. As an example, a mixer may be used for the frequency conversion unit of the radio communication device, the signal S1 may correspond to the local transmission frequency signal (Lo), and the signal S2 may correspond to the radio frequency signal.

  The mixer includes two sets of differential amplifiers in a parallel positional relationship. The transistor pair includes two N-channel field effect transistors (referred to as sixth and seventh FETs), and output resistors R are connected between the high potential source and the drains of the sixth and seventh FETs, respectively. The gates of the sixth and seventh FETs receive one signal S1 to be multiplied, the sources are connected to each other, and the potential of the connection node is referred to as V5 for convenience. It has an N channel field effect transistor (referred to as a fifth FET) having a drain connected to the connection node, a gate connected to the output of the Gm compensation bias circuit, and a source connected to a low potential source. The gate of the fifth FET receives the other signal S2 to be multiplied.

  The other differential amplifier also includes a transistor pair and a current source. The transistor pair includes two N-channel field effect transistors (referred to as ninth and tenth FETs). The drains of the ninth and tenth FETs are connected to the drains of the sixth and seventh FETs, respectively, and are thus connected to the output resistor R, respectively. The gates of the ninth and tenth FETs receive one signal S1 to be multiplied, the sources are connected to each other, and the potential of the connection node is referred to as V5 ′ for convenience. It has an N channel field effect transistor (referred to as the 8th FET) having a drain connected to the connection node, a gate connected to the output of the Gm compensation bias circuit, and a source connected to a low potential source. The gate of the eighth FET receives the other signal S2 to be multiplied.

  The first FET of the amplifiers of the first to third embodiments can be associated with the fifth FET of the fourth embodiment. The second FETs of the amplifiers of the first to third embodiments can be related to the sixth and seventh FETs of the fourth embodiment. Similarly to the case where the drain voltage V1 of the first FET is stabilized in the first to third embodiments, the drain voltage V5 of the fifth FET and the drain voltage V5 ′ of the eighth FET are stabilized in the fourth embodiment. More specifically, the fifth and eighth FETs are associated with the first auxiliary FET, and the sixth and seventh FET transistor pairs and the ninth and tenth FET transistor pairs are associated with the second auxiliary FET. Accordingly, when the output voltage of the Gm compensation bias circuit and the drain voltage V1 ′ of the first auxiliary FET are made equal by the stabilizing bias circuit, the drain voltage V5 of the fifth FET, the drain voltage V5 ′ of the eighth FET, and the Gm compensation. The output voltage of the bias circuit becomes equal (V3 = V4 = V1 ′ = V5 = V5 ′). As a result, the gain of the amplifier used in the mixer can be stabilized.

  FIG. 10 shows a comparison result by simulation between the fourth embodiment and the conventional example. When a large number of amplifying devices including the mixer of FIG. 9 and the conventional bias example (constant voltage source) are manufactured, what value (that is, how the gain of the amplifying device takes) is simulated. The typical value (TYP), minimum value (MIN), and maximum value (MAX) of the gain were determined. When a large number of amplifying devices including the mixer and the bias circuit of FIG. 9 are manufactured, the value of the gain of the amplifying device (that is, how the gain varies) is simulated, and a typical value of the gain (TYP ), Minimum value (MIN) and maximum value (MAX). In the simulation, manufacturing process variation and operating temperature were also taken into account.

  As shown on the left side of FIG. 10, when a conventional bias circuit (constant voltage source) is used, the minimum gain value 3.3 is −4.8 dB (−60% relative to the typical value 8.1). ) Is also deviating, the maximum value of 9.9 is deviating by +1.8 dB (+ 22%) from the typical value of 8.1, and the variation range is 82% of the typical value. . On the other hand, when the bias circuit of the fourth embodiment is used, as shown in the right side of FIG. 10, the minimum gain value 5.4 is −2.7 dB (− 33%), the maximum value of the gain 9.1 deviates only +1.0 dB (+ 12%) from the typical value 8.1, and the variation range is 45% of the typical value. (It only takes about 1/2 of the conventional one.) Therefore, according to the present embodiment, the gain can be stabilized more than before.

  Although the present invention has been described above with reference to specific embodiments, the present invention is not limited to the circuit configuration of the amplifier described, and may be used in any appropriate amplifier that achieves gain stabilization.

  Each embodiment is merely illustrative, and those skilled in the art will appreciate various variations, modifications, alternatives, substitutions, and the like. For example, the logic combining the FETs may be positive logic or negative logic. That is, the polarities of the N channel and P channel may be reversed from those already described. Although specific numerical examples have been described in order to facilitate understanding of the invention, these numerical values are merely examples and any appropriate values may be used unless otherwise specified. The division of each embodiment is not essential to the present invention, and two or more embodiments may be used as necessary. For convenience of explanation, an apparatus according to an embodiment of the present invention has been described using a functional block diagram, but such an apparatus may be realized by hardware, software, or a combination thereof. The present invention is not limited to the above embodiments, and various modifications, modifications, alternatives, substitutions, and the like are included in the present invention without departing from the spirit of the present invention.

Hereinafter, the means taught by the present invention will be listed as an example.
(Appendix 1)
The load resistor and the drain of the second FET are connected,
An amplifier having a structure in which the source of the second FET and the drain of the first FET are connected;
A first bias circuit for supplying a first bias current to the first FET;
A second bias circuit for supplying a second bias voltage to the gate of the second FET;
And the second bias circuit includes:
An amplifying apparatus comprising a comparator for supplying a control signal to the gate of the second FET so that a bias voltage at a connection node of the first and second FETs and an output voltage of the first bias circuit are linked.
(Appendix 2)
In Appendix 1,
An amplifying device having a comparator for supplying a control signal to the gate of the second FET so that the bias voltage at the connection node of the first and second FETs is equal to the output voltage of the first bias circuit.
(Appendix 3)
The second bias circuit includes:
A first auxiliary FET having a gate connected to the output of the first bias circuit;
A second auxiliary FET whose source is connected in series to the drain of the first auxiliary FET via a connection node;
A comparator for comparing the output voltage of the first bias circuit and the voltage of the connection node, and providing a signal indicating the comparison result to the gate of the second FET and the gate of the second auxiliary FET;
The amplifying device according to Supplementary Note 1 or 2, wherein (3)
(Appendix 4)
The second bias circuit includes:
A low pass filter having an input connected to a connection node of the first and second FETs;
A comparator for comparing the output voltage of the first bias circuit and the output voltage of the low-pass filter, and providing a signal indicating the comparison result to the gate of the second FET;
The amplifying device according to claim 1, comprising:
(Appendix 5)
The first bias circuit includes:
A third FET having a first electrode and a second electrode through which a first current flows and having a gate connected to the first electrode;
A fourth FET having a first electrode and a second electrode through which a second current flows and having a gate connected to the gate of the third FET;
A first resistor connected to a second electrode of the third FET or a second electrode of the fourth FET;
A comparator that outputs a signal corresponding to a comparison result of a first voltage that is a voltage of the first electrode of the third FET and a second voltage that is a voltage of the first electrode of the fourth FET;
The amplification device according to appendix 3 or 4, wherein the first current and the second current are controlled so that the first voltage and the second voltage are equalized by a signal output from the comparison device .
(Appendix 6)
The third and fourth FETs are N-channel FETs, a P-channel FET is provided as the first current source between the first electrode of the third FET and a high potential source, and the first electrode of the fourth FET is A P-channel FET is provided as a second current source in the previous period with the potential source, and the second electrode of the third FET or one second electrode of the fourth FET is connected to the low potential source via the first resistor. The amplification device according to appendix 5, wherein the second electrode of the other FET on the side to which the first resistor is not connected is connected to a low potential source.
(Appendix 7)
The third and fourth FETs are P-channel FETs, an N-channel FET is provided as the first current source between the first electrode of the third FET and a low potential source, and the first electrode of the fourth FET is low An N-channel FET is provided as a second current source in the previous period with the potential source, and the second electrode of the third FET or one second electrode of the fourth FET is connected to the high potential source via the first resistor. The amplification device according to appendix 5, wherein the second electrode of the other FET on the side to which the first resistor is not connected is connected to a high potential source.
(Appendix 8)
The amplifying apparatus according to appendix 1, wherein the comparison device of the first bias circuit includes an operational amplifier.
(Appendix 9)
The amplifying apparatus according to appendix 1, wherein the first FET is connected to a low potential source via a strain relief resistor.
(Appendix 10)
The amplifying apparatus according to appendix 2, wherein the first FET and the first auxiliary FET are connected to a low potential source through a strain relief resistor, respectively.
(Appendix 11)
The amplification device according to appendix 2, wherein the first and second auxiliary FETs are connected in series via a voltage adjustment resistor.
(Appendix 12)
The amplifying apparatus according to appendix 1, wherein the comparison device includes an operational amplifier.
(Appendix 13)
The first bias circuit includes:
A third FET having a first electrode and a second electrode through which a first current flows and having a gate connected to the first electrode;
A fourth FET having a first electrode and a second electrode through which a second current flows and having a gate connected to the gate of the third FET;
A first resistor connected to the second electrode of the third FET or the second electrode of the previous fourth FET;
A current mirror circuit connected to the first electrode of the third FET and the first electrode of the fourth FET;
The amplifying apparatus according to any one of supplementary notes 1-4.
(Appendix 14)
The amplifying apparatus according to claim 11, wherein the first signal is input to a gate of the first FET, and the second signal is input to the second FET.
(Appendix 15)
The amplification device according to any one of appendices 1 to 3, and 4 to 6, wherein sources of the first FET and the first auxiliary FET are connected to a low potential source or a high potential source via a resistor.
(Appendix 16)
The amplifier has a first terminal for inputting a first signal and a second terminal for receiving a second signal, and constitutes a Gilbert cell mixer that outputs a third signal obtained by multiplying the first and second signals. The amplifying apparatus according to any one of appendices 1 to 3, and 4 to 6, wherein the first bias circuit supplies a bias voltage to the first terminal, and the second bias circuit supplies a bias voltage to the second terminal.
(Appendix 17)
Supplying a second bias current to the second FET of the amplifier circuit having a load resistor and a structure in which the first and second FETs are connected in series and having a Gm compensation bias circuit for supplying the first bias current to the first FET. A stabilizing bias circuit,
A stabilizing bias circuit having a comparator for supplying a control signal to the gate of the second FET so that a bias voltage at a connection node of the first and second FETs is equal to an output voltage of the Gm compensation bias circuit.
(Appendix 18)
A first auxiliary FET having a gate connected to the output of the Gm compensation bias circuit;
A second auxiliary FET connected in series to the first auxiliary FET via a connection node;
The comparison device compares the output voltage of the Gm compensation bias circuit and the voltage of the connection node, and supplies a control signal indicating a comparison result to the gate of the second FET and to the gate of the second auxiliary FET. 18. The stabilization bias circuit according to 17.
(Appendix 19)
And a low-pass filter having an input connected to a connection node of the first and second FETs, and the comparison device compares the output voltage of the Gm compensation bias circuit and the output voltage of the low-pass filter, and compares the result. The stabilizing bias circuit according to appendix 17, wherein a control signal to be shown is applied to the gate of the second FET.
(Appendix 20)
The stabilization bias circuit according to appendix 18, wherein the first auxiliary FET is connected to a low potential source via a strain relief resistor.
(Appendix 21)
The stabilizing bias circuit according to appendix 18, wherein the first and second auxiliary FETs are connected in series via a voltage adjusting resistor.
(Appendix 22)
18. The stabilization bias circuit according to appendix 17, wherein the comparison device includes an operational amplifier.

It is a figure which shows an example of an amplifier. It is a figure which shows typically the drain current voltage characteristic of FET. 1 is a diagram illustrating an amplifying apparatus according to a first embodiment of the present invention. It is a figure which shows a mode that the conventional circuit was used for the Gm compensation bias circuit. It is a figure which shows the amplifier by 2nd Example of this invention. The operation | movement explanatory drawing of a Gm compensation bias circuit is shown. It is a figure which shows a modification. It is a figure which shows the amplifier by 3rd Example of this invention. It is a figure which shows the amplifier by 4th Example of this invention. It is a figure which shows a simulation result.

Explanation of symbols

Gm, gm mutual conductance
Rs Source resistance
Iref reference current
Ibi bias current
COM comparison device

Claims (10)

The load resistor and the drain of the second FET are connected,
An amplifier having a structure in which the source of the second FET and the drain of the first FET are connected;
A first bias circuit for supplying a first bias current to the first FET;
A second bias circuit for supplying a second bias voltage to the gate of the second FET;
And the second bias circuit includes:
An amplifying apparatus comprising a comparator for supplying a control signal to the gate of the second FET so that a bias voltage at a connection node of the first and second FETs and an output voltage of the first bias circuit are linked. In claim 1,
An amplifying device having a comparator for supplying a control signal to the gate of the second FET so that the bias voltage at the connection node of the first and second FETs is equal to the output voltage of the first bias circuit. The second bias circuit includes:
A first auxiliary FET having a gate connected to the output of the first bias circuit;
A second auxiliary FET whose source is connected in series to the drain of the first auxiliary FET via a connection node;
A comparator for comparing the output voltage of the first bias circuit and the voltage of the connection node, and providing a signal indicating the comparison result to the gate of the second FET and the gate of the second auxiliary FET;
The amplifying device according to claim 1, comprising: The second bias circuit includes:
A low pass filter having an input connected to a connection node of the first and second FETs;
A comparator for comparing the output voltage of the first bias circuit and the output voltage of the low-pass filter, and providing a signal indicating the comparison result to the gate of the second FET;
The amplifying device according to claim 1, comprising: The first bias circuit includes:
A third FET having a first electrode and a second electrode through which a first current flows and having a gate connected to the first electrode;
A fourth FET having a first electrode and a second electrode through which a second current flows and having a gate connected to the gate of the third FET;
A first resistor connected to a second electrode of the third FET or a second electrode of the fourth FET;
A comparator that outputs a signal corresponding to a comparison result of a first voltage that is a voltage of the first electrode of the third FET and a second voltage that is a voltage of the first electrode of the fourth FET;
5. The amplification according to claim 3, wherein the first current and the second current are controlled so that the first voltage and the second voltage are equalized by a signal output from the comparison device. apparatus. The third and fourth FETs are N-channel FETs, a P-channel FET is provided as the first current source between the first electrode of the third FET and a high potential source, and the first electrode of the fourth FET is P-channel FET is provided as a pre-Symbol second current source between the potential source, one of the second electrodes of the second electrode or the first 4FET of the first 3FET is connected to the low potential source via a first resistor The amplification device according to claim 5, wherein the second electrode of the other FET on the side to which the first resistor is not connected is connected to a low potential source. The third and fourth FETs are P-channel FETs, an N-channel FET is provided as the first current source between the first electrode of the third FET and a low potential source, and the first electrode of the fourth FET is low N-channel FET is provided as a pre-Symbol second current source between the potential source, one of the second electrodes of the second electrode or the first 4FET of the first 3FET is connected to the high potential source via a first resistor The amplifying apparatus according to claim 5, wherein the second electrode of the other FET on the side to which the first resistor is not connected is connected to a high potential source. The first bias circuit includes:
A first 3FET that having a first electrode and a second electrode first current flows,
A first 4FET having a second current having a first electrode and a second electrode flows, connected to said Gate of the 3FET gate,
A first resistor connected to the second electrode of the second electrode or previous SL first 4FET of the first 3FET,
A current mirror circuit connected to the first electrode of the third FET and the first electrode of the fourth FET;
The amplification device according to claim 1 , comprising: The source of the first 1FET and first auxiliary FET via the resistor Ru is connected to the low potential source or a high potential source, the amplifier device according to any one of claims 1-6. The amplifier has a first terminal for inputting a first signal and a second terminal for receiving a second signal, and constitutes a Gilbert cell mixer that outputs a third signal obtained by multiplying the first and second signals. The amplification according to any one of claims 1 to 6 , wherein the first bias circuit supplies a bias voltage to the first terminal, and the second bias circuit supplies a bias voltage to the second terminal. apparatus.

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