CN115225048A

CN115225048A - Amplifier circuit, corresponding device and method

Info

Publication number: CN115225048A
Application number: CN202210398389.4A
Authority: CN
Inventors: A·贝托里尼; G·尼科利尼
Original assignee: STMicroelectronics SRL
Current assignee: STMicroelectronics SRL
Priority date: 2021-04-16
Filing date: 2022-04-15
Publication date: 2022-10-21
Also published as: US20220337198A1

Abstract

The amplifier circuit includes a first input stage having a differential input transistor pair and a second gain stage having an output node coupled to a load. A node in the first gain stage is coupled to an output node in the second gain stage. A feedback line couples the output node to a control node of a first transistor of the differential input transistor pair. A current mirror circuit system is coupled to a current flow path through the further transistor in the second gain stage and includes a sense node configured to generate a sense signal indicative of a current supplied to the load. The sense signal at the sense node is fed directly back to the control node of the first transistor of the differential input transistor pair to provide a zero in the loop transfer function that matches and tracks and cancels the load-dependent pole.

Description

Amplifier circuit, corresponding device and method

Priority requirement

The present application claims priority to italian patent application No. 102021000009653, filed on 16/4/2021, the contents of which are incorporated by reference in their entirety to the maximum extent allowed by law.

Technical Field

The description relates to amplifier circuits.

One or more embodiments may be advantageously applied to amplifiers with accurate signal amplification.

Background

Despite the continuing activity in this area, there is still a need for amplifiers that exhibit improved performance in terms of precise signal amplification (e.g., accuracy better than 0.1%), large output swing (e.g., near supply voltage), and stable behavior for a wide range of capacitive loads (almost any capacitive load).

There is a need in the art to provide an improved amplifier that meets this need.

Disclosure of Invention

One or more embodiments may be directed to an amplifier circuit.

One or more embodiments may relate to a corresponding apparatus.

Devices comprising electrostatic and/or piezoelectric actuators, for example with associated capacitance values from a few pF to a few tens nF, may be examples of such devices.

One or more embodiments may relate to a corresponding design method.

One or more embodiments may provide one or more of the following advantages: simplicity, as long as one transistor and one current generator are added (or in the case of a class AB amplifier, only two transistors are added); negligible extra area and power consumption; accurate closed loop gain; large output voltage swing (close to V) _CC ) (ii) a Stability of large-scale capacitive loads; and is easily extended to fully differential amplifiers.

In one embodiment, a circuit includes: a first gain stage having a differential input transistor pair and a bias current source, the differential input transistor pair including first and second transistors having respective control nodes and respective current flow paths therethrough, and the bias current source being coupled to the respective current flow paths through the first and second transistors, wherein the control nodes of the first and second transistors are configured to apply an input signal therebetween, and the second transistor is located between the bias current source and a coupling node in the current flow path through the second transistor; and a second gain stage having an output node configured to be coupled to a load and to apply an output voltage thereto, the output voltage being a function of an input signal applied between the control nodes of the first and second transistors, wherein the second gain stage includes a further current flow path through at least one further transistor.

The circuit further comprises: a coupling network of the second gain stage to the first second gain stage, the coupling network coupling a coupling node in the first gain stage to an output node in the second gain stage; and a feedback line coupling the output node in the second gain stage to the control node of the first transistor in the first gain stage.

The circuit further comprises: a current mirror circuit system coupled to the further current flow path through the at least one further transistor in the second gain stage, the current mirror circuit system comprising a current mirror flow line between a power supply line and ground, wherein a sense node in the current mirror flow line is configured to generate a sense signal indicative of a current supplied to the load at an output node; and a coupling line coupling a sense node in the current mirror flow line in the second gainstage to a control node of the first transistor in the first gainstage, wherein a sense signal at the sense node is fed back to the control node of the first transistor in the first gainstage.

In an embodiment, a circuit includes: a differential input stage comprising a pair of input transistors having control terminals configured to receive a first signal and a second signal, wherein a first input transistor of the pair of input transistors generates a differential signal; an output stage comprising an output transistor having a control terminal configured to receive a differential signal and a drain terminal that generates an output signal; a resistive feedback circuit coupled between a drain terminal of an output transistor and a control terminal of a second input transistor of the pair of input transistors; a sense transistor connected to the output transistor in a current mirror circuit, the sense transistor having a control terminal configured to receive a differential signal and a drain terminal that generates a sense signal indicative of a current delivered by an output signal; and a feedback path configured to apply a sense signal to the second input transistor of the input transistor pair.

Drawings

One or more embodiments will now be described, by way of example only, with reference to the accompanying drawings, in which:

FIG. 1 is an amplifying circuit diagram;

fig. 2 illustrates details of a possible two-stage implementation of the amplifier circuit as illustrated in fig. 1;

fig. 3 and fig. 4A, 4B are gain versus frequency graphs for amplifier circuits, showing possible stable/unstable behavior;

FIG. 5 is a circuit diagram illustrating a possible implementation of a class A amplifier circuit in an inverting configuration according to embodiments of the present description;

FIG. 6 is a circuit diagram illustrating a possible implementation of a class A amplifier circuit in a non-inverting configuration according to embodiments of the present description;

fig. 7 is a circuit diagram illustrating a possible implementation of a class AB amplifier circuit in an inverting configuration according to embodiments of the present description; and

fig. 8 is a circuit diagram illustrating a possible implementation of a class AB amplifier circuit in a non-inverting configuration according to embodiments of the present description.

Detailed Description

In the following description, one or more specific details are set forth in order to provide a thorough understanding of examples of embodiments of the present description. Embodiments may be obtained without one or more of the specific details, or with other methods, components, materials, etc. In other instances, well-known structures, materials, or operations are not shown or described in detail so as not to obscure certain aspects of the embodiments.

Reference to "an embodiment" or "one embodiment" within the framework of the specification is intended to indicate that a particular configuration, structure, or characteristic described in connection with the embodiment is included in at least one embodiment. Thus, phrases such as "in an embodiment" or "in one embodiment" that may be present in one or more points of the specification do not necessarily refer to one and the same embodiment.

Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

Headings/references used herein are provided for convenience only and thus do not define the scope of protection or the scope of the embodiments.

For simplicity and ease of explanation, throughout the description: the same label may be used to designate a line or node and a signal (e.g., V) that may be present at that node _IN 、V _OUT ) (ii) a The same reference numbers may be used to designate a certain component (e.g., a resistor or capacitor) and an associated electrical parameter (e.g., resistance or capacitance); like parts or elements in the various figures are indicated with like reference numerals and corresponding description is not repeated for each figure.

Fig. 1 is a basic circuit diagram of an amplifier circuit 10 that may be considered for applications that require (very) accurate signal amplification (e.g. better than 0.1% accuracy), large output swing (e.g. close to the supply voltage) and stability under any capacitive load.

The circuit of fig. 1 surrounds a differential gain stage a _V Is constructed, provided with a (very) high gain (a) _V >>1)。

As illustrated in FIG. 1, gain stage A _V Having a non-inverting input (+) at a reference (e.g., common mode) voltage V _CM Is coupled to the node and is configured to receive the signal via a first resistor R ₁ And is applied to the (voltage) input signal V of the inverting input (-) _IN 。

Responsive to (voltage) input signal V _IN Is applied to the first resistor R ₁ The amplifier circuit 10 is configured to generate at its output a (voltage) output signal V _OUT To be applied to a capacitive load C _L ，

As illustrated in FIG. 1, gain stage A _V Having a second resistor R coupled between the output node and the inverting input (-) ₂ To provide a (negative) feedback line to set the ratio V _OUT /V _IN (assume gain stage A) _V With very high gain).

The general representation of fig. 1 also applies to the voltage V _CM And V _IN The "non-inverting" configuration of the exchange: corresponding configurations will be discussed below in conjunction with fig. 6 and 8.

Especially when the capacitive load has a very large value, the arrangement as illustrated in fig. 1 is not subject to strict specifications in terms of closed loop bandwidth.

This helps to achieve a reasonable trade-off between (large) load capacitance and amplifier bandwidth.

In principle, a single amplifier stage will be able to drive almost any capacitive load without causing stability problems.

However, a single stage (even of the telescopic or folded cascade type) may not have sufficient DC open loop gain when the load has resistive feedback. Furthermore, a single stage may not be able to bring the output swing close to the supply voltage.

To solve these problems, a two-stage amplifier circuit may be used.

A well-known two-stage Operational Transconductance Amplifier (OTA) is a so-called miller amplifier, as illustrated in fig. 2.

As illustrated in fig. 2, such an amplifier comprises a current generator I _B1 Of the first differential stage A1, a current generator I _B1 Coupled to a voltage V _CC And is configured to supply a bias current at node B towards a parallel connection of a first current flow line and a second current flow line between node B and ground GND.

The first current flow line includes a first transistor pair, i.e., transistor M _1A And a (diode-connected) transistor M _2A The cascade current flow path (source-drain, in the exemplary case of a MOSFET transistor considered herein).

The second current flow line comprises a second transistor pair, i.e. transistor M _1B And a transistor M _2B The cascade current flow path (source-drain, in the exemplary case of MOSFET transistors considered herein).

Differential input voltages (IN + and IN-) are applied to the transistor M _1B (which is arranged at node B and transistor M) _2B In between) and a transistor M _1A (which is arranged at node B and transistor M) _2A In between) on the control terminal (gate, in the exemplary case of MOSFET transistors considered herein).

Transistor M _2A And M _2B With their control terminals (gates, in the exemplary case of MOSFET transistors considered herein) coupled to each other in a current mirror configuration.

As illustrated in fig. 2, the second stage A2 comprises a current generator I _B The current generator I _B Is coupled again to voltage V _CC The power line of (1). Such a current generator is at node C (which also provides an output node OUT, which is shown with a capacitive load C coupled thereto _L ) Through a transistor M arranged intermediate node C/OUT and ground GND ₃ A bias current is supplied to the current flow path (source-drain, in the exemplary case of the MOSFET transistor considered herein).

As illustrated in fig. 2, transistor M ₃ At the transistor M (gate, in the exemplary case of a MOSFET transistor considered herein) _1B And M _2B The middle node D is coupled to the second current flow line in the first stage A1.

The first stage A1 and the second stage A2 are further connected via a capacitor C _C And a resistor R _Z Is coupled between node C/OUT and node D.

It can be seen that the transfer function of the circuit illustrated in fig. 2 has a pole p given by the equation _d 、p ₁ And p ₂ And zero point Z ₁ ：

Wherein: c _C 、C _L 、R _Z Capacitance and resistance values for the same-name components illustrated in fig. 2; r is _out Is the total resistance at the output node, i.e. the transistor M in parallel with the (external) resistive feedback ₃ The output resistance of (1); r is ₀₁ Is the output resistance of the first stage A1, i.e., the AND transistor M _1B Transistor M with parallel-connected output resistors _2B The output resistance of (1); g is a radical of formula _m3 Is a transistor M ₃ Transconductance of (1); and C _GS3 Is a MOSFET transistor M ₃ Of (parasitic) gate-source capacitance.

Due to the fact that for R _Z P2 is at a high frequency, so R is usually chosen _Z To null the Right Hand Plane (RHP) Z ₁ Move to infinity.

However, in the known C _L In those cases, the designer may choose to move the zero point from the right-hand plane (RHP) to the left-hand plane (LHP) by:

so as to eliminate the first non-dominant pole p of the left-hand plane (LHP) zero ₁ 。

The result is shown in fig. 3, in which the loop gain G of an amplifier circuit comprising the two-stage miller amplifier of fig. 2 is plotted against the frequency f (abscissa) _loop (ordinate)An arbitrary value).

The corresponding Unity Gain Bandwidth (UGB) is:

wherein g is _m1 Mark transistor M _1A And M _1B Transconductance of (1).

In the vicinity of UGB, G _loop The slope of the graph is, for example, 20 dB/decade (decade), and the amplifier is stable according to well-known control theory.

However, it is worth noting that this approach suffers from two inherent drawbacks.

First, if C _L Very high, then R _Z Or C _C It becomes equally high and the corresponding components (resistors/capacitors) become too large and are in fact incompatible with integration in an integrated circuit chip.

As a first example: if C is present _L =1 μ F → hypothesis g _m3 =100 μ A/V and C _C =10pF, then R _Z ＝1GOhm。

As a second example: if C is _L =1 μ F → hypothetical g _m3 =100 μ A/V and R _Z =10kOhm, then C _C ＝1μF

Furthermore, g _m 、C _C 、R _Z And C _L An extension in mass production may generate a large random mismatch between the poles to be cancelled and the cancellation zeros.

That is, uncontrolled pole/zero double peaks may be generated, which may cause the amplifier to be in an unstable state, as shown in fig. 4A and 4B.

In fig. 4A and 4B, the loop gain G is plotted against the frequency f (abscissa) _loop (ordinate, arbitrary value).

Specifically, FIG. 4A shows that the expansion may move a pole at a frequency lower than the zero, while FIG. 4B depicts the opposite situation, i.e., the zero is moved to a frequency lower than the pole.

In both cases, the rootAround UGB, G, according to well-known control theory _loop May be, for example, 40 dB/decade, and the amplifier is unstable.

Therefore, the solution discussed in connection with fig. 2 is not satisfactory at the load capacitance C _L May result in unstable circuits.

In this regard, it is noted that the load itself, although illustrated and discussed herein for the sake of explanation and understanding, may represent a different element than the amplifier circuit.

For example, the amplifier circuit and the load may be provided by different vendors to the device manufacturer, where the load is ultimately coupled to the amplifier circuit.

One or more embodiments relate to the use of _loop In order to track the output pole in a theoretically perfect way, independent of process, temperature and supply voltage factors.

In one or more embodiments, this may be supplied to load C by sensing ("reading") _L Outputs a current and feeds it back to a node in the loop so as to be at G _loop Creating a load dependent capacitance C _L Zero point of (c).

It is again noted that although illustrated and discussed herein for the sake of explanation and understanding, the load itself may represent a different element from the amplifier circuit.

A first possible implementation is illustrated in fig. 5.

In fig. 5 (and in fig. 6, 7 and 8), the parts, elements or entities are indicated with the same reference numerals/signs as the parts, elements or entities already discussed in connection with the previous figures: for the sake of brevity, corresponding descriptions will not be repeated for each of these figures.

Furthermore, to avoid over-complicating the present description, the general description of the two-stage amplifier provided in connection with fig. 2 will not be repeated. Thus, unless the context and associated additional disclosure indicates otherwise, the general description of the two-stage amplifier provided in connection with fig. 2 applies in comparison to fig. 5-8.

Indeed, the circuit diagrams of fig. 5 to 8 can be seen as examples of a circuit (similar to the circuit of fig. 2) comprising a first gain stage A1 comprising: a differential input transistor pair including a first transistor M having a respective control node and a current flow path therethrough _1A And a second transistor M _1B (ii) a Coupled (at node B) to the first transistor M _1A And a second transistor M _1B Of the current flow path of _B1 And a first transistor M configured to apply an input signal therebetween _1A And a second transistor M _1B The control node of (2).

As discussed below, all of the circuit diagrams illustrated in fig. 5-8 include a (first) feedback line comprising a resistor pair R in a voltage divider configuration ₁ 、R ₂ 。

One of these resistors (i.e. R) ₂ ) Will the output node V of the amplifier _OUT (hereinafter also referred to as node C) and a first transistor M _1A Is coupled (gate, in the exemplary case of MOSFET transistors considered herein).

The other resistor of the pair (i.e. R) ₁ ) Coupled to the first transistor M _1A And is configured to supply a voltage to the first transistor M _1A The control node of (a) applies: in the inverting configuration as illustrated in fig. 5 and 7 — input signal V _IN Wherein the second transistor M _1B Has applied thereto a reference signal V _CM (ii) a Or in a non-inverted configuration as illustrated in FIGS. 6 and 8-reference signal V _CM Wherein the second transistor M _1B Has applied thereto an input signal V _IN 。

Whatever the arrangement adopted, the first transistor M _1A And a second transistor M _1B Is configured to apply an input signal therebetween, which may be via a resistor R, as illustrated in fig. 5-8 ₁ 。

As illustrated, the firstTwo transistors M _1B Is located through the second transistor M _1B In the current flow path of _B1 (node B) and a coupling node D.

Also, the circuit diagrams of fig. 5-8 include a circuit having an output node C (or V) _OUT ) The output node C (or V) of the second gain stage A2 _OUT ) Is configured to be coupled to a load C _L And applying an output voltage V to the load _OUT Output voltage V _OUT Is applied to the first transistor M _1A And a second transistor M _1B As a function of the input signal between the control nodes.

In the exemplary implementation of fig. 5, the second stage A2 includes a current mirror circuit including a transistor M _3R The control terminal (gate, in the exemplary case of a MOSFET transistor considered here) of which is coupled to the transistor M ₃ With associated bias current generator I _BR 。

Such a current mirror circuit thus provides a slave supply line V _CC Current flow line to ground GND which will include transistor M ₃ And associated bias current generator I _B The output current flow lines of (a) are mirrored.

In that way, the transistor M _3R Can "read" the inflow to C _L Current (in the current path via transistor M) _3R Transistor M for mirroring ₃ Under control of) and sends a corresponding signal back to the resistor R in the resistive feedback network ₁ And R ₂ With a common node X in between, node X representing a virtual ground node.

Thus, the implementation of fig. 5 is an example of a circuit that includes a coupling network of the second gain stage A2 to the first gain stage A1.

As illustrated, the coupling network includes a capacitor C _C Which couples the coupling node D in the first gain stage A1 to the output node C or V in the second gain stage A2 _OUT . In contrast to fig. 2, in the exemplary implementation of fig. 5, a return-to-zero resistor R in the coupling network between stages A1 and A2 _Z May be omitted so long as one or more embodiments discussed hereinThe introduction of a left-hand plane (LHP) zero point is envisaged.

As previously discussed, provision is made to include a resistor R ₁ 、R ₂ Via a resistor R ₂ The output node C (or V) in the second gain stage A2 _OUT ) Coupled to a first transistor M in a first gain stage A1 _1A The control node of (2).

In the exemplary implementation of fig. 5, the circuit 10 includes a current mirror circuit system I _BR 、M _3R Coupled through a transistor M in the second gain stage A2 ₃ The current flow path of (2). As illustrated, the current mirror circuit system I _BR 、M _3R Included in the supply line VC) and ground GND, in which a sense node E is present, configured to generate an indication at an output node V _OUT Is supplied to the load C _L Is detected by the current sensor.

In the exemplary implementation of fig. 5, a coupling line 100 is provided that couples a sensing node E in the current mirror flow line to a first transistor M in the first gain stage A1 _1A The control node of (2). Thus, the sensing signal at the sensing node E is fed back to the first transistor M in the first gain stage A1 _1A The control node of (2).

It can be seen that in the exemplary implementation of fig. 5, the poles and zeros in the transfer function of Gloop are given by the following equations:

wherein the various entities indicated have the same meaning as previously described.

Can reasonably maintain approximate g _m3R <<g _m3 In applications, provided that the output stage is biased more than through transistor M _3R The mirror current of (c) flows a much higher current than the line.

Advantageously, the transistor M is regulated _3R And a bias generator I _BR So that g is _m3R R ₂ =1 leads to the following relationship:

this corresponds to an almost perfect mutual cancellation of the output poles and zeros.

By satisfying the condition g under all process, voltage and temperature (PVT) conditions _m3R R ₂ =1, such zero-pole cancellation can be facilitated.

This can be achieved by: transistor M ₃ And M _3R Configured (in a manner known per se) to operate in weak inversion (gate-source voltage below threshold voltage) and to select R ₂ Resistors R of the same type _bias ＝αR ₂ Inversely proportional bias current I of PTAT _B And I _BR (proportional to absolute temperature) type (in short, bias current source I _B And I _BR Is configured to provide and feedback a resistor R ₂ Current in inverse proportion to the resistance of (c).

In this way:

wherein V _T Is the thermal voltage, η is a parameter of the weak inversion transistor, and N is an integer.

Therefore, by sufficiently selecting N and α, it is (always) possible to satisfy the relationship g _m3R R ₂ =1, andPVT conditions are irrelevant.

Due to this zero-pole cancellation, the amplifier circuit as illustrated in fig. 5 was found to exhibit a behavior exactly similar to that of a single-pole OTA in terms of stability, with an essentially stable capability, while being compatible with a capacitive load C _L Is independent of the value of (very) small compensation capacitor C even in the presence of _C (e.g., 1 pF).

This may apply, for example, to closed loop gains ranging from 0dB to +20dB, where C _L Varying from 0.1pF to 10nf _C =1pF. In all cases considered, the phase margin was found to be always (much) above 60 degrees, showing a completely sufficient stability.

With respect to closed-loop behavior, the closed-loop bandwidth is equal to the Gloop's original Unity Gain Bandwidth (UGB) and the zero frequency z, due to the introduction of the zero in the feedback path (rather than in the forward path) ₁ Lower value in between, and the in-band Gain-Gain (Gain) can be expressed as:

for gains of 0dB and 20dB, at C _L Fully adequate performance was tested at input and output voltages equal to 10pF, 100pF, 1nF and 10nF, respectively, with sine wave inputs of 100kHz, 10kHz, 1kHz and 100 Hz.

The foregoing discussion applies step by step to the non-inverting configuration of the amplifier circuit 10 illustrated in fig. 6, where the voltage V is _CM (see FIG. 1) is exchanged for V _IN 。

In the case of FIG. 6, G _loop The poles and zeros and the closed loop poles in the transfer function of (a) are the same as in the inverse configuration of fig. 5.

Only the in-band Gain-the Gain (Gain) is different because it is in-phase and equal to:

the circuit has the following features: current mirror circuit system I _BR 、M _3R Coupled to pass through at least one further transistor M in the second gain stage A2 ₃ The current mirror circuit system includes a current mirror circuit system in the power supply line V _CC And a current mirror flow line I between ground GND _BR 、M _3R Wherein the current mirror flows through line I _BR 、M _3R Is configured to generate a sense signal indicative of the voltage at the output node V _OUT Is supplied to the load C _L The current of (a); and a coupling line 100 coupling a sensing node E in the current mirror flow line to a first transistor M in a first gain stage A1 _1A Wherein the sense signal at the sense node E is fed back to the first transistor M in the first gain stage A1 _1A The control node of (2).

The exemplary (non-inverting) implementation of fig. 6 may share other advantageous features with the exemplary (inverting) implementation of fig. 5. For example, in both implementations of fig. 5 and 6, the second gain stage A2 is included in the supply line V _CC And a ground GND, the output current flow line including a further transistor M coupled to the ground ₃ Of the further current flow path of the respective bias current source I _B Wherein the output node V _OUT (or C) is arranged at the corresponding bias current source I _B And a further transistor M ₃ In the middle.

Furthermore, in both implementations of fig. 5 and 6, the current mirror circuit system I _BR 、M _3R Included in the power supply line V _CC And ground GND, the current mirror flow line including a current mirror coupled to a ground such as M _3R Mirror bias current source I of current mirror transistor _BR Wherein the sensing node E is arranged at the mirror bias current source I _BR And a current mirror transistor M _3R In the middle.

For example, in both implementations of fig. 5 and 6, the coupling network of the second gain stage A2 to the first gain stage A1 comprises (only) a capacitor C _C Capacitor C _C Coupling a coupling node D in a first gain stage A1 to an input in a second gain stage A2Out node C (or V) _OUT )。

In both implementations of fig. 5 and 6, in addition a transistor M ₃ And a current mirror transistor M _3R May be biased in weak inversion.

For example, in both implementations of fig. 5 and 6, the respective bias current sources I _B And a mirror bias current source I _BR May be configured to provide a current Proportional To Absolute Temperature (PTAT).

The previous discussion of the class a two stage amplifier can be extended to a class AB two stage amplifier as illustrated in fig. 7 (inverting configuration) and fig. 8 (non-inverting configuration).

As is well known to those skilled in the art, class AB amplifier operation involves a combination of class a operation (for low power output) and class B operation (for larger current output), typically achieved by pre-biasing two transistors in the amplifier output stage.

Taking a class AB amplifier architecture in the context of the discussion herein mainly involves: different topologies of the coupling network between the two stages A1, A2 are designed (in a manner known per se); and including a sense node E in the current mirror flow line configured to produce an indication at the output node V of the class AB amplifier _OUT Is supplied to the load C _L Such that the sense signal at the sense node can be fed back to the first gain stage A1 to produce a double zero-pole peak, as already discussed in connection with the implementations of fig. 5 and 6.

The class AB amplifier as illustrated by way of example in fig. 7 and 8 again comprises a first differential stage A1 with a tail bias current generator 2I _B Coupled to ground GND and at node B and a supply voltage V _CC The point B in between draws current from the parallel connection of the first current flow line and the second current flow line.

The first current flow line includes a first transistor pair, i.e., transistor M _1A And a (diode-connected) transistor M _2A The cascade current flow path (source-drain, in the exemplary case of the MOSFET transistor considered here).

Second oneThe current flow line includes a second transistor pair, i.e. transistor M _1B And a transistor M _2B The cascade current flow path (source-drain, in the exemplary case of the MOSFET transistor considered here).

Differential input voltage is applied to transistor M _1A (which is arranged at the transistor M) _2A And node B) and transistor M _1B (which is arranged at the transistor M) _2B And node B) on a control terminal (gate, in the exemplary case of a MOSFET transistor considered herein) possibly at a resistor R ₁ Under the intervention of (a).

Although with respect to bias source 2I _B Different relative arrangements are possible, but in fig. 7 and 8, those references corresponding to fig. 5 and 6 have been reserved for the transistor M _1A And M _1B They receive a differential input signal at their control terminals (gates, MOSFET transistors considered here in the exemplary case).

Likewise, in fig. 7 and 8, the labels corresponding to those in fig. 5 and 6 are reserved for the transistor M _2A And M _2B Which have mutually coupled control terminals (gates, in the exemplary case of MOSFET transistors considered herein).

Moving from left to right in the circuit diagrams of fig. 7 and 8, the class AB amplifier circuit illustrated in fig. 7 and 8 comprises a power supply line V _CC And a current flow line pair between ground GND.

In these current flow line pairs: the first one including a bias current generator I _B Coupled to a supply line V _CC And at node D ₁ To inject current into the diode-connected transistor pair M ₆ And M ₄ In the cascaded current flow path (source-drain, in the example case of a MOSFET transistor considered herein), wherein a transistor M ₆ At the current generator and the transistor M ₄ A middle part; the second one includes a bias current generator I _B Coupled to ground GND and at node D ₂ From a diode-connected transistor pair M ₇ And M ₅ Of the cascade current flow path(source-drain, in the exemplary case of a MOSFET transistor considered herein) in which transistor M sinks current ₇ At the current generator and the transistor M ₅ In the middle.

Also, moving from left to right in the circuit diagrams of fig. 7 and 8, in the class AB amplifier circuits illustrated in fig. 7 and 8, at the power supply line V _CC And ground GND, another current flow line is provided, comprising: bias current generator I _B Acting on the power supply line V _CC And a transistor M located in the first stage A1 _1B And M _2B Between (coupling) node D (hereinafter also referred to as node C) ₂ ) Middle; pass transistor M ₈ Slave node C ₂ To node C ₁ In the case of a MOSFET transistor), wherein the transistor M is a transistor ₈ Is coupled to the transistor M (gate, in the example case of a MOSFET transistor) ₆ A control terminal (gate, in the example case of a MOSFET transistor); another bias current generator I _B Acting on the transistor M ₈ (node C) ₁ ) And ground GND such that transistor M ₈ Is arranged at node C ₁ And C ₂ In the middle (i.e. between two bias current generators I) _B Intermediate, coupled to node C ₁ And C ₂ ) (ii) a And a transistor M ₉ Is arranged with a pass transistor M ₈ Coupled to node C in parallel through which ₁ And C ₂ Is used (source-drain, in the example case of a MOSFET transistor), and a transistor M ₉ Is coupled to a diode-connected transistor M (gate, in the exemplary case of a MOSFET transistor) ₇ A control terminal (gate, in the exemplary case of a MOSFET transistor).

In a class AB amplifier as illustrated in fig. 7 and 8, the second stage A2 comprises an output transistor pair M ₂ And M ₃ Which is arranged with: cascaded at a voltage from ground GND and V _CC Power supply line (transistor M) ₃ Coupled to a voltage V _CC Power supply line of (d), transistor M ₂ Coupled to ground GND) of a power supplyThe current path (source-drain, in the example case of a MOSFET transistor) through which it flows in the flow line; and their control terminals (gates, in the example case of MOSFET transistors), coupled to the transistor M ₈ And M ₉ Node C of opposite ends of the parallel connection ₁ And C ₂ Thus the transistor M ₃ Via node C ₂ Coupled to the coupling node D in the first stage A1.

In a class AB amplifier as illustrated in fig. 7 and 8, node C in the second stage A2 will output a voltage V _OUT Supplied to a capacitive load C _L The node C is arranged at the pass transistor M ₂ And M ₃ And via a current path having a capacitance value C _C A/2 capacitor coupled to node C ₁ 、C ₂ I.e. coupled to the transistor M ₂ And M ₃ A control terminal (gate, in the exemplary case of a MOSFET transistor).

It will be assumed that the following relationship applies to the class AB amplifier illustrated in figures 7 and 8:

M ₈ ＝M ₆ /2

M ₉ ＝M ₇ /2

M ₂ ＝k.M ₄

M ₃ ＝k.M ₅ 。

the meaning of these relationships (essentially the ratio of the active areas of the transistors involved) is conventional in the art.

Furthermore, in the case of class AB amplifiers as illustrated in fig. 7 and 8, the basic concept of the embodiments involves creating a zero in the Gloop's transfer function, aiming to track the output pole with high accuracy, regardless of process, temperature and supply voltage.

Here again, this approach may be through sensing ("reading") C _L And feeding it back to a node in the control loop for Gloop creation depending on the load capacitance C _L Zero point of (c).

The possible implementation illustrated in fig. 7 and 8 includes two transistors (e.g.MOSFET)M _2R And M _3R They are configured to read C _L And feeds back a corresponding sense signal at a node, here again designated as E, to R ₁ And R ₂ A common node of the feedback network in between, i.e. the virtual ground node X.

As illustrated in fig. 7 and 8, the transistor M _2R And M _3R Is provided with: cascaded at a voltage from ground GND and V _CC The current flow path (source-drain, in the example case of a MOSFET transistor) in the current flow line of the power supply line there through, and back to R ₁ And R ₂ A signal of a common node E of the feedback network is passed through a transistor M _2R And M _3R A cascaded current flow path center tap of (a); and their control terminals (gates, in the example case of MOSFET transistors) coupled to the transistor M ₃ (for transistor M) _3R ) And a transistor M ₂ (for transistor M) _2R ) Is applied to the control terminal (here, the gate).

In addition to the basic features also shared with the implementations of fig. 5 and 6, the implementations of fig. 7 and 8 thus share the following features between them, such as: current mirror circuit system M _2R 、M _3R Coupled to pass a further transistor M in the second gain stage A2 ₂ 、M ₃ Current flow path of (2), the current mirror circuit system M _2R 、M _3R Included in the power supply line V _CC And a current mirror flow line M between ground GND _2R 、M _3R Wherein the current mirror flows on the line M _2R 、M _3R Is configured to generate an indication at an output node V _OUT Is supplied to the load C _L A sense signal of the current of (a); and a coupling line 100 coupling a sensing node E in the current mirror flow line to a first transistor M in the first gainstage A1 _1A The control node of (2).

As is the case with the implementations of fig. 5 and 6, in the implementations of fig. 7 and 8, the sense signal at the sense node E is fed back to the first transistor M in the first gain stage A1 _1A The control node of (2).

It can be seen that the pole p of the transfer function of Gloop _d 、p ₁ And zero point z ₁ Given by the following equation:

wherein g is _m2 And g _m3 Is a transistor M ₂ And M ₃ Transconductance of (1).

Here again, as long as the output stage M is ₂ 、M ₃ Is biased to be larger than the associated current mirror stage M _2R 、M _3R At high (much) current, then approximately g can be maintained _m3R <<g _m3 For use.

Advantageously, M is adjusted _3R And I _BR Such that g _m3R R ₂ =1 leads to the following relationship:

this again represents an almost perfect cancellation between the output poles and zeros.

Here again, under the condition (g) _m3R *g _m2R )R ₂ Where =1 (always) is valid, it facilitates achieving the desired zero-pole cancellation regardless of process, voltage and temperature (PVT) conditions.

This result can be achieved by: (toIn a manner known per se) to design the transistor M in weak inversion (gate-to-source voltage below the threshold voltage) ₃ 、M ₂ 、M _3R And M _2R And is selected from the group consisting of ₂ Resistors R of the same type _bias ＝αR ₂ Inversely proportional bias current I of PTAT _B Type (proportional to absolute temperature) as reported in the case of fig. 5 and 6.

Advantageously, in both implementations of fig. 7 and 8, the second gain stage A2 is included in the supply line V _CC And a ground GND, wherein such output current flow line comprises a first further transistor M ₂ And a second further transistor M ₃ In the cascade current flow path of (2), wherein the output node C (or V) _OUT ) Is arranged at the first further transistor M ₂ And a second further transistor M ₃ The middle output current flow line.

In both implementations of fig. 7 and 8, a current mirror circuit system is provided, which is included in the power supply line V _CC And a current mirror flow line between ground GND. As illustrated, such a current mirror flow line includes a first current mirror transistor M _2R And a second current mirror transistor M _3R Wherein the sensing node E is arranged at the first current mirror transistor M _2R And a second current mirror transistor M _3R At the middle of this current mirror flow line.

In the implementations illustrated in fig. 7 and 8, class AB operation is facilitated by a coupling network of the second gain stage A2 to the first gain stage A1, which includes a capacitor pair C _C 2, which connects the output node C (or V) in the second gain stage A2 _OUT ) Coupled to a first node C ₁ And a second node C ₂ The first node C ₁ And a second node C ₂ Is located through the first coupling transistor M ₈ And a second coupling transistor M ₉ At opposite ends of the parallel connection of the current flow paths (source-drain, in the exemplary case of MOSFETs considered herein).

In the implementation illustrated in fig. 7 and 8, by means of a first coupling transistor M ₈ And a second coupling crystalBody tube M ₉ Is inserted in the power supply line V _CC And ground GND.

In such a current flow line, the first further transistor M in the output current flow line in the second gainstage A2 ₂ And a second further transistor M ₃ With respective coupling to node C ₁ And node C ₂ The control node of (2).

In addition, node C ₂ Is coupled to a coupling node D in the first gain stage A1, and a first coupling transistor M ₈ Having a control node (gate, in the exemplary case of the MOSFET considered herein) coupled to a supply line V _CC And a first drive current line (i.e. I) between ground GND _B 、M ₄ 、M ₆ ) Is first drive node (i.e., designated as D) ₁ Node(s) of (a).

Such a first drive current line comprises (as a transistor M connected by e.g. a diode) ₄ 、M ₆ Provided) a (first) series connection of diode junctions and a first drive current bias generator I _B The drive current bias generator I _B Is arranged at the power supply line V _CC And a first driving node D ₁ In the meantime.

As illustrated in fig. 7 and 8, the second coupling transistor M ₉ Having a control node (gate, in the exemplary case of the MOSFET considered herein) coupled to a supply line V _CC And a second drive node (i.e., node D) in a second drive current line between ground GND ₂ )。

As illustrated in fig. 7 and 8, such a second drive current line comprises (a diode-connected transistor M) ₅ 、M ₇ Provided) a (second) series connection of diode junctions and a second drive current bias generator I _B Wherein such a drive current bias generator is arranged at ground GND and a second drive node D ₂ In the meantime.

Due to the zero-pole double peak discussed above, it was found thatThe illustrated class AB amplifier circuit exhibits behavior exactly similar to that of a unipolar OTA in terms of stability, with the ability to be essentially stable, with capacitive loading C _L Is independent of the value of (very) small compensation capacitor C even in the presence of _C (e.g., 3 pF).

This may be applicable, for example, to closed loop gains ranging from 0dB to 20dB, where C _L Varying from 0.1pF to 10nf _C =3pF. In all cases considered, the phase margin was found to be consistently above 60 degrees, showing fully adequate stability.

With respect to closed-loop behavior, the closed-loop bandwidth is equal to the Gloop's original Unity Gain Bandwidth (UGB) and the zero frequency z, due to the introduction of the zero in the feedback path (rather than in the forward path) ₁ Lower value in between, while the in-band Gain, gain (Gain), in the case of the inverting configuration of fig. 7, may be expressed as:

or in the case of the non-inverting configuration of fig. 8 may be expressed as:

for gains of 0dB and 20dB and C _C At C of =3pF _L Fully adequate performance was tested at input and output voltages equal to 10pF, 100pF, 1nF and 10nF, respectively, with sine wave inputs of 100kHz, 10kHz, 1kHz and 100 Hz.

As with the implementations of fig. 5 and 6, the implementations of fig. 7 and 8 may facilitate the design of circuit 10 by: designing the first gain stage A1, the second gain stage A2 and the coupling network of the second gain stage A2 to the first gain stage A1, and the feedback line R ₁ 、R ₂ Which couples the output node C of the second gain stage A2 to the first transistor M in the first gain stage A1 _1A To obtain a control node having (at least) one output pole, i.e. a control nodep ₁ The loop transfer function Gloop of (a); and designs the current mirror circuit system with coupled lines 100 (i.e.: I in the implementations of fig. 5 and 6) _BR 、M _3R And M in the implementations of FIGS. 7 and 8 _2R 、M _3R ) To obtain a signal having an output zero point z ₁ The loop transfer function Gloop of (1), the output zero point z ₁ Since the sensing signal at the sensing node E is fed back to the first transistor M in the first gain stage A1 _1A Control node (e.g., gate) to cancel the output pole p ₁ 。

In all implementations of fig. 5, 6, 7 and 8, a feedback line is provided which includes an output node C (or V) coupled in the second gain stage A2 _OUT ) And a first transistor M in the first gain stage A1 _1A Of the control node (gate, in the exemplary case of the MOSFET considered herein) of (i.e. R) ₂ )。

The feedback line further comprises a second resistor (i.e. R) ₁ ) Coupled to a first transistor M in a first gain stage (A1) _1A Wherein the second resistor R ₁ Is configured to pass through the first transistor M _1A The control node of (a) applies: in the case of the "inverted" configuration of FIGS. 5 and 7-input signal V _IN Wherein the second transistor M _1B Has applied thereto a reference signal V _CM (ii) a Or in the case of the "non-inverting" configuration of FIGS. 6 and 8-the reference signal V _CM Wherein the second transistor M _1B Has applied thereto an input signal V _IN 。

The circuit as discussed herein is itself suitable for being included in a circuit comprising an output node C (or V) coupled to a second gain stage A2 _OUT ) Capacitive load C of _L In the apparatus of (1).

Devices comprising electrostatic and/or piezoelectric actuators, for example, with capacitance values related from a few pF to a few tens nF, may be examples of such devices.

Without prejudice to the underlying principles, the details and the embodiments may vary, even significantly, with respect to what has been described by way of example only, without departing from the scope of protection.

The claims are an integral part of the technical teaching of the examples provided herein.

The scope of protection is determined by the appended claims.

Claims

1. A circuit, comprising:

a first gain stage having a differential input transistor pair and having a bias current source, the differential input transistor pair comprising a first transistor having a control node and a current flow path, and a second transistor having a control node and a current flow path, the bias current source coupled to the current flow path of the first transistor and the current flow path of the second transistor, wherein the control node of the first transistor and the control node of the second transistor are configured to apply an input signal between the first transistor and the second transistor, and wherein the second transistor is located between the bias current source and a coupling node in the current flow path through the second transistor;

a second gain stage having an output node configured to couple to a load and apply an output voltage to the load, the output voltage being a function of the input signal applied between the control node of the first transistor and the control node of the second transistor, wherein the second gain stage includes a further current flow path through at least one further transistor;

a coupling network configured to: coupling the coupling node in the first gain stage to the output node in the second gain stage;

a feedback line coupling the output node in the second gain stage to the control node of the first transistor in the first gain stage;

a current mirror circuit system coupled to the further current flow path through the at least one further transistor in the second gain stage, the current mirror circuit system comprising a current mirror flow line between a power supply line and ground, wherein a sense node in the current mirror flow line is configured to generate a sense signal indicative of the current supplied to the load at the output node; and

a coupled line directly connecting the sense signal generated at the sense node in the current mirror flow line in the second gain stage, the sense signal fed back to the control node of the first transistor in the first gain stage.

2. The circuit according to claim 1, wherein the first and second switches are connected to the first and second terminals,

wherein the second gain stage comprises an output current flow line between the power supply line and ground, the output current flow line comprising a respective bias current source coupled to the further current flow path through the at least one further transistor, wherein the output node is arranged intermediate the respective bias current source and the at least one further transistor; and

wherein the current mirror circuitry comprises a current mirror flow line between the power supply line and ground, the current mirror flow line comprising a mirror bias current source coupled to a current mirror transistor, wherein the sense node is located intermediate the mirror bias current source and the current mirror transistor.

3. The circuit of claim 2, wherein the coupling network comprises a capacitor coupling the coupling node in the first gain stage to the output node in the second gain stage.

4. The circuit of claim 2, wherein the further transistor and the current mirror transistor are biased in weak inversion.

5. The circuit of claim 2, wherein the respective bias current source and the mirror bias current source are configured to provide a current Proportional To Absolute Temperature (PTAT).

6. The circuit according to claim 2, wherein the first and second switches are connected to the first and second switches,

wherein the feedback line comprises a feedback resistor coupling the output node in the second gain stage to the control node of the first transistor in the first gain stage; and

wherein the respective bias current source and the mirror bias current source are configured to provide a current inversely proportional to a resistance of the feedback resistor.

7. The circuit according to claim 1, wherein the first and second switches are connected to the first and second terminals,

wherein the at least one further transistor comprises a first further transistor and a second further transistor;

wherein the second gain stage comprises an output current flow line between the power supply line and ground, the output current flow line comprising a cascaded current flow path through the first further transistor and the second further transistor, wherein the output node is arranged at the output current flow line intermediate the first further transistor and the second further transistor; and

wherein the current mirror circuit system comprises a current mirror flow line between the power supply line and ground, the current mirror flow line comprising the cascaded current flow path through a first current mirror transistor and a second current mirror transistor, wherein the sense node is arranged at the current mirror flow line intermediate the first current mirror transistor and the second current mirror transistor.

8. The circuit of claim 7, wherein the coupling network comprises a pair of capacitors coupling the output node in the second gain stage to first and second nodes at opposite ends of a parallel connection of the current flow paths through first and second coupling transistors, the parallel connection of the current flow paths through first and second coupling transistors being interposed between a pair of bias current generators in a current flow line between the power supply line and ground.

9. The circuit according to claim 8, wherein the first and second switches are connected to a common power supply,

wherein the first further transistor and the second further transistor in the output current flow line in the second gain stage have control nodes coupled to the first node and the second node, respectively;

wherein the second node is coupled to the coupling node in the first gain stage;

wherein the first coupling transistor has a control node, the control node of the first coupling transistor being coupled to a first drive node in a first drive current line between the power supply line and ground, the first drive current line comprising a cascade arrangement of a first series connection of diode junctions and a first drive current bias generator, the drive current bias generator being arranged between the power supply line and the first drive node; and

wherein the second coupling transistor has a control node coupled to a second drive node in a second drive current line between the power supply line and ground, the second drive current line comprising a cascade arrangement of a second series connection of diode junctions and a second drive current bias generator, the drive current bias generator being arranged between ground and the second drive node.

10. The circuit of claim 9, wherein the bias current generator is configured to provide a current Proportional To Absolute Temperature (PTAT).

11. The circuit according to claim 9, wherein the first and second switches are connected to the first and second switches,

wherein the bias current generator is configured to provide a current inversely proportional to the resistance of the feedback resistor.

12. The circuit of claim 7, wherein the first further transistor, the second further transistor, the first current mirror transistor, and the second current mirror transistor are biased in weak inversion.

13. The circuit of claim 1, wherein the feedback line comprises:

a first resistor coupling the output node in the second gain stage and the control node of the first transistor in the first gain stage; and

a second resistor coupled to the control node of the first transistor in the first gain stage, wherein the second resistor is configured to apply one of:

inputting a signal, wherein the control node of the second transistor has applied a reference signal to the second transistor; or

A reference signal, wherein the control node of the second transistor has applied an input signal to the second transistor.

14. A system, comprising:

the circuit of claim 1; and

a capacitive load coupled to the output node in the second gain stage of the circuit.

15. A method of designing the circuit of claim 1, comprising:

designing the first gain stage, the second gain stage, the coupling network of the second gain stage to the first second gain stage, wherein the feedback line couples the output node in the second gain stage to the control node of the first transistor in the first gain stage to obtain a loop transfer function having an output pole; and

designing the current mirror circuit system, wherein the coupling line couples the sense node in the current mirror flow line in the second gain stage to the control node of the first transistor in the first gain stage to obtain a loop transfer function having an output zero that cancels the output pole in response to the sense signal at the sense node being fed back to the control node of the first transistor in the first gain stage.

16. A circuit, comprising:

a differential input stage comprising a pair of input transistors having control terminals configured to receive a first signal and a second signal, wherein a first input transistor of the pair of input transistors generates a differential signal;

an output stage comprising an output transistor having a control terminal configured to receive the differential signal and a drain terminal that generates an output signal;

a resistive feedback circuit coupled between the drain terminal of the output transistor and the control terminal of a second input transistor of the input transistor pair;

a sense transistor connected to the output transistor in a current mirror circuit, the sense transistor having a control terminal configured to receive the differential signal and a drain terminal that generates a sense signal indicative of a current delivered by the output signal; and

a feedback path configured to: applying the sense signal to the second input transistor of the input transistor pair.

17. The circuit of claim 16, further comprising a miller compensation capacitor coupled between the drain terminal and the control terminal of the output transistor.

18. The circuit of claim 16, wherein the sense transistor and the output transistor are biased in weak inversion.

19. The circuit of claim 16, further comprising an output current source coupled to the output transistor and a mirror current source coupled to the sense transistor, wherein the current supplied by the output current source and the mirror current source is proportional to an absolute temperature (PTAT) current.