JP5233994B2 - Mixer - Google Patents

Description

  The present invention relates to a mixer that lowers a high-frequency received signal to an intermediate frequency signal or raises an intermediate frequency signal to a high-frequency transmission signal in the wireless communication field.

  FIG. 10 is a diagram showing a configuration of a conventional mixer. As shown in FIG. 10, a mixer composed of bipolar transistors is conventionally known (see, for example, Patent Document 1). Bipolar transistors have high transconductance gm even at high frequencies. Therefore, even if the resistance value R1 of the resistor 1 is small, 1 / gm can be ignored. The gain of the mixer is determined by the resistance value R2 of the resistor 2 relative to the resistance value R1 of the resistor 1, that is, [R2 / R1].

  However, when a bipolar transistor is used, there is a drawback that it is higher than a mixer configured with a CMOS (Complementary Metal Oxide Semiconductor) structure. Further, since the mixer shown in FIG. 10 has one Io current source and two 2Io current sources, if the noise generated by the Io current source is In, a total of 5In noise is generated. Therefore, there is a drawback that noise is large.

  On the other hand, since the transconductance gm is low in the CMOS structure, a configuration in which the gain is determined by the resistance ratio as in the case of the bipolar transistor cannot be applied to the high frequency circuit. Therefore, the CMOS structure has a configuration in which the gain is determined by the transconductance gm and the resistance value R2 of the resistor 2. In this case, in order to make the gain constant, it is necessary to keep the transconductance gm constant. However, since the variation in the transconductance gm of the CMOS process is so large that it cannot be ignored, the current sources 3 and 4 in FIG. (For example, refer to Patent Document 2).

US Pat. No. 5,920,810 (FIG. 2) JP 10-49244 A (paragraph numbers [0019] to [0021])

  However, in a configuration using a current source that compensates for the variation in transconductance gm, the variation in transconductance gm is about 1.5 times. To compensate for this, the current value needs to be changed by about 2.3 times. . As a result, the linear range of the mixer is narrowed by the amount deviated from the optimum current value. This is not preferable in view of the fact that one of the characteristics required for the mixer has a wide linearity.

  The present invention has been made in view of the above, and an object of the present invention is to provide a CMOS-structured mixer having a wide linearity.

  In order to solve the above-described problems and achieve the object, the present invention includes a mixer circuit and a linear range compensation circuit that compensates for a linear range of output characteristics of the mixer circuit. The mixer circuit has a load resistor connected between the output terminal and the power supply line. The linear range compensation circuit controls the amount of current flowing through the load resistance in accordance with the midpoint voltage of the output voltage of the mixer circuit. Specifically, the linear range compensation circuit increases the amount of current flowing through the load resistance of the mixer circuit when the midpoint voltage of the output voltage of the mixer circuit is higher than the desired voltage, and the amount of voltage drop at the load resistance. Is controlled to be large. Further, the linear range compensation circuit reduces the amount of current flowing through the load resistance of the mixer circuit when the midpoint voltage of the output voltage of the mixer circuit is lower than the desired voltage, and the amount of voltage drop at the load resistance is reduced. To control. The output signal of the linear range compensation circuit is fed back to the opposite side of the output terminal with respect to the input terminal of the local oscillation signal. Further, the mixer circuit is composed of a CMOS circuit.

  According to the present invention, when the midpoint voltage of the output voltage of the mixer circuit is higher than the midpoint voltage when a wide linear range is obtained, the amount of voltage drop at the load resistance of the mixer circuit becomes large, and the linear range Is controlled so that the midpoint voltage of the output voltage of the mixer circuit is controlled. In addition, when the midpoint voltage of the output voltage of the mixer circuit is lower than the midpoint voltage when a wide linear range is obtained, the amount of voltage drop at the load resistance of the mixer circuit becomes small and the linear range becomes wide. In addition, the midpoint voltage of the output voltage of the mixer circuit is controlled.

  The mixer according to the present invention has a CMOS structure, is inexpensive, and has a wide linearity.

FIG. 1 is a diagram illustrating the configuration of the mixer according to the first embodiment of the present invention. FIG. 2 is a diagram illustrating simulation results of the output characteristics of the mixer according to the first embodiment. FIG. 3 is a diagram illustrating simulation results of the output characteristics of the mixer according to the first embodiment. FIG. 4 is a diagram illustrating simulation results of the output characteristics of the mixer according to the first embodiment. FIG. 5 is a diagram illustrating simulation results of output characteristics of the mixer of the comparative example. FIG. 6 is a diagram illustrating a simulation result of output characteristics of the mixer of the comparative example. FIG. 7 is a diagram illustrating the configuration of the mixer according to the second embodiment of the present invention. FIG. 8 is a diagram illustrating the configuration of the mixer according to the third embodiment of the present invention. FIG. 9 is a diagram showing a configuration of a fourth embodiment in which the present invention is applied to a buffer. FIG. 10 is a diagram showing a configuration of a conventional mixer.

Explanation of symbols

10, 50, 60 Mixer 11, 13, 14 Mixer circuit 12, 15 Linear range compensation circuit 21 Current source, first current source 22, 23 First differential pair 24, 25 First current mirror circuit 26, 27 Second current mirror circuit 28, 29 Second differential pair 30, 31 Third differential pair 32, 33 Load resistance 34 Second current source 35 Third current source

  Hereinafter, embodiments of a mixer according to the present invention will be described in detail with reference to the drawings. In the following description, a p-channel MOS (Metal Oxide Semiconductor) transistor and an n-channel MOS transistor are referred to as a PMOS transistor and an NMOS transistor, respectively. Note that the present invention is not limited to the embodiments.

  FIG. 1 is a diagram illustrating the configuration of the mixer according to the first embodiment of the present invention. As shown in FIG. 1, the mixer 10 includes a CMOS structure mixer circuit 11 and a linear range compensation circuit 12 that compensates for the linear range of the output characteristics of the mixer circuit 11.

  The mixer circuit 11 includes a first PMOS transistor 21 that is equivalently a current source of Io, a second PMOS transistor 22 and a third PMOS transistor 23 that constitute a first differential pair, and a first current. A first NMOS transistor 24 and a second NMOS transistor 25 constituting a mirror circuit, and a third NMOS transistor 26 and a fourth NMOS transistor 27 constituting a second current mirror circuit are provided. In addition, the mixer circuit 11 includes a fifth NMOS transistor 28 and a sixth NMOS transistor 29 that constitute the second differential pair, and a seventh NMOS transistor 30 and an eighth NMOS that constitute the third differential pair. An NMOS transistor 31, a first load resistor 32, and a second load resistor 33 are provided.

  The source terminal of the first PMOS transistor 21 is connected to a power supply line to which the power supply potential VDD is applied. A bias (bias 1) is applied to the gate terminal of the first PMOS transistor 21. The value of the bias (bias1) is appropriately selected so that the first PMOS transistor 21 passes a desired current. The drain terminal of the first PMOS transistor 21 is connected to the source terminals of the second PMOS transistor 22 and the third PMOS transistor 23.

  The input signal IN is input to the gate terminal of the second PMOS transistor 22. The drain terminal of the second PMOS transistor 22 is connected to the drain terminal of the first NMOS transistor 24. The gate terminal of the first NMOS transistor 24 is connected to its own drain terminal. The source terminal of the first NMOS transistor 24 is connected to a ground line to which the ground potential VSS is applied.

  An inverted signal (hereinafter referred to as an input inverted signal) INX of the input signal IN is input to the gate terminal of the third PMOS transistor 23. The drain terminal of the third PMOS transistor 23 is connected to the drain terminal of the third NMOS transistor 26. The gate terminal of the third NMOS transistor 26 is connected to its own drain terminal. The source terminal of the third NMOS transistor 26 is connected to the ground line.

  One end of each of the first load resistor 32 and the second load resistor 33 is connected to a power supply line. The other end of the first load resistor 32 is connected to each drain terminal of the fifth NMOS transistor 28 and the seventh NMOS transistor 30. The other end of the second load resistor 33 is connected to each drain terminal of the eighth NMOS transistor 31 and the sixth NMOS transistor 29.

  The local oscillation signal Lo is input to the gate terminals of the fifth NMOS transistor 28 and the eighth NMOS transistor 31. An inverted signal of the local oscillation signal Lo (hereinafter referred to as local oscillation inversion signal) LoX is input to the gate terminals of the sixth NMOS transistor 29 and the seventh NMOS transistor 30. An output signal OUT is output from the drain terminal of the fifth NMOS transistor 28. From the drain terminal of the eighth NMOS transistor 31, an inverted signal (hereinafter referred to as an output inverted signal) OUTX of the output signal OUT is output.

  The source terminals of the fifth NMOS transistor 28 and the sixth NMOS transistor 29 are connected to the drain terminal of the second NMOS transistor 25. The gate terminal of the second NMOS transistor 25 is connected to the gate terminal of the first NMOS transistor 24. The source terminal of the second NMOS transistor 25 is connected to the ground line.

  The source terminals of the eighth NMOS transistor 31 and the seventh NMOS transistor 30 are connected to the drain terminal of the fourth NMOS transistor 27. The gate terminal of the fourth NMOS transistor 27 is connected to the gate terminal of the third NMOS transistor 26. The source terminal of the fourth NMOS transistor 27 is connected to the ground line.

  The linear range compensation circuit 12 includes a fourth PMOS transistor 41 and a fifth PMOS transistor 42 serving as a current source, a third load resistor 43, a fourth load resistor 44, and an operational amplifier 45. One end of the third load resistor 43 is connected to the signal line of the output signal OUT. One end of the fourth load resistor 44 is connected to the signal line of the output inversion signal OUTX. The other ends of the third load resistor 43 and the fourth load resistor 44 are commonly connected to the non-inverting input terminal of the operational amplifier 45. A reference voltage Vref is applied to the inverting input terminal of the operational amplifier 45.

  The operational amplifier 45 outputs a voltage corresponding to the difference between the midpoint voltage of the output signal OUT and the output inverted signal OUTX and the reference voltage Vref from its output terminal. The reference voltage Vref is appropriately selected so that the midpoint voltage of the output signal OUT and the output inverted signal OUTX becomes a desired value. The output terminal of the operational amplifier 45 is connected to the gate terminals of the fourth PMOS transistor 41 and the fifth PMOS transistor 42. The source terminals of the fourth PMOS transistor 41 and the fifth PMOS transistor 42 are connected to the power supply line. The drain terminal of the fourth PMOS transistor 41 is connected to the drain terminal of the second NMOS transistor 25.

  The drain terminal of the fifth PMOS transistor 42 is connected to the drain terminal of the fourth NMOS transistor 27. Therefore, each of the fourth PMOS transistor 41 and the fifth PMOS transistor 42 uses the output voltage of the operational amplifier 45 as a bias and supplies a current corresponding to the voltage to the second NMOS transistor 25 and the fourth NMOS transistor 27. It flows as part of the flowing current.

  Next, the operation of the circuit shown in FIG. 1 will be described. It is assumed that the amount of current flowing through the first PMOS transistor 21 is 2Io, and half of the current flows through the first NMOS transistor 24 and the third NMOS transistor 26, respectively. Since the first NMOS transistor 24 and the second NMOS transistor 25, and the third NMOS transistor 26 and the fourth NMOS transistor 27 constitute a current mirror circuit, respectively, the second NMOS transistor 25 and the fourth NMOS transistor 25 The current Io also flows through the NMOS transistor 27.

When the amount of current flowing through the fourth PMOS transistor 41 and the fifth PMOS transistor 42 by the output voltage of the operational amplifier 45 is Ib, the amount of current flowing through the first load resistor 32 and the amount of current flowing through the second load resistor 33 are: , [Io-Ib]. When each resistance value of the first load resistor 32 and the second load resistor 33 is R, the voltage drop amount Vb due to R is expressed by the following equation (1). Vb is the difference between the power supply potential VDD and the midpoint voltage of the output signal OUT and the output inversion signal OUTX.
Vb = R · (Io−Ib) (1)

When the transconductance gm of the second PMOS transistor 22 and the third PMOS transistor 23 constituting the differential pair is high, when Ib is zero and Io is the minimum value Imin, the output signal OUT and the output inverted signal Design so that the midpoint voltage of OUTX is optimal. Since [Io = Imin] and [Ib = 0], Vb is expressed by the following equation (2) from the above equation (1). Further, Imin is expressed by the following equation (3). For example, if Vb is 1 V and R is 1 kΩ, Imin is 1 mA.
Vb = R · (Imin−0) = R · Imin (2)
Imin = Vb / R (3)

In the mixer designed as described above, when the transconductance gm is typical and Io is [1.4 × Imin], the midpoint voltage of the output signal OUT and the output inverted signal OUTX is optimized. Ib is adjusted as follows. Since [Io = 1.4 × Imin], Vb is expressed by the following equation (4) from the above equation (1). From the expressions (3) and (4), Ib is expressed by the following expression (5). Therefore, Vb is expressed by the following equation (6).
Vb = R · (1.4 × Imin−Ib) (4)
Ib = 1.4 × Imin−Vb / R = 1.4 × Imin−Imin = 0.4 × Imin
... (5)
Vb = R · (1.4 × Imin−0.4 × Imin) = R · Imin (6)

Further, when the transconductance gm is low and Io is [2 × Imin], Ib is adjusted so that the midpoint voltage of the output signal OUT and the output inverted signal OUTX is optimized. Since [Io = 2 × Imin], Vb is expressed by the following equation (7) from the above equation (1). From the expressions (3) and (7), Ib is expressed by the following expression (8). Therefore, Vb is expressed by the following equation (9).
Vb = R · (2 × Imin−Ib) (7)
Ib = 2 × Imin−Vb / R = 2 × Imin−Imin = Imin (8)
Vb = R · (2 × Imin−Imin) = R · Imin (9)

  Thus, even if the transconductance gm varies, the value of the current flowing through the linear range compensation circuit 12 so that the current of [Io−Ib = Imin] flows through the first load resistor 32 and the second load resistor 33. Ib is adjusted. Thereby, Vb is always kept at a constant value of [R · Imin]. That is, the midpoint voltage of the output signal OUT and the output inverted signal OUTX is always kept at a constant value.

  2 to 4, when the power supply voltage is 3 V, Vb is 1 V, and the reference voltage Vref is 2 V, when Io is optimal (FIG. 2), Io is small for compensating the transconductance gm. The simulation result of the output characteristic in the case (FIG. 3) and the case where Io is large for the compensation of the transconductance gm (FIG. 3) is shown. As shown in these figures, in any case, the midpoint voltage of the output signal OUT and the output inversion signal OUTX is adjusted to 2 V by the linear range compensation circuit 12, so that a wide linear range of 1.8 V is obtained. It turns out that it is obtained.

  For comparison, FIGS. 5 and 6 show the results of a similar simulation performed on a mixer having a configuration in which the linear range compensation circuit 12 is removed from the circuit shown in FIG. The parameters that determine the electrical characteristics of the mixer, such as the size of the transistor and the resistance value of the load resistance, are the same as in the simulation of the mixer shown in FIG. The simulation result when Io is optimal is the same as in FIG. 2, and a linear range of 1.8 V is obtained.

  On the other hand, as shown in FIG. 5, when Io is small to compensate for transconductance gm, the midpoint voltage of output signal OUT and output inversion signal OUTX is 2.3 V, and the linear range is 1. It becomes as narrow as 1V. Further, as shown in FIG. 6, when Io is large to compensate for the transconductance gm, the midpoint voltage of the output signal OUT and the output inversion signal OUTX is 1.5V, and the linear range is 1.0V. It gets narrower.

  FIG. 7 is a diagram illustrating the configuration of the mixer according to the second embodiment of the present invention. As shown in FIG. 7, the second embodiment is different from the first embodiment in the configuration of the mixer circuit 13 of the mixer 50. Hereinafter, only the configuration different from that of the first embodiment will be described, and the same configuration as that of the first embodiment will be denoted by the same reference numerals as those of the first embodiment, and redundant description will be omitted.

  The mixer circuit 13 is not provided with the first current mirror circuit (first NMOS transistor and second NMOS transistor) and the second current mirror circuit (third NMOS transistor and fourth NMOS transistor). . Instead, the mixer circuit 13 includes a ninth NMOS transistor 34 and a tenth NMOS transistor 35 as current sources.

  In the ninth NMOS transistor 34, its drain terminal and source terminal are connected to the drain terminal of the second PMOS transistor 22 and the ground line, respectively. A bias (bias2) is applied to the gate terminal of the ninth NMOS transistor. The drain terminal and the source terminal of the tenth NMOS transistor 35 are connected to the drain terminal and the ground line of the third PMOS transistor 23, respectively. A bias (bias2) is applied to the gate terminal of the ninth NMOS transistor. The value of the bias (bias2) is appropriately selected so that the ninth NMOS transistor 34 and the tenth NMOS transistor 35 pass a desired current.

  Further, the source terminals of the fifth NMOS transistor 28 and the sixth NMOS transistor 29 constituting the second differential pair are connected to the drain terminal of the ninth NMOS transistor 34. The source terminals of the seventh NMOS transistor 30 and the eighth NMOS transistor 31 constituting the third differential pair are connected to the drain terminal of the tenth NMOS transistor 35. Further, the drain terminal of the fourth PMOS transistor 41 of the linear range compensation circuit 12 is connected to the drain terminal of the ninth NMOS transistor 34. The drain terminal of the fifth PMOS transistor 42 of the linear range compensation circuit 12 is connected to the drain terminal of the tenth NMOS transistor 35.

  Next, the operation of the circuit shown in FIG. 7 will be described. It is assumed that the amount of current flowing through the first PMOS transistor 21 is 2Io, and half of the current flows through the ninth NMOS transistor 34 and the tenth NMOS transistor 35, respectively. Further, it is assumed that the ninth NMOS transistor 34 and the tenth NMOS transistor 35 pass a current of 2 Io. In this case, the current Io flows from the second differential pair (the fifth NMOS transistor 28 and the sixth NMOS transistor 29) and the fourth PMOS transistor 41 to the drain terminal of the ninth NMOS transistor 34. Similarly, the current Io flows from the third differential pair (the seventh NMOS transistor 30 and the eighth NMOS transistor 31) and the fifth PMOS transistor 42 to the drain terminal of the tenth NMOS transistor 35.

  Assuming that the current flowing through the fourth PMOS transistor 41 and the fifth PMOS transistor 42 is Ib, the values of the current flowing through the first load resistor 32 and the current flowing through the second load resistor 33 are the same as those in the first embodiment. Similarly, [Io-Ib] is obtained. Thus, when each resistance value of the first load resistor 32 and the second load resistor 33 is R, the above equation (1) is obtained. Accordingly, in the same manner as in the first embodiment, in the second embodiment, when the transconductance gm is high, the above formulas (2) to (9) are established for the typical case and the low case, so that the transconductance gm is Even if there is a variation, the midpoint voltage of the output signal OUT and the output inverted signal OUTX is always kept at a constant value.

  FIG. 8 is a diagram illustrating the configuration of the mixer according to the third embodiment of the present invention. As shown in FIG. 8, the third embodiment is different from the first embodiment in the configuration of the mixer circuit 14 and the linear range compensation circuit 15 of the mixer 60. Hereinafter, only the configuration different from that of the first embodiment will be described, and the same configuration as that of the first embodiment will be denoted by the same reference numerals as those of the first embodiment, and redundant description will be omitted.

  In the mixer circuit 14, an eleventh NMOS transistor 36 and a twelfth NMOS transistor 37 are added. The drain terminal of the eleventh NMOS transistor 36 is connected to the drain terminal of the first NMOS transistor 24 constituting the first current mirror circuit. The drain terminal of the twelfth NMOS transistor 37 is connected to the drain terminal of the third NMOS transistor 26 constituting the second current mirror circuit. The gate terminals of the eleventh NMOS transistor 36 and the twelfth NMOS transistor 37 are connected to the output terminal of the operational amplifier 45 of the linear range compensation circuit 15.

  Accordingly, each of the eleventh NMOS transistor 36 and the twelfth NMOS transistor 37 uses the output voltage of the operational amplifier 45 as a bias, and passes a current corresponding to the voltage. The source terminals of the eleventh NMOS transistor 36 and the twelfth NMOS transistor 37 are connected to the ground line. In the linear range compensation circuit 15, the reference voltage Vref is applied to the non-inverting input terminal of the operational amplifier 45, and the other end of the third load resistor 43 and the other end of the fourth load resistor 44 are commonly connected to the inverting input terminal. ing. The linear range compensation circuit 15 is configured without the fourth PMOS transistor and the fifth PMOS transistor.

  Next, the operation of the circuit shown in FIG. 8 will be described. It is assumed that the amount of current flowing through the first PMOS transistor 21 is 2Io, and half of the current flows toward the first NMOS transistor 24 and the third NMOS transistor 26, respectively. Further, the amount of current flowing through the eleventh NMOS transistor 36 and the twelfth NMOS transistor 37 by the output voltage of the operational amplifier 45 is defined as Ib.

  In this case, of the current Io flowing from the drain terminals of the second PMOS transistor 22 and the third PMOS transistor 23, Ib flows to the eleventh NMOS transistor 36 and the twelfth NMOS transistor 37. That is, the current of [Io−Ib] flows through the first NMOS transistor 24 and the third NMOS transistor 26, and the second NMOS transistor 25 and the fourth NMOS constituting the current mirror circuit with them. The current flowing through the transistor 27 is also [Io−Ib].

  Therefore, each value of the current flowing through the first load resistor 32 and the current flowing through the second load resistor 33 is [Io−Ib] as in the first embodiment. Thus, when each resistance value of the first load resistor 32 and the second load resistor 33 is R, the above equation (1) is obtained. Accordingly, in the same manner as in the first embodiment, in the third embodiment, when the transconductance gm is high, the cases where the transconductance gm is typical, and the case where the transconductance gm is low, the expressions (2) to (9) hold. Even if there is a variation, the midpoint voltage of the output signal OUT and the output inverted signal OUTX is always kept at a constant value.

  FIG. 9 is a diagram showing a configuration of a fourth embodiment in which the linear range compensation circuit according to the present invention is applied to a buffer. As shown in FIG. 9, the buffer 70 includes a buffer circuit 16 and a linear range compensation circuit 12. The configuration of the buffer circuit 16 is the same as that of the mixer circuit 11 of the first embodiment except for a part. The linear range compensation circuit 12 has the same configuration as that of the first embodiment. Hereinafter, only the configuration different from that of the first embodiment will be described, and the same configuration as that of the first embodiment will be denoted by the same reference numerals as those of the first embodiment, and redundant description will be omitted.

  The buffer circuit 16 is not provided with the second differential pair (fifth NMOS transistor and sixth NMOS transistor) and the third differential pair (seventh NMOS transistor and eighth NMOS transistor). . Instead, the buffer circuit 16 has a thirteenth NMOS transistor 38 and a fourteenth NMOS transistor 39.

  In the thirteenth NMOS transistor 38, the drain terminal and the source terminal are connected to the other end of the first load resistor 32 and the drain terminal of the second NMOS transistor 25, respectively. An output signal OUT is output from the drain terminal of the thirteenth NMOS transistor 38. A bias (bias 2) is applied to the gate terminal of the thirteenth NMOS transistor 38.

  In the fourteenth NMOS transistor 39, the drain terminal and the source terminal are connected to the other end of the second load resistor 33 and the drain terminal of the fourth NMOS transistor 27, respectively. An output inversion signal OUTX is output from the drain terminal of the fourteenth NMOS transistor 39. A bias (bias 2) is applied to the gate terminal of the fourteenth NMOS transistor 39. The value of the bias (bias2) is appropriately selected so that the thirteenth NMOS transistor 38 and the fourteenth NMOS transistor 39 pass a desired current. Since the operation of the circuit shown in FIG. 9 is the same as that of the first embodiment, the description thereof is omitted.

  According to the first to third embodiments, when the midpoint voltage of the output voltages of the mixer circuits 11, 13, and 14 is higher than the midpoint voltage when a wide linear range is obtained, the voltage at the load resistors 32 and 33 The midpoint voltage of the output voltages of the mixer circuits 11, 13, and 14 is controlled so that the amount of drop is large and the linear range is widened. Further, when the midpoint voltage of the output voltages of the mixer circuits 11, 13, and 14 is lower than the midpoint voltage when a wide linear range is obtained, the amount of voltage drop at the load resistors 32 and 33 becomes small and linear. The midpoint voltage of the output voltages of the mixer circuits 11, 13, and 14 is controlled so that the range becomes wider. Therefore, it is possible to obtain the mixers 10, 50, 60 having a CMOS structure, being inexpensive and having a wide linearity. The same effect can be obtained in the buffer 70 of the fourth embodiment.

  For example, in a conventional mixer that can ensure a linear range of 1.8V, if the transconductance gm varies ± 30%, the linear range deteriorates to about 1V due to variations in current for compensating the transconductance gm. End up. On the other hand, according to the embodiment, since there is no deterioration, it is possible to secure a linear range about 1.8 times that of the conventional case. Considering temperature fluctuations, the variation in transconductance gm reaches about ± 50%, so the effect is further increased.

  Further, according to the first embodiment, since there are equivalently two current sources of Io and one diode-connected transistor corresponding to the current source of Io, the noise generation amount can be suppressed to 3In in total. An effect is obtained. Further, according to the second embodiment, the effect that two transistors are less than that of the first embodiment is obtained. Furthermore, according to the third embodiment, an effect that current consumption is smaller than that of the first embodiment can be obtained.

  As described above, the mixer according to the present invention is useful for a transmission device or a reception device used in wireless communication such as an OFDM (Orthogonal Frequency Multiple Access) method, and is particularly suitable for a mobile phone.

Claims (5)

A mixer circuit in which a load resistor is connected between the output terminal and the power supply line;
When the midpoint voltage of the output voltage of the mixer circuit is higher than a desired voltage, the amount of current flowing through the load resistor is increased, and when the midpoint voltage of the output voltage of the mixer circuit is lower than the desired voltage, the load A linear range compensation circuit that controls to reduce the amount of current flowing through the resistor, and feeds back the output signal to the opposite side of the output terminal with respect to the input terminal of the local oscillation signal,
The linear range compensation circuit, such that the current flowing through the load resistor is minimized, mixer characterized by having a current source for adjusting the current flowing through the load resistor. The mixer circuit includes a current source, a first differential pair connected to the current source and receiving an input signal from the outside, and an input end connected to a first output end of the first differential pair. Connected to the output terminal of the first current mirror circuit, the second current mirror circuit whose input terminal is connected to the second output terminal of the first differential pair, and the output terminal of the first current mirror circuit A second differential pair to which a local oscillation signal is input from the outside, and a third differential pair connected to the output terminal of the second current mirror circuit and to which a local oscillation signal is input from the outside, Have
The first output terminal of the mixer circuit includes one end of a first load resistor, the first output terminal of the second differential pair, the second output terminal of the third differential pair, and the linear range. The first input of the compensation circuit is connected;
The second output terminal of the mixer circuit includes one end of a second load resistor, the second output terminal of the second differential pair, the first output terminal of the third differential pair, and the linear range. The second input of the compensation circuit is connected;
A first output terminal of the linear range compensation circuit is connected to an output terminal of the first current mirror circuit;
A second output terminal of the linear range compensation circuit is connected to an output terminal of the second current mirror circuit;
The linear range compensation circuit includes a first output terminal of the first current mirror circuit and a second output terminal so that a midpoint voltage of the first output terminal and the second output terminal of the mixer circuit becomes a desired voltage. The mixer according to claim 1, wherein the amount of current flowing through the output terminal of the current mirror circuit is controlled. The mixer circuit includes a first current source, a first differential pair connected to the first current source and receiving an input signal from the outside, and a first output of the first differential pair. A second current source having an input terminal connected to the end, a third current source having an input terminal connected to the second output terminal of the first differential pair, and an input of the second current source A second differential pair connected to the terminal and receiving a local oscillation signal from the outside; and a third differential pair connected to the input terminal of the third current source and receiving a local oscillation signal from the outside. And having
The first output terminal of the mixer circuit includes one end of a first load resistor, the first output terminal of the second differential pair, the second output terminal of the third differential pair, and the linear range. The first input of the compensation circuit is connected;
The second output terminal of the mixer circuit includes one end of a second load resistor , the second output terminal of the second differential pair, the first output terminal of the third differential pair, and the linear range. The second input of the compensation circuit is connected;
A first output terminal of the linear range compensation circuit is connected to an input terminal of the second current source;
A second output terminal of the linear range compensation circuit is connected to an input terminal of the third current source;
The linear range compensation circuit includes the input end of the second current source and the third end so that the midpoint voltage of the voltage of the first output end and the second output end of the mixer circuit becomes a desired voltage. The mixer according to claim 1, wherein the amount of current flowing through the input terminal of the current source is controlled. The mixer circuit includes a current source, a first differential pair connected to the current source and receiving an input signal from the outside, and an input end connected to a first output end of the first differential pair. Connected to the output terminal of the first current mirror circuit, the second current mirror circuit whose input terminal is connected to the second output terminal of the first differential pair, and the output terminal of the first current mirror circuit A second differential pair to which a local oscillation signal is input from the outside, and a third differential pair connected to the output terminal of the second current mirror circuit and to which a local oscillation signal is input from the outside, Have
The first output terminal of the mixer circuit includes one end of a first load resistor, the first output terminal of the second differential pair, the second output terminal of the third differential pair, and the linear range. The first input of the compensation circuit is connected;
The second output terminal of the mixer circuit includes one end of a second load resistor , the second output terminal of the second differential pair, the first output terminal of the third differential pair, and the linear range. The second input of the compensation circuit is connected;
An output terminal of the linear range compensation circuit is connected to an input terminal of the first current mirror circuit;
An output terminal of the linear range compensation circuit is connected to an input terminal of the second current mirror circuit;
The linear range compensation circuit includes: an input terminal of the first current mirror circuit and the first output terminal so that a midpoint voltage of the voltage of the first output terminal and the second output terminal of the mixer circuit becomes a desired voltage. 2. The mixer according to claim 1, wherein the amount of current flowing through an input terminal of the two current mirror circuits is controlled.   The mixer according to claim 1, wherein the mixer circuit is constituted by a CMOS circuit.

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