JPS63185208A - Differential amplifying circuit - Google Patents

Differential amplifying circuit

Info

Publication number
JPS63185208A
JPS63185208A JP62019091A JP1909187A JPS63185208A JP S63185208 A JPS63185208 A JP S63185208A JP 62019091 A JP62019091 A JP 62019091A JP 1909187 A JP1909187 A JP 1909187A JP S63185208 A JPS63185208 A JP S63185208A
Authority
JP
Japan
Prior art keywords
voltage
constant
circuit
source
transistor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62019091A
Other languages
Japanese (ja)
Inventor
Yutaka Sada
佐田 裕
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP62019091A priority Critical patent/JPS63185208A/en
Publication of JPS63185208A publication Critical patent/JPS63185208A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To suppress the variance of gain caused by the variance of a value of resistance of an integrated circuit, by providing an error amplifying for comparing the same phase output voltage and a reference voltage, detecting an error from a prescribed value of a current quantity of a constantcurrent source, and executing a negative feedback control so that said current quantity becomes the prescribed value. CONSTITUTION:The same phase output voltage detecting resistances 14, 15 which have eliminated a constant-voltage source in a conventional circuit, and in which a constant-voltage source 16 and one end are connected to an output terminal 4 and 5, respectively, and the other end is connected in common at a point A, and an error amplifier 17 in which an inversion input is connected to the constant-voltage source 16, and a non-inversion input is connected to the point A, and an output is connected to a base of a transistor 8 are added. In this case, a resistance value RA of the resistances 14, 15 is higher enough than a resistance value RL of resistances 11, 12. A voltage of the connecting point A is a voltage which has divided a voltage of output signals whose phases are opposite to each other, into two, and becomes equal to the same phase output voltage of a differential amplifying circuit. The potential of the point A is compared with a reference voltage VR, and by an output of the error amplifier 17 corresponding to its difference, the base of the transistor 8 for constituting a constant- current source is biased. By this operation, with regard to the constant-current quantity of the constant-current source, a negative feedback control is executed as a circuit.

Description

【発明の詳細な説明】 〔産業上の利用分野) 本発明は、集積回路化された差動増幅回路に関し、特に
オープンコレクタ出ノ〕の差動増幅回路に関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an integrated circuit differential amplifier circuit, and particularly to an open collector output differential amplifier circuit.

(従来の技術〕 従来、この種の差動増幅回路は、例えば、第4図に示す
ように、差動増幅回路の入力端子1と2と、差動増幅回
路の出力段を除いた前段回路3と、ベースが前段回路3
の一方の出力に接続され、コレクタが差動増幅回路の出
力端子4に接続されたトランジスタ6と、ベースが前段
回路3の他方の出力に接続され、コレクタが差動増幅回
路の出力端子5に接続されたトランジスタ7と、コレク
タが差動対をなす2つのトランジスタ6.7の共通接続
端(エミッタ)に接続されたトランジスタ8と、トラン
ジスタ8のベースをバイアスする定電圧源10と、一端
がトランジスタ8のエミッタに接続され他端が接地され
た抵抗9と、定電圧源13と、定電圧源13と出力端子
4,5との間に接続された負荷抵抗1コ、12とからな
っている。
(Prior Art) Conventionally, this type of differential amplifier circuit, for example, as shown in FIG. 3, and the base is the front stage circuit 3
A transistor 6 whose collector is connected to one output of the differential amplifier circuit and whose collector is connected to the output terminal 4 of the differential amplifier circuit, and whose base is connected to the other output of the pre-stage circuit 3 and whose collector is connected to the output terminal 5 of the differential amplifier circuit. The connected transistor 7, the transistor 8 whose collectors are connected to the common connection end (emitter) of the two transistors 6 and 7 forming a differential pair, and the constant voltage source 10 that biases the base of the transistor 8, It consists of a resistor 9 connected to the emitter of the transistor 8 and whose other end is grounded, a constant voltage source 13, and load resistors 1 and 12 connected between the constant voltage source 13 and the output terminals 4 and 5. There is.

(発明が解決しj:うとする問題点) この第4図に示される差動増幅回路の差動利得Gvは、
負荷抵抗11.12の値をR5、抵抗9の抵抗値をRE
1定電圧源10の電圧をvl、トランジスタ8のベース
・エミッタ間順方向電圧をv6.とし、電子負荷をq1
ボルツマン定数をk、絶対温度を王とすると、 q  Vl−VBE となり、抵抗9の抵抗値R1に逆比例する。集積回路の
抵抗の絶対値は代表的な伯として±20%程庶変動する
ので、本回路を集積回路化すると差動利得Gvは一17
%から+25%ばらつくことになる。このため利得Gv
の規格をより厳しくする必要がある用途の場合、従来の
回路では製造歩留が低くなる恐れがある。これを防ぐに
は、ツェナーIJ’ツブや抵抗のトリミング等を使うこ
とも考えられるが、余分の工程が必要になり、]ス1〜
アップになる。
(Problem to be solved by the invention) The differential gain Gv of the differential amplifier circuit shown in FIG.
The value of load resistor 11.12 is R5, and the resistance value of resistor 9 is RE
1, the voltage of the constant voltage source 10 is vl, and the forward voltage between the base and emitter of the transistor 8 is v6. and the electronic load is q1
If the Boltzmann constant is k and the absolute temperature is the king, then q Vl-VBE is obtained, which is inversely proportional to the resistance value R1 of the resistor 9. The absolute value of the resistance of an integrated circuit typically fluctuates by about ±20%, so if this circuit is integrated, the differential gain Gv will be -17.
% to +25%. Therefore, the gain Gv
For applications that require more stringent standards, conventional circuits may suffer from low manufacturing yields. To prevent this, it is possible to use the Zener IJ' knob or trimming the resistor, but this requires an extra process, and
It's going to be up.

上)ホした従来の差動増幅回路は、定電流源の電流量が
、半導体集積回路製造の際の抵抗の値のばらつきの影響
を直接に受tノで変動しやすく、その結果、利得のばら
つきが生じや1いという欠点がある。
In the conventional differential amplifier circuit mentioned above, the amount of current of the constant current source is directly affected by variations in the value of the resistance during semiconductor integrated circuit manufacturing, and as a result, the gain changes easily. It has the disadvantage that variations occur.

〔問題点を解決するための手段〕[Means for solving problems]

本発明の差動増幅回路は、同相出力電圧と基準電圧とを
比較して、前記定電流源の電流量の所定値からの誤差を
検出し、該電流量が所定値になるように負帰還制御する
誤差増幅器を有している。
The differential amplifier circuit of the present invention compares the common-mode output voltage with a reference voltage, detects an error in the current amount of the constant current source from a predetermined value, and provides negative feedback so that the current amount becomes a predetermined value. It has a controlling error amplifier.

〔作用〕[Effect]

したがって、定電流源を構成づ−る抵抗の抵抗値がばら
つい!、:場合でも、定電流量の所定値からのずれ吊(
誤差)が、差動増幅回路の同相出力電圧の変化として検
出され、その検出結果に応じた負帰還制御がおこなわれ
るので、定電流量は所定値に保たれ、その結果、利得の
変動が生じない。
Therefore, the resistance values of the resistors that make up the constant current source vary! , : Even if the constant current amount deviates from the predetermined value (
error) is detected as a change in the common-mode output voltage of the differential amplifier circuit, and negative feedback control is performed according to the detection result, so the constant current amount is maintained at a predetermined value, resulting in gain fluctuation. do not have.

(実施例) 次に、本発明の実施例について図面を参照して説明する
(Example) Next, an example of the present invention will be described with reference to the drawings.

第1図は本発明の差動増幅回路の第1の実施例の回路図
である。
FIG. 1 is a circuit diagram of a first embodiment of the differential amplifier circuit of the present invention.

本実施例の差動増幅回路は、第4図に示す従来回路にお
いて、定電圧源10を除去し、定電圧源16と、一端が
それぞれ出力端子4と5に接続され、他端がA点におい
て其通接続された同相出力電圧検出用抵抗14.15と
、反転入力が定電圧源16に接続され、非反転入力がA
点に接続され、出力がトランジスタ8のベースに接続さ
れた票差増幅器17とを付加したものである。
In the differential amplifier circuit of this embodiment, the constant voltage source 10 is removed from the conventional circuit shown in FIG. The common-mode output voltage detection resistors 14 and 15 connected to each other at
A differential amplifier 17 whose output is connected to the base of the transistor 8 is added.

ここで、負荷抵抗11.12の抵抗値をR1とし、同相
出力電圧検出用抵抗14と15の抵抗値を共にRAとし
、定電圧源13の電圧をV。0とし、基準電圧用の定電
圧源16の電圧をVRとする。
Here, the resistance value of the load resistors 11 and 12 is R1, the resistance values of the common-mode output voltage detection resistors 14 and 15 are both RA, and the voltage of the constant voltage source 13 is V. 0, and the voltage of the constant voltage source 16 for reference voltage is VR.

また、同相出力電圧検出用抵抗14..15の抵抗値R
は、負荷抵抗11.12の抵抗値R]−よりも十分大き
いものとする。さらに、誤差増幅器17の入力インピー
ダンスは十分高いものとする。
In addition, common mode output voltage detection resistor 14. .. 15 resistance value R
is sufficiently larger than the resistance value R]- of the load resistor 11.12. Furthermore, it is assumed that the input impedance of the error amplifier 17 is sufficiently high.

次に、実施例の動作を説明する。同相出力電圧検出用抵
抗14.15の接続点Aの電圧は、二つの出力端子4,
5にあられれる互いに逆相の出力信号を2分圧した電圧
であり、差動増幅回路の同相出力電圧に等しくなる。こ
のA点の電位(同相出力電圧)は基準電圧VRと比較さ
れ、その差に応じた誤差増幅器17の出力により、定電
流源を= 5− 構成するトランジスタ8のベースがバイアスされる。こ
の動作により、定電流源の定電流量に関して、回路的に
負帰還制御がなされる。すなわち、同相出力電圧(A点
の電位)は、差動増幅回路の定電流源の定電流量に依存
して変化するため、同相出力電圧を基準電圧VRと比較
することにより、結果的に、定電流量の所定値からずれ
呈(誤差)を検出でき、この誤差を補正すべく制御がな
されるのCある。差動入力OVでオフセット電圧O■の
ときのトランジスタ6のコレクタ電 得得Gvは R1・RA となる。RA>RLの関係にあるから、q  VCc−
VR ・・・(1) となる。第1の実施例の回路は、(旬式から判るように
電a電圧V。0とM準電圧VRによって決定され、集積
回路内の抵抗値が変動しても、差動利得Gvはばらっが
ない。
Next, the operation of the embodiment will be explained. The voltage at the connection point A of the common-mode output voltage detection resistor 14.15 is the voltage at the connection point A of the two output terminals 4,
This is a voltage obtained by dividing the mutually opposite-phase output signals appearing in the output signals 5 and 5 into two, and is equal to the common-mode output voltage of the differential amplifier circuit. The potential at point A (common-mode output voltage) is compared with reference voltage VR, and the base of transistor 8 constituting the constant current source is biased by the output of error amplifier 17 according to the difference. Through this operation, negative feedback control is performed in terms of the circuit regarding the constant current amount of the constant current source. That is, since the common mode output voltage (potential at point A) changes depending on the constant current amount of the constant current source of the differential amplifier circuit, by comparing the common mode output voltage with the reference voltage VR, as a result, A deviation (error) in the amount of constant current from a predetermined value can be detected, and control is performed to correct this error. The collector voltage gain Gv of the transistor 6 when the offset voltage is O■ with the differential input OV is R1.RA. Since there is a relationship of RA>RL, q VCc-
VR...(1) becomes. The circuit of the first embodiment is determined by the electric voltage V.0 and the M quasi-voltage VR, and even if the resistance value within the integrated circuit changes, the differential gain Gv does not vary. There is no.

第2図は第1図にお(プる誤差増幅器17および定電圧
源16の具体的回路を示す回路図である。
FIG. 2 is a circuit diagram showing a specific circuit of the error amplifier 17 and constant voltage source 16, which are similar to those shown in FIG.

定電圧源16は、抵抗18とツェナーダイオード19と
で構成され、誤差増幅器17は、差動対をなすトランジ
スタ20.21と、差動対をバイアスする定電流源22
と、トランジスタ21のコレクタ電流を入力とするカレ
ントミラー回路を構成するトランジスタ23.24と、
コレクタ接地出力トランジスタ25.26および抵抗2
7とで構成されている。
The constant voltage source 16 includes a resistor 18 and a Zener diode 19, and the error amplifier 17 includes transistors 20 and 21 forming a differential pair, and a constant current source 22 that biases the differential pair.
and transistors 23 and 24 forming a current mirror circuit that receives the collector current of the transistor 21 as an input.
Common collector output transistor 25, 26 and resistor 2
It consists of 7.

第3図は本発明の第2の実施例の回路図である。FIG. 3 is a circuit diagram of a second embodiment of the present invention.

この実施例の差動増幅回路は、第4図に示される従来回
路において、定□電旦源10を除去し、次の構成、すな
わち、トランジスタ6のエミッタにアノードが接続され
たダイオード28と、ダイオード28のカソードにアノ
ードが接続されたダイオード29と、トランジスタ7の
エミッタにアノードが接続されたダイオード30と、ダ
イオード30のカソードにアノードが接続された夕゛イ
オード31と、コレクタが定電圧源13に接続されベー
スが出力端子4に接続されたトランジスタ32と、一端
がトランジスタ32のエミッタに接続され他端が接地さ
れた抵抗33と、コレクタが定電圧源13に接続されベ
ースが出力端子5に接続されたトランジスタ34と、一
端がトランジスタ34のエミッタに接続され他端が接地
された抵抗35と、定電圧源16と、誤差増幅器17と
、一端がそれぞれトランジスタ32.34のエミッタに
接続され、他端が誤差増幅器17の非反転入力に接続さ
れた同相出力電圧検出用抵抗36.37とが付加されて
構成されている。
In the differential amplifier circuit of this embodiment, the constant □ current source 10 is removed from the conventional circuit shown in FIG. A diode 29 whose anode is connected to the cathode of the diode 28, a diode 30 whose anode is connected to the emitter of the transistor 7, a diode 31 whose anode is connected to the cathode of the diode 30, and a collector connected to the constant voltage source 13. A transistor 32 whose base is connected to the output terminal 4, a resistor 33 whose one end is connected to the emitter of the transistor 32 and whose other end is grounded, and whose collector is connected to the constant voltage source 13 and whose base is connected to the output terminal 5. A connected transistor 34, a resistor 35 having one end connected to the emitter of the transistor 34 and the other end grounded, a constant voltage source 16, and an error amplifier 17, each having one end connected to the emitter of the transistor 32, 34, In-phase output voltage detection resistors 36 and 37 whose other ends are connected to the non-inverting input of the error amplifier 17 are added.

第2の実施例の特徴は、差動増幅回路の出力端子4.5
と同相出力電圧検出用抵抗36.37との間にコレクタ
接地トランジスタ32.34が介在している点であり、
また差動対をなすトランジスタ6.7のエミッタにダイ
オード28〜31が接続されている点である。
The feature of the second embodiment is that the output terminals 4.5 of the differential amplifier circuit
A common-collector transistor 32.34 is interposed between the common-mode output voltage detection resistor 36.37,
Another point is that diodes 28 to 31 are connected to the emitters of transistors 6.7 forming a differential pair.

コレクタ接地トランジスタ32.34が存在する形態は
、以下の場合に有効である。例えば、第1の実施例(第
1図)において、誤差増幅器17の入力のインピーダン
スが小さいために、A点に同相出力電圧を得る場合に、
その入力インピーダンスの影響を無視覆ることができな
くなり、調整のために同相出力電圧検出用抵抗14.1
5の抵抗値R^を小さくする必要が生じるときがある。
The configuration in which the common collector transistors 32 and 34 are present is effective in the following cases. For example, in the first embodiment (FIG. 1), when obtaining the common mode output voltage at point A because the input impedance of the error amplifier 17 is small,
The influence of the input impedance cannot be ignored and the common mode output voltage detection resistor 14.1 is used for adjustment.
There are times when it is necessary to reduce the resistance value R^ of 5.

このとき、同相出力電圧検出用抵抗14.15の抵抗値
Rと負荷抵抗11.12の抵抗値R1との間に、R)R
1の関係が成立しなくなる場合があり、こうなると、抵
抗14.1!’+があたかも負荷抵抗11.12と並列
に、負荷抵抗としてf4加された形態となり正確な利得
を設定することが困難となる。
At this time, between the resistance value R of the common mode output voltage detection resistor 14.15 and the resistance value R1 of the load resistor 11.12, R
There are cases where the relationship 1 does not hold, and in this case, the resistance 14.1! '+ is in parallel with the load resistances 11 and 12, and f4 is added as a load resistance, making it difficult to set an accurate gain.

しかし、第3図に示すように、コレクタ接地トランジス
タ32.34を設【プると、その入力インピーダンスが
極めて大ぎいために、負荷抵抗11゜12と同相出力電
圧検出用抵抗36.37とがインピーダンス的に分離さ
れ、前述した問題点が解消する。
However, as shown in FIG. 3, when the common-collector transistors 32 and 34 are installed, their input impedance is extremely large, so the load resistance 11°12 and the common-mode output voltage detection resistor 36,37 They are separated in terms of impedance, and the above-mentioned problems are solved.

また、この実施例の回路は、差動増幅回路の利得を低く
設定したい場合にも有効である。すなわち、誤差増幅器
17は、同相出力電圧が、vR十V になるように制御
する。ただし、vRは定電B[ 圧線16の電圧、■BEはコレクタ接地トランジスタ3
2と34のベース・エミッタ間順方向電圧である。この
時の差動出力段の差動利得Gvは、= 10− qVCC’R’BE とへり、第1の実施例の利得の約1/3となっている。
Further, the circuit of this embodiment is also effective when it is desired to set the gain of the differential amplifier circuit low. That is, the error amplifier 17 controls the common mode output voltage to be vR0V. However, vR is constant voltage B [voltage of voltage line 16, ■BE is collector common transistor 3
This is the base-emitter forward voltage of 2 and 34. The differential gain Gv of the differential output stage at this time is equal to 10-qVCC'R'BE, which is about 1/3 of the gain of the first embodiment.

(2)式の分母に表われる3という数字は、差動対をな
すトランジスタ6.7の各エミッタに2個のダイオード
(28,29あるいは30゜31)が直列に付71Gさ
れ、差動増幅回路の1つの電流経路に、実質的(こ直列
に3つのダイオードが介在する構成となっているためで
ある。トランジスタ6.7のエミッタに接続されるダイ
オードの個数は任念に設定可能η・ある。もちろん(2
)式から明らかなように、この実施例の回路でも、集積
回路の抵抗値が変動しても、差動利得Gvはばらつかな
い。
The number 3 appearing in the denominator of equation (2) means that two diodes (28, 29 or 30°31) are connected in series to each emitter of the transistors 6 and 7 forming a differential pair, and a differential amplification is performed. This is because one current path of the circuit has a configuration in which three diodes are actually interposed in series.The number of diodes connected to the emitter of the transistor 6.7 can be set arbitrarily. Yes, of course (2
) As is clear from the equation, even in the circuit of this embodiment, the differential gain Gv does not vary even if the resistance value of the integrated circuit varies.

以」ニ述べたように、第2の実施例は、(1)第1の実
施例では誤差増幅器17の人力インビーダンスか小さい
ため抵抗14と15の抵抗値1(八を小さくする必要が
生じR>Jが成立しない場合や(2)出力段の差動利(
!7 G vを小さくしたい場合に有効である。
As mentioned above, the second embodiment has the following problems: (1) In the first embodiment, since the human input impedance of the error amplifier 17 is small, it is necessary to reduce the resistance value 1 (8) of the resistors 14 and 15. If R>J does not hold or (2) differential gain of the output stage (
! This is effective when it is desired to reduce 7Gv.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明は、差動増幅回路にお1Jる
定電流源の定電流量のばらつきを同相出力電圧の変化と
して検出し、この定電流を所望(「11こ保つべくn路
内に負帰還制御を行うことにより、抵抗値の変動に起因
する定電流量のばらつきを防止し、その結果、差動増幅
@路の差動利得のばらつきを防止する効果がある。
As explained above, the present invention detects the variation in the constant current amount of the constant current source provided in the differential amplifier circuit as a change in the common mode output voltage, By performing negative feedback control, it is possible to prevent variations in the amount of constant current caused by variations in the resistance value, and as a result, it is effective to prevent variations in the differential gain of the differential amplifier@path.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図および第2図は本発明の差動増幅回路の第1の実
施例の回路図、第3図は本発明の差動増幅回路の第2の
実施例の回路図、第4図は従来例の回路図である。 1.2・・・差動増幅回路の入力端子、3・・・曲設回
路、 4.5・・・差動増幅回路の出力端子、6.7・・・差
動増幅回路の差動対をなず1ヘランジスタ、 8.9・・・差動増幅回路の定電流源を構成するトラン
ジスタと抵抗、 13・・・定電圧源、 11.12・・・差動増幅回路の負荷抵抗、14.15
,36.37・・・同相出力電圧検出用抵抗、 16・・・基準電辻用定電圧源、 17・・・誤差増幅器。 特許出願人  日木電気株式会社 第1図 第2図
1 and 2 are circuit diagrams of a first embodiment of the differential amplifier circuit of the present invention, FIG. 3 is a circuit diagram of a second embodiment of the differential amplifier circuit of the present invention, and FIG. 4 is a circuit diagram of a second embodiment of the differential amplifier circuit of the present invention. FIG. 2 is a circuit diagram of a conventional example. 1.2...Input terminal of differential amplifier circuit, 3...Bending circuit, 4.5...Output terminal of differential amplifier circuit, 6.7...Differential pair of differential amplifier circuit 8.9... Transistor and resistor constituting a constant current source of the differential amplifier circuit, 13... Constant voltage source, 11.12... Load resistance of the differential amplifier circuit, 14 .15
, 36.37... Resistor for common mode output voltage detection, 16... Constant voltage source for reference current path, 17... Error amplifier. Patent applicant: Hiki Electric Co., Ltd. Figure 1 Figure 2

Claims (1)

【特許請求の範囲】 差動対をなす一対のトランジスタと、前記トランジスタ
に接続された定電流源とを有する差動増幅回路において
、 同相出力電圧と基準電圧とを比較して、前記定電流源の
電流量の所定値からの誤差を検出し、該電流量を所定値
になるように負帰還制御する誤差増幅器を有することを
特徴とする差動増幅回路。
[Scope of Claims] In a differential amplifier circuit having a pair of transistors forming a differential pair and a constant current source connected to the transistors, a common mode output voltage and a reference voltage are compared, and the constant current source is 1. A differential amplifier circuit comprising an error amplifier that detects an error in the amount of current from a predetermined value and performs negative feedback control to control the amount of current so that the amount of current becomes the predetermined value.
JP62019091A 1987-01-28 1987-01-28 Differential amplifying circuit Pending JPS63185208A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62019091A JPS63185208A (en) 1987-01-28 1987-01-28 Differential amplifying circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62019091A JPS63185208A (en) 1987-01-28 1987-01-28 Differential amplifying circuit

Publications (1)

Publication Number Publication Date
JPS63185208A true JPS63185208A (en) 1988-07-30

Family

ID=11989792

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62019091A Pending JPS63185208A (en) 1987-01-28 1987-01-28 Differential amplifying circuit

Country Status (1)

Country Link
JP (1) JPS63185208A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05102740A (en) * 1991-01-15 1993-04-23 Crystal Semiconductor Corp Low-strain unit-gain amplifier for digital to analog converter
WO2008129629A1 (en) * 2007-04-11 2008-10-30 Fujitsu Limited Mixer
WO2011001523A1 (en) * 2009-07-01 2011-01-06 パイオニア株式会社 Light-quantity detecting device, and light-quantity information processing device
JP2012050006A (en) * 2010-08-30 2012-03-08 Olympus Corp Amplifier circuit

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05102740A (en) * 1991-01-15 1993-04-23 Crystal Semiconductor Corp Low-strain unit-gain amplifier for digital to analog converter
WO2008129629A1 (en) * 2007-04-11 2008-10-30 Fujitsu Limited Mixer
WO2011001523A1 (en) * 2009-07-01 2011-01-06 パイオニア株式会社 Light-quantity detecting device, and light-quantity information processing device
JP5085785B2 (en) * 2009-07-01 2012-11-28 パイオニア株式会社 Light amount detection device and light amount information processing device
US8742314B2 (en) 2009-07-01 2014-06-03 Pioneer Corporation Light amount detecting apparatus, and light amount information processing apparatus
JP2012050006A (en) * 2010-08-30 2012-03-08 Olympus Corp Amplifier circuit

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