KR100456238B1 - Frequency up conversion mixer of CMOS device - Google Patents

Abstract

The present invention relates to a frequency up-conversion mixer of a CMOS device used in a communication system. The negative feedback circuit is connected to a signal input part of a frequency up-conversion mixer to improve linearity of the input part. We present a frequency upconversion mixer for CMOS devices with low power and high linearity.

Description

Frequency up conversion mixer of CMOS device

The present invention relates to a frequency upconversion mixer of a CMOS device, and more particularly, to a frequency upconversion mixer of a CMOS device capable of increasing linearity at low voltage.

1 is a block diagram of a W-CDMA system transmitter having a general super-heterodyne structure.

Referring to FIG. 1, a transmitter of a W-CDMA system generally includes a converter unit 100, an I / Q modulator 200, a variable gain amplifier (VGA) 300, and an RF modulator 400. And a transmit / receive antenna 500.

The converter unit 100 receives a predetermined data signal DATA and converts it into an analog signal (Digital to Analog converter; 110), and the analog converted by the D / A converter (110) And a low pass filter (LPF) 120 for filtering the switching noise of the signal.

The I / Q modulator 200 generates an I / Q oscillator 220 and an I / Q oscillator 220 for generating an in-phase and quadrature phase. A frequency up-conversion mixer 210 is used to up-convert a baseband signal to an intermediate frequency (IF) using an in-phase and quadrature phase.

The RF modulator 400 includes an IF filter 410 for filtering out unnecessary signals included in the output signal of the variable gain amplifier 300, an RF oscillator 430 for generating an RF signal, and an RF filter 430. An RF mixer 420 for mixing the output signal of the IF filter 410 and the output signal of the RF oscillator 430, a power amplifier 440 for supplying power to the transmit / receive antenna 500, and the The transmit / receive antenna 500 comprises a transmit / receive switch 450 for protecting the receiver from a transmission output when transmitting and receiving the echo signal 500 and transmitting an echo signal to the receiver when receiving.

As described above, the frequency up-conversion mixer 210 constituting the I / Q modulator 200 generally includes a D / A converter 110 and a baseband filter 120 at the rear end of the converter unit 100. As it is positioned, a large input signal is received from the converter unit 100. Therefore, the frequency up-conversion mixer 210 must be configured to have a wide linearity.

Recently, to improve the linearity of such a frequency up-conversion mixer, US Patent No. 6,242,963, registered on June 5, 2001, and "Differential Mixer With Improved Linearity", and US Patent No. 6,094,571, registered on July 25, 2000 "Differential Class AB Mixer Circuit" and US Patent No. 6,121,818, "Mixer Using Replica Voltage-Current Converter," registered on September 9, 2000, are presented. Reference is made here only to US Pat. No. 6,242,963 (hereinafter referred to as 'prior art').

The conventional technology is based on the most widely used Gilbert mixer structure, and the output load is composed of a diode and a transistor in a linear region to improve the nonlinearity of the output active load, thereby improving linear characteristics in a desired signal range. It suggests a way to make it possible. This will be described in detail with reference to FIG. 2 as follows.

FIG. 2 is a detailed circuit diagram showing a frequency up-conversion mixer of the prior art, which includes a mixing unit 211, a common mode output unit 212, and first and second linear load units 213 and 214.

The mixing unit 211 is connected between the output terminals OUT ⁺ and OUT ⁻ and the first node B1 to operate the first and second NMOS transistors N1 and N2 operated according to the carrier signals LO ⁺ and LO ⁻ . ), and an output terminal (OUT ⁺ and OUT ^-) and a second node (B2) is connected between the carrier signal (LO ⁺ and LO ^-) third and 4 NMOS transistor (N3 and N4 which operates in accordance with), a a first node (B1), a second node (B2) and the third node (B3) connected between the RF signal (RF ⁺ and RF ^-) of claim 5 and claim 6 NMOS transistors (N5 and N6) which is operated in accordance with the And a seventh NMOS transistor N7 connected between the third node B3 and the ground source Vss and operated according to the gate voltage Vg.

The common mode output unit 212 is connected in series between the output terminals OUT ⁺ and OUT ⁻ to operate the fifth and sixth PMOS transistors P5 operated according to an output signal of a replica bias circuit 215. And P6).

Between the first linear load unit 213 is a voltage source (Vcc) and an output terminal a first PMOS transistor (P1) and the voltage source (Vcc) and said output terminal (OUT ⁺⁾ connected in a diode form between (OUT ^+), It is composed of a second PMOS transistor P2 connected in the form of a triode and operated according to a reference control voltage VC.

Between the second linear load unit 214 is a voltage source (Vcc) and an output terminal (OUT ^{- -),} the third being connected to a diode between the PMOS transistor (P3) and the voltage source (Vcc) and said output terminal (OUT) A fourth PMOS transistor P4 connected in the form of a triode and operated according to the reference control voltage VC is formed.

As described above, the first and second linear load section (213 and 214) and a carrier signal which is operated as a mixer is the active load of the prior art, type (LO ⁺ and LO ^{- -)} and the RF signal (RF ⁺ and RF) And a mixing unit 211 for receiving and mixing, wherein the first and second linear load units 213 and 214 are connected to diode-connected first and third PMOS transistors P1 and P3 in a triode form. And the second and fourth PMOS transistors P2 and P4 operating in the linear region are connected in parallel to have ideal linear load characteristics in a certain region. That is, the mixer of the prior art can obtain a relatively large linear region by using a linear active load rather than a general active load.

However, the mixer of the prior art has a seventh NMOS transistor N7 operated as a current source, fifth and sixth NMOS transistors N5 and N6 to which RF signals RF ⁺ and RF ⁻ are input, carrier signals LO ⁺ and The first to fourth NMOS transistors N1 to N4 and the first to fourth PMOS transistors P1 to P4 of the first and second linear load units 213 and 214 to which LO ⁻ are input are stacked. Because of the architecture, considering the threshold voltage (V _th ) of each transistor, it is not suitable to obtain a wide linear region in a low voltage structure of less than 3V. That is, in the case of the stack structure as described above, there is a limit in the linearity of the structure even if the current is increased, and there is a problem in that the current amount must be increased in proportion to the square of the linear region. Therefore, the above problem is a problem in the low power design of the transceiver to meet the trend of miniaturization of the portable terminal in recent years.

Recently, in order to solve the above problems, a frequency signal input by configuring an attenuator in front of a mixer constituting a transmitter is a low frequency signal close to baseband (hereinafter referred to as an input signal). ) Is proposed. However, in the case of an up-conversion of the input signal in the mixer of the transmitter, in the ideal case, only the sum (+) and the difference (-) frequencies of the input signal and the carrier frequency are output, whereas the DC signal is included in the input signal. In this case, the carrier component by the product of the DC offset and the carrier and the carrier component by the feed-through of the parasitic capacitor are output. At this time, as the input signal approaches the baseband signal, the carrier signal is output very close to the output signal frequency of the mixer (that is, the sum and difference of the input signal and the carrier signal).

Thus, the carrier signal is output as is without being removed by the filter. In this case, when the output carrier signal is large, the noise characteristic of the transmitter is very poor due to inter-modulation distortion caused by non-linearity of blocks located at the rear of the mixer. Spectrum specifications will not be satisfied. In addition, when the carrier signal is low, the influence of the component generated by the DC offset of the input terminal is increased, and as the carrier signal increases, the carrier feed-through component generated by the parasitic capacitor increases, which causes more serious problems. .

Since the effect of the DC offset is displayed at the output terminal as a value relative to the input signal size, increasing the size of the input signal is reduced by that amount, and the component by coupling is also relatively reduced when the input signal size is increased. In other words, if the size of the input signal is increased by increasing the input linear region of the mixer, the carrier attenuation of the output signal can be improved. However, in the case where the input terminal is a CMOS transistor, there is a problem in that the linear region is generally severely limited and power consumption is increased to increase linearity.

Accordingly, the present invention has been made to solve the above problem, by forming a negative feedback circuit in the signal input portion of the frequency up-conversion mixer to increase the size of the input signal and improve the linearity to relatively reduce the size of the carrier signal The purpose is to improve carrier attenuation.

In addition, the present invention provides a frequency up-conversion mixer for a CMOS device which is suitable for a low voltage structure, has a function of compensating for DC offset, and has a simple structure.

1 is a block diagram illustrating a W-CDMA system transmitter of a general super-heterodyne structure.

2 is a detailed circuit diagram for explaining a conventional frequency up-conversion mixer.

3 is a detailed circuit diagram illustrating a frequency up-conversion mixer according to the present invention.

4 is an equivalent circuit diagram of an output unit shown in FIG. 3.

FIG. 5 is a simulation graph for explaining the linear characteristics of the frequency up-conversion mixer shown in FIG. 3. FIG.

<Explanation of symbols for the main parts of the drawings>

100: converter 110: D / A converter

120: baseband filter 200: I / Q modulator

210: frequency up-conversion mixer 211: mixing unit

212: common mode output unit 213: first linear load unit

214: second linear load portion 215: replica bias portion

216: first input unit 217: second input unit

218: output section 219: offset compensation circuit section

220: I / Q oscillator 300: variable gain amplifier

400: RF modulator 410: IF filter

420: RF Mixer 430: RF Oscillator

440: power amplifier 450: transceiver switch

500: transmit and receive antenna

The present invention comprises first means for increasing the linearity of a positive potential input signal in a negative feedback loop manner; Second means for increasing the linearity of the negative potential input signal, the second feedback loop being configured in a negative feedback loop manner; And a mixing unit for mixing the signal output from the first and second means with the carrier signal.

Hereinafter, the present invention will be described with reference to the accompanying drawings.

3 is a detailed circuit diagram illustrating a frequency up-conversion mixer of a CMOS device according to an exemplary embodiment of the present invention.

Referring to FIG. 3, in the frequency up-conversion mixer of the CMOS device of the present invention, both signal input units (hereinafter referred to as 'first input units') 216 to which an input signal IN ⁺ is input from the outside, an input signal IN ⁻ It comprises a) an output unit 218 for outputting to the mixing ^-) input sound signal input unit (hereinafter referred to as "second input section" hereinafter) 217 and the input signal (iN ⁺ and iN is.

The first input unit 216 is connected between the power supply voltage source Vcc and the first node B11 to operate according to the potential of the second node B12 and the first node (N11). A second NMOS transistor N12 connected between B11 and the ground voltage source Vss and operated according to the first signal Vb1, and connected between a power supply voltage source Vcc and the second node B12 and connected to the second node. The first PMOS transistor P11 operated according to the signal Vb2 and the second node B12 and the third node B13 are connected to the source follower according to the input signal IN ⁺ . A third NMOS transistor N13 operated and a fourth NMOS transistor N14 connected between the third node B13 and the ground voltage source Vss and operated according to the potential of the first node B11. do. Here, the first, third and fourth NMOS transistors N11, N13, and N14 form a negative feedback loop to maintain the drain current of the third NMOS transistor N13 constant.

The second input unit 217 is connected between the power source voltage source Vcc and the fourth node B14 to operate according to the potential of the fifth node B15, and the fourth node (N15). A sixth NMOS transistor N16 connected between N14 and a ground voltage source Vss and operated according to the first signal Vb1, a power source voltage Vcc, and a fifth node B15, and The second PMOS transistor P12 operated according to the second signal Vb2 and the fifth node B15 and the sixth node B16 are connected to the source follower according to the input signal IN ⁻ . And a seventh NMOS transistor N17 and an eighth NMOS transistor N18 connected between the sixth node B16 and the ground voltage source Vss and operated according to the potential of the fourth node B14. Here, the fifth, seventh, and eighth NMOS transistors N15, N17, and N18 form a negative feedback loop, thereby maintaining a constant drain current of the seventh NMOS transistor N17.

The output unit 218 includes a first resistor R1 connected between the power supply voltage source Vcc and the output terminal OUT ⁻ , and a second resistor R2 connected between the power supply voltage source Vcc and the output terminal OUT ⁺ . ), A ninth NMOS transistor N19 connected between the first resistor R1 and the seventh node B17 and operated according to a carrier signal LO ⁺ , the seventh node B17 and a ground voltage source. A carrier signal connected between the thirteenth NMOS transistor N23 and the second resistor R2 and the seventh node B17 that are connected between the first and second nodes B11 and operated according to the potential of the first node B11. An eleventh NMOS transistor N20 operated according to (LO ⁻ ) and an eleventh NMOS transistor (N20) connected between the first resistor R1 and an eighth node B18 and operated according to a carrier signal L0 ⁻ . the eighth N21) and to the second resistor (R2) and the eighth node (12 first NMOS transistor (N22) is connected between B18) which operates in accordance with the carrier signal (LO ^+), Is connected to the side-(N18) and a ground voltage source (Vss) is composed of the 14 NMOS transistor (N24) is operated in accordance with the potential of the fourth node (B14).

Referring to the operation characteristics of the CMOS frequency up-conversion mixer of the present invention configured as described above are as follows.

First, in the first input unit 216, a current flowing through the first PMOS transistor P11 and the second NMOS transistor N12 is generated by the first signal Vb1 and the second signals Vb1 and Vb2 having a predetermined magnitude. Stays constant. Thus, the first PMOS transistor P11 and the second NMOS transistor N12 operate as current sources.

In this state, when the input signal IN ⁺ having a potential lower than a predetermined reference potential is input to the gate of the third NMOS transistor N13 operating as a source follower, the drain voltage of the third NMOS transistor N13 increases. As a result, the potential of the second node B12 is increased. As the potential of the second node B12 increases, the gate voltage of the first NMOS transistor N11 increases and the source voltage of the first NMOS transistor N11 increases, thereby increasing the potential of the first node B11. The potential rises. In addition, as the potential of the first node B11 increases, the gate voltage of the fourth NMOS transistor N14 increases. As a result, the potential on the third node B13 drops as the drain voltage of the fourth NMOS transistor N14 falls, so that a negative feedback loop in which the drain voltage of the third NMOS transistor N13 falls Is formed.

On the contrary, when the input signal IN ⁺ having a potential higher than a predetermined reference potential is input to the gate of the third NMOS transistor N13 that operates as a source follower, the drain voltage of the third NMOS transistor N13 is lowered so that The potential of the two nodes B12 is lowered. As the potential of the second node B12 drops, the gate voltage of the first NMOS transistor N11 decreases and the source voltage of the first NMOS transistor N11 falls, thereby decreasing the voltage of the first node B11. The potential drops. In addition, as the potential of the first node B11 drops, the gate voltage of the fourth NMOS transistor N14 decreases. As a result, as the drain voltage of the fourth NMOS transistor N14 rises, the potential of the third node B13 rises, so that the negative feedback loop in which the drain voltage of the third NMOS transistor N13 rises. Is formed.

That is, the drain voltage of the first PMOS transistor P11 operating as a current source is constant by repeating the operation through the negative feedback loop via the first, third and fourth NMOS transistors N11, N13, and N14. Therefore, the current of the third NMOS transistor N13 is always kept constant. Therefore, the third NMOS transistor N13, which operates as a source follower, has an almost ideal linear characteristic, and the voltage gain at that time is about '1'.

On the other hand, in the second input unit 217, similar to the first input unit 216, the second PMOS transistor P12 and the second by the first signal (Vb1) and the second signal (Vb1 and Vb2) having a predetermined magnitude. The 6 NMOS transistor N16 operates as a current source.

In this state, when an input signal IN ⁻ having a potential lower than a predetermined reference potential is input to the gate of the seventh NMOS transistor N17 operating as a source follower, the drain voltage of the seventh NMOS transistor N17 increases. As a result, the potential of the fifth node B15 increases. As the potential of the fifth node B15 increases, the gate voltage of the fifth NMOS transistor N15 increases and the source voltage of the fifth NMOS transistor N15 increases, thereby increasing the potential of the fourth node B14. The potential rises. In addition, as the potential of the fourth node B14 increases, the gate voltage of the eighth NMOS transistor N18 increases. As a result, the potential on the sixth node B16 drops as the drain voltage of the eighth NMOS transistor N18 falls, so that a negative feedback loop in which the drain voltage of the seventh NMOS transistor N17 falls is obtained. Is formed.

On the contrary, when an input signal IN ⁻ having a potential higher than a predetermined reference potential is input to the gate of the fifth NMOS transistor N15 that operates as a source follower, the drain voltage of the fifth NMOS transistor N15 is lowered to decrease the first voltage. The potential of the five nodes B15 is lowered. As the potential of the fifth node B15 drops, the gate voltage of the fifth NMOS transistor N15 decreases, and the source voltage of the fifth NMOS transistor N15 falls, thereby reducing the potential of the fourth node B14. The potential drops. In addition, as the potential of the fourth node B14 decreases, the gate voltage of the eighth NMOS transistor N18 drops. As a result, as the drain voltage of the eighth NMOS transistor N18 increases, the potential of the sixth node B16 increases, so that a negative feedback loop in which the drain voltage of the seventh NMOS transistor N17 increases. Is formed.

That is, the second input unit 217 passes through the negative feedback loop through the fifth, sixth and seventh NMOS transistors N15, N16, and N17 in the same manner as the operating characteristics of the first input unit 216. By repeating the operation, the current of the seventh NMOS transistor N17 is always kept constant. Therefore, the seventh NMOS transistor N17, which operates as a source follower, has an almost ideal linear characteristic, and the voltage gain at that time is about '1'.

The potential on the third node B13 of the first input unit 216 operated as described above is 'V _B13 ', and the potential of the sixth node B16 of the second input unit 217 is 'V _B16 ', the third and the like. When the gain of the source follower of the seventh NMOS transistors N13 and N17 is 'K ₁ ', it becomes 'V _B13 = K ₁ × (IN ⁺ ), V _B16 = K ₁ × (IN ⁻ )'.

That is, since the linear characteristics of 'V _B13 ' and 'V _B16 ' are almost ideal, the difference lo1 of the current flowing through the fourth and eighth NMOS transistors N14 and N18 by the third resistor R3 is as follows. It may be represented as in Equation 1.

Here, the Rin is the resistance value of the third resistor (R3), Vin = (IN +) - a ^- (IN).

Meanwhile, as shown in FIG. 4, the thirteenth and fourteenth NMOS transistors N23 and N24 of the output unit 218 operate as current sources lo2p and lo2n, and their operating characteristics are as follows.

The thirteenth NMOS transistor N23 is operated in the same manner as the fourth NMOS transistor N14 of the first input unit 216 according to the potential of the first node B11, so that the thirteenth NMOS transistor N23 The same current flows as the fourth NMOS transistor N14. In addition, the fourteenth NMOS transistor N24 may also operate in accordance with the potential of the fourth node B14 in the same manner as the eighth NMOS transistor N18 of the second input unit 217, thereby allowing the fourteenth NMOS transistor N24 to operate. The same current flows through the eighth NMOS transistor N18.

In this case, when the sizes of the fourth and eighth NMOS transistors N14 and N18 and the thirteenth and fourteenth NMOS transistors N23 and N24 are different from each other, current flows in proportion to the difference between the sizes.

That is, the sizes of the fourth and eighth NMOS transistors N14 and N18 are 'W ₁ / L ₁ ', and the sizes of the thirteenth and fourteenth NMOS transistors N23 and N24 are 'W ₂ / L ₂ '. In this case, the difference lo2 of the current flowing through the thirteenth and fourteenth NMOS transistors N23 and N24 operating as a current source of the output unit 218 is expressed by Equation 2 below.

,

Subsequently, the current difference lo2 flowing through the thirteenth and fourteenth NMOS transistors N23 and N24 is mixed by the ninth through twelfth NMOS transistors N19 through N22 to which carrier signals LO ⁺ and LO ^- are input. To the first and second resistors R1 and R2.

In this case, the resistance values of the first and second resistors R1 and R2 of the output unit 218 are referred to as 'Rout', and the size of the 19th to 22nd NMOS transistors N19 to N22 is 'W ₃ / L'. _3, the output terminal (OUT ^+, OUT ^-) of the output unit 218 when referred to as "output voltage (Vout) to be outputted to a can lead to the expression (3) below.

,

Here, 'I1' is a drain current of the ninth NMOS transistor N19, 'I2' is a drain current of the tenth NMOS transistor N20, and 'I3' is a drain current of the eleventh NMOS transistor N21, 'I4'. Represents a drain current of the twelfth NMOS transistor N22, and 'I1-I2' and 'I3-I4' are represented by Equation 4 below.

,

Here, 'V _B17 ' is the potential of the seventh node B17, 'V _B17 = _{ΔV s} / 2 + V _s ', and' V _B18 'is the potential of the eighth node B18,' V _B18 = -ΔV _s / 2 + V _s '. 'V _th ' is the threshold voltage of the ninth through twelfth NMOS transistors N19 through N22, and 'Is a constant value of the MOS device.

In addition, the current sources lo2p and lo2n in the DC state are represented by Equation 5 below, and the difference between the current sources lo2p-lo2n is shown in Equation 6.

That is, by using Equations 4 and 6, 'I1-I2 + I3-I4' may be obtained as in Equation 7.

Therefore, by substituting Equations 2 and 7 into Equation 3, the output voltage Vout of the mixer of the present invention can be obtained as Equation 8 below.

Here, since 'V _dc ' and 'V _s ' are constants, as can be seen from Equation 8, the frequency upconversion mixer of the CMOS device of the present invention has an input voltage V _in and a carrier voltage V _LO . has a linear characteristic, particularly the input voltage (V _in), the source follower of the first and the second input unit (216 and 217) is input is the input voltage (V _in) because it improves linearity by using a feedback circuit the negative The linear characteristics are very good.

FIG. 5 is a graph simulating the linear characteristics of the frequency up-conversion mixer of the CMOS device shown in FIG. 3, wherein V _L0 = 0.25V, V _dc = 2.2V (Vcc = 3.0V, temperature = 25 ° C.). This is a simulated graph.

Here, X-axis represents the input voltage (Vin), Y axis represents the output (OUT ^+, OUT ^-) output voltage (V _out) to represent an output voltage of the waveform rising from left to right in the graph is 'OUT ^+' terminal of the (V _out) shows the waveform, the waveform that drops from left to right are ^- indicates the output voltage (V _out) waveform of the terminal 'OUT'.

As shown, each output for an input voltage (V _in) ^- it can be seen that the increasing or lowering the almost linear output voltage (V _out) of ⁽⁺ OUT, OUT). Therefore, it can be seen that the CMOS frequency up-conversion mixer of the present invention has a characteristic that is linear with respect to the input voltage V _in .

In addition, the frequency upconversion mixer of the CMOS device of the present invention includes an offset compensation circuit unit 219 for compensating for mismatches of DC offset and differential structure that may occur in a general mixer.

The offset compensation circuit 219 is a seventh node (B17) and a ground voltage source (Vss) and the 15 NMOS transistor (N25) is connected to be operated in accordance with the offset signal (OFF ⁺⁾ between the eighth node (B18) and The sixteenth NMOS transistor N26 is connected between the ground voltage source Vss and operated according to the offset signal OFF ⁻ .

The offset compensation circuit 219 is normal, the can is turned off (OFF), the offset signal (OFF ^+, OFF ^-) for generating an external DC offset control circuit when operated (not shown), the DC offset and differential structure It acts as a current source that supplies an equivalent current to compensate for mismatches

The transistors constituting the frequency upconversion mixer of the CMOS device of the present invention described above are all designed to operate in a saturation region. The reason for this is as follows.

In the case of a transmission mixer, the main cause of carrier components at the output of the mixer is the carrier offset and the mismatch in the differential structure caused by the DC offset and parasitic elements. In order to reduce the component caused by the DC offset, the mixer should be designed so that the DC offset is sufficiently small compared to the signal size. In order to reduce the component caused by the mismatch, the size of the transistor related to the gain is not sufficiently sensitive to the mismatch. Mixers must be designed to operate in large and stable areas.

In addition, the layout of the mixer should be designed symmetrically, because in the case of carrier feed-through, the symmetry of the layout is very important. Since the carrier feed-through component is proportional to the carrier signal size, it can be reduced by reducing the size of the carrier signal. In addition, it is possible to reduce the carrier feed-through component by increasing the size of the input signal. As the size of the input signal increases, the carrier signal by the feed-through is constant, while the output signal is larger, so that the relative carrier feed-through component can be reduced. Because there is.

In particular, the ninth through twelfth NMOS transistors N19 through N22 of the output unit 218 may operate in a switching region, or operate in a linear region or a saturation region. However, when operating in the linear region instead of the switching region, the linearity of the carrier signal input is good, but the frequency characteristic is worsened because the transistor size becomes too large, and the transconductance (gm) characteristic of the NMOS is not stable. Cause a mismatch error. Accordingly, the ninth through twelfth NMOS transistors N19 through N22 may be operated in a switching region or in a saturation region.

Therefore, in the present invention, since the carrier signal size must be large to operate the ninth to twelfth NMOS transistors N19 to N22 in the switching region, the ninth to twelfth NMOS transistors N19 to reduce carrier feed-through are required. N22) is operated in the saturation region and the size of the carrier signal is reduced.

As described above, the present invention can increase the magnitude of the input signal by forming a negative feedback loop circuit in the input portion to which the input signal is input, thereby improving the linearity of the input signal. Therefore, the carrier attenuation of the mixer can be improved due to the increase in the magnitude of the input signal.

In addition, the present invention can improve the noise characteristics due to the intermodulation distortion, etc. by improving the linearity of the input signal, and can improve the linear characteristics and the carrier attenuation of the mixer by using the offset compensation circuit.

In addition, the present invention can provide a frequency up-conversion mixer that is suitable for low voltage devices, has a function of compensating for DC offset, and is simple in structure.

Claims (17)

A frequency up-conversion mixer that receives a differential input potential and a differential carrier potential and outputs a differential output potential, An input having first and second NMOS transistors for receiving the differential input potentials through gates, and feedback means connected to sources and drains of the first and second NMOS transistors; And Receives the differential carrier potential and the differential transfer potential output from the feedback means of the input unit and outputs the differential output potential proportional to the product of the differential input potential and the differential carrier potential, wherein the differential transfer potential is the differential input An output for inducing a differential current proportional to the potential, The feedback means may include a third and fourth NMOS transistor, each gate connected to a drain of each of the first and second NMOS transistors, and each source connected to a respective node outputting the differential transfer potential; Fifth and sixth NMOS transistors connected to respective sources of the third and fourth NMOS transistors, each source connected to a ground voltage source, and each drain connected to a respective node outputting the differential transfer potential; and And a first resistor connected to the first NMOS transistor source and the source of the second NMOS transistor. The method of claim 1, And said first and second NMOS transistors are source followers. delete The method of claim 1, The feedback means A first current source connected to a drain and a power supply voltage source of the first NMOS transistor; A second current source connected to a drain and a power supply voltage source of the second NMOS transistor; A third current source connected to a source and a ground voltage source of the third NMOS transistor; And And a fourth current source connected to the source and ground voltage source of the fourth NMOS transistor. The method of claim 4, wherein The first current source is a first PMOS transistor having a gate connected to a first current control voltage source, a source connected to a power supply voltage source, and a drain connected to a drain of the first NMOS transistor. The second current source is a second PMOS transistor having a gate connected to a first current control voltage source, a source connected to a power supply voltage source, and a drain connected to a drain of a second NMOS transistor. The third current source is a seventh NMOS transistor connected to a gate of the second current control voltage source, a source of the ground voltage source, and a drain of the third NMOS transistor. And said fourth current source is an eighth NMOS transistor connected at a gate thereof to a second current control voltage source, at a source thereof to a power supply voltage source, and at a drain thereof to a source of a fourth NMOS transistor. delete The method of claim 1, The output unit A converter configured to generate the differential current proportional to the differential input potential from the differential transfer potential; And And a mixing section for producing said differential output potential from said differential current and said differential carrier potential. The method of claim 7, wherein The conversion unit A ninth NMOS transistor having a gate connected to one of the differential transfer potentials and a source connected to a ground voltage source; And A gate having a tenth NMOS transistor connected at a remaining terminal of the differential transfer potential and a source connected to a ground voltage source; And the drain current of the ninth and tenth NMOS transistors is the differential current. The method of claim 7, wherein The mixing unit An eleventh NMOS transistor having a gate connected to one of the differential carrier potentials, a source to one current of the differential current, and a drain to one potential of the differential output potential; A twelfth NMOS transistor connected at a gate thereof to the other potential terminal of the differential carrier potential, a source to one current terminal of the differential current, and a drain to the remaining potential terminal of the differential output potential; A thirteenth NMOS transistor connected at a gate thereof to the other potential terminal of the differential carrier potential, a source to the remaining current terminal of the differential current, and a drain to one potential terminal of the differential output potential; A fourteenth NMOS transistor having a gate connected to one of the differential carrier potentials, a source to a remaining current end of the differential current, and a drain to a remaining potential end of the differential output potential; A second resistor connected to a power supply voltage source and one potential terminal of said differential output potential; And And a third resistor connected to a power supply voltage source and the remaining potential terminal of said differential output potential. The method of claim 9, And the eleventh to fourteenth NMOS transistors are configured to operate in a saturation region. The method of claim 7, wherein The output unit A frequency up-conversion mixer, further comprising: an offset compensation circuit for compensating for mismatches of DC offset and differential structure. The method of claim 11, The offset compensation circuit unit A fifteenth NMOS transistor having a gate connected to one of the differential offset compensation potentials, a source connected to a ground voltage source, and a drain connected to one current terminal of the differential current; And And a sixteenth NMOS transistor whose gate is connected to the remaining potential of the differential offset compensation potential, the source is connected to the ground voltage source, and the drain is connected to the remaining current stage of the differential current. delete delete delete delete delete