JP2000354055A - Constant-current outputting circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable a constant-current outputting circuit to maintain a fixed current drive ability, regardless of fluctuations in the bias voltage of a cable. SOLUTION: A river 10 constituted in a CMOS is connected to a twisted pair cable 20, having two signal lines respectively coupled with a bias voltage Vm via terminating resistance, Rt, so that the driver 10 make data transmission, when the direction of a constant current made to flow to the cable 20 is changed. A gate voltage control circuit 30 fixes drain currents Idp and Idn of a PMOS driving transistor 11 and an NMOS driving transistor 14 in the driver 10 by controlling the gate voltages Vgp and Vgn of the transistors 11 and 14, by utilizing a detected bias voltage Vm and voltage drops at replica resistors 33 and 38 constituting the replicas of the terminators Rt.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a constant current output circuit for outputting a constant current to a cable.

[0002]

2. Description of the Related Art The IEEE 1394 standard regulates differential data transmission using twisted pair cables.

[0003] US Patent No. 5,418,478 discloses a CMOS differential circuit for driving a twisted pair cable. The circuit includes a first PMOS drive transistor having a drain electrode coupled to a first signal line of the cable, a second PMOS drive transistor having a drain electrode coupled to a second signal line of the cable, , A first NMOS drive transistor having a drain electrode coupled to the first signal line, and a second NMOS drive transistor having a drain electrode coupled to the second signal line. When the first PMOS drive transistor applies a current to the first signal line, the current returned via the terminating resistor and the second signal line is converted to a second signal.
NMOS drive transistor sucks. Second PMO
When the S drive transistor supplies current to the second signal line, the first NMOS drive transistor sinks the current returned via the terminating resistor and the first signal line. That is, the first and second PMOS drive transistors constitute a constant current output circuit for outputting a positive constant current to the cable, respectively, and the first and second NMOS drive transistors respectively provide a negative constant current to the cable. A constant current output circuit for outputting is configured.

[0004]

In the above-described conventional constant current output circuit, on the premise that each of the four driving transistors operates in a saturation region, the gate-source voltage of each of the four driving transistors is maintained at a constant value. Was configured as follows. Therefore, there is a serious problem due to the potential of the other device connected to the end of the cable.

[0005] Two signal lines of the cable are to be coupled to a certain bias voltage Vm via a terminating resistor Rt. Here, the power supply of the constant current output circuit is V
dd and Vss. The power supply Vdd is connected to the first and second P
A constant power supply voltage (for example, a positive voltage of +2.5 V) is applied to each source electrode of the MOS drive transistor. The power supply Vss applies a constant power supply voltage (for example, a ground voltage of 0 V) to each source electrode of the first and second NMOS driving transistors. At this time, the bias voltage Vm of the cable viewed from the power supply Vdd fluctuates according to the potential of the other device connected to the end of the cable. The bias voltage Vm viewed from the power supply Vss also fluctuates according to the potential of the partner device. For example, when the ground voltage of the counterpart device is higher than the voltage of the power supply Vss of the constant current output circuit, the bias voltage Vm viewed from the power supply Vdd of the constant current output circuit decreases. Due to the variation of the bias voltage Vm, the first
And if the drain-source voltage of each of the second PMOS drive transistors becomes too small, as long as the gate-source voltage of each of these transistors is maintained at a constant value, its respective operating point will be out of the saturation region. Moving to the linear region, the constant current output is no longer maintained. Conversely, when the ground voltage of the other device is lower than the voltage of the power supply Vss of the constant current output circuit, the power supply Vss
The bias voltage Vm seen from the side becomes small. Due to the variation of the bias voltage Vm, the first and second NMOSs
If the drain-source voltage of each of the driving transistors becomes too small, the operating point of each of these transistors moves from the saturation region to the linear region as long as the gate-source voltage of each of these transistors is maintained at a constant value. As a result, the constant current output can no longer be maintained. Further, the bias voltage Vm of the cable may be intentionally changed in order to transmit the data transmission rate setting information and the power management information. In this case, the same problem may occur.

An object of the present invention is to provide a constant current output circuit capable of maintaining a constant current driving ability irrespective of fluctuations in a bias voltage of a cable.

[0007]

In order to achieve the above object, the present invention provides a constant current output circuit for outputting a constant current to a cable coupled to a bias voltage via a terminating resistor. Is provided, and when the drain-source voltage of the drive transistor changes due to the change in the bias voltage of the cable, the change in the drain current of the drive transistor due to the change in the voltage is compensated. The current driving capability of the driving transistor is adjusted so that the drain current of the driving transistor substantially matches the constant current. This current drive capability is adjusted by controlling the gate voltage of the drive transistor, the substrate voltage, and the like. This adjustment is performed based on the detection result of the change in the bias voltage or based on system information indicating the prediction of the change in the bias voltage.

The driving transistor in the constant current output circuit of the present invention can be replaced with a driver composed of a plurality of driving transistors connected in parallel to each other. The current driving capability of this driver is adjusted by digitally controlling the number of activated transistors or by analogly controlling the gate voltage of a specific transistor.

[0009]

FIG. 1 shows a configuration example of a constant current output circuit according to the present invention. A driver 10 and a gate voltage control circuit 30 in FIG. 1 are connected to a twisted pair cable (hereinafter simply referred to as “cable”) having a characteristic impedance Z0.
That. ) 20 to form a constant current output circuit for outputting a constant current. The two signal lines of the cable 20 are each coupled to a bias voltage Vm via a terminating resistor Rt. For example, Z0 = 110Ω and Rt = 55Ω. Here, the value of the bias voltage Vm is determined by a partner device connected to the end of the cable 20.

A driver 10 for outputting a current to a cable 20 includes a PMOS driving transistor 11 and first and second PMOS switching transistors 12 and 13.
, An NMOS drive transistor 14, and first and second NMOS switching transistors 15 and 16. The PMOS drive transistor 11 supplies a gate electrode that receives the gate voltage Vgp, a source electrode that receives a constant power supply voltage (for example, a positive voltage of +2.5 V) from the power supply Vdd, and a drain current Idp (for example, 4 mA) that flows into the cable 20. As described above, the first signal line of the cable 20 has the drain electrode coupled to the second signal line of the cable 20 via the second PMOS switching transistor 13 via the first PMOS switching transistor 12. It is a transistor. NMOS
The driving transistor 14 is provided with a gate electrode receiving the gate voltage Vgn and a constant power supply voltage (for example, 0 V
A second NMOS switching transistor is connected to a first signal line of the cable 20 via a first NMOS switching transistor 15 so as to absorb a drain current Idn (for example, 4 mA) from the cable 20. And a drain electrode respectively coupled to the second signal line of the cable 20 via the second signal line. The data signal IN is applied to the gate electrodes of the first PMOS switching transistor 12 and the first NMOS switching transistor 15, and the complementary data signal XIN is applied to the gates of the second PMOS switching transistor 13 and the second NMOS switching transistor 16. Each is given to an electrode. Therefore, when IN = L and XIN = H, a current flows from the power supply Vdd to the cable 20 via the PMOS drive transistor 11 and the first PMOS switching transistor 12, and the second NMOS
A current is sucked into the power supply Vss via the switching transistor 16 and the NMOS drive transistor 14. Assuming that the voltages at the output nodes of the driver 10 are Vo1 and Vo2, Vo1> Vo2 in this case. When IN = H and XIN = L, a current flows from the power supply Vdd to the cable 20 via the PMOS drive transistor 11 and the second PMOS switching transistor 13,
In addition, current is drawn from the cable 20 to the power supply Vss via the first NMOS switching transistor 15 and the NMOS driving transistor 14. In this case, Vo1 <
Vo2.

Now, what kind of equipment is connected to the end of the cable 20 is undefined. That is, the bias voltage Vm of the cable 20 viewed from the driver 10 varies depending on the ground voltage of the other device. In some cases, the other device intentionally changes the bias voltage Vm. Therefore, the drain-source voltage Vdsp of the PMOS drive transistor 11 and the drain-source voltage Vdsn of the NMOS drive transistor 14 also fluctuate. In this way, a gate voltage control circuit 30 is provided to keep Idp and Idn unchanged even when Vdsp and Vdsn fluctuate.
The gate voltage control circuit 30 of FIG. 1 adjusts the current drive capability of the driver 10 by controlling the gate voltages Vgp and Vgn so that the change in the output current of the driver 10 due to the change in the bias voltage Vm is compensated. Is what you do. More specifically, the gate voltage control circuit 30 includes a first PMO which is provided between the power supply Vdd and the reference node Np and forms a replica of the PMOS drive transistor 11.
S replica transistor 31 and first and second PMOs
A series circuit of a second PMOS replica transistor 32 forming a replica of the S switching transistors 12 and 13 and a replica resistor 33 forming a replica of the terminating resistor Rt, and a constant current I from the series circuit to the power supply Vss.
The gate voltage of the first PMOS replica transistor 31 is controlled so that the constant current source 34 for sucking k and the bias voltage Vm of the cable 20 are detected, and the voltage of the reference node Np matches the bias voltage Vm. And an operational amplifier 35 for supplying the controlled gate voltage Vgp to the gate electrode of the PMOS drive transistor 11. Further, the gate voltage control circuit 30 includes a first NMOS replica transistor 36, which constitutes a replica of the NMOS drive transistor 14, and a first and second NMOS switching transistor 14 interposed between the power supply Vss and the reference node Nn. , Which constitutes 15 replicas
NMOS replica transistor 37 and the terminating resistor Rt
, A constant current source 39 for flowing a constant current Ik from the power supply Vdd into the series circuit, and a bias voltage Vm of the cable 20 are detected to detect the reference node Nn. An operational amplifier 40 for controlling the gate voltage of the first NMOS replica transistor 36 so that the voltage coincides with the bias voltage Vm, and supplying the controlled gate voltage Vgn to the gate electrode of the NMOS driving transistor 14. Have. k
When a real number that satisfies ≧ 1 is k, the magnitude of the current Ik is 1 / k times the output current of the driver 10 and each replica transistor 31, 32, 36, 37 is 1 / k times the main transistor. A gate width, each replica resistor 3
Reference numerals 3 and 38 have a resistance value k times the terminating resistance Rt.

FIG. 2 shows a configuration example of the constant current sources 34 and 39 in FIG. In FIG. 2, 50 is a constant voltage generation circuit, 60 is a constant current generation circuit, and 70 is a current mirror circuit. The constant voltage generation circuit 50 includes a BGR (band gap reference) circuit 51, an operational amplifier 52, and two resistors 53 and 54. The BGR circuit 51
For example, H. Banba et al., "A CMOS Band-Gap Reference
Circuit with Sub 1VOperation ", 1998 Symposium on
VLSI Circuits, Digest of Technical Papers, pp.228-
As described in 229, this circuit can generate a constant voltage independent of temperature fluctuation, power supply voltage fluctuation and the like. The constant current generating circuit 60 includes an operational amplifier 61, an NMOS transistor 62, and a replica resistor 63 forming a replica of the terminating resistor Rt. Current mirror circuit 70
Are five PMOS transistors 71, 72, 75, 7
8, 79 and four NMOS transistors 73, 74,
76 and 77.

FIG. 3 shows how the operating point of the PMOS drive transistor 11 in FIG. 1 moves. According to the configuration of FIG. 1, a deep bias Vgp is applied to the gate electrode of the PMOS drive transistor 11 as Vdsp decreases, so that the operating point moves to P, Q, R, and S. As a result, the drain current Idp can maintain a constant value. Assuming that the gate voltage Vgp (= −1.5 V) at the operating point P is held as in the related art, for example,
When Vdsp becomes smaller than 0.5 V, the operating point moves from the saturation region to the linear region, and Idp becomes smaller.

FIG. 4 shows how the operating point of the NMOS drive transistor 14 in FIG. 1 moves. According to the configuration of FIG. 1, a higher bias Vgn is applied to the gate electrode of the NMOS drive transistor 14 as Vdsn decreases, so that the operating point moves to X, Y, and Z, and as a result, the drain current Idn maintains a constant value. can do.

As described above, according to the configuration of FIG. 1, by changing the direction of the constant current flowing through the cable, a stable operation of the data transmission system becomes possible. In addition, there is an effect that noise caused by fluctuation of the current flowing through the power supply line and the ground line of the system can be avoided.

It is also possible to adopt a driver configuration in which the PMOS drive transistor 11 in FIG. 1 is divided into two, each of which is connected in series to each of the switching transistors 12 and 13. The same applies to the NMOS drive transistor 14. In this case, it is also possible to exchange the positions of the driving transistor and the switching transistor that constitute each pair.

FIG. 5 is a circuit diagram of the gate voltage control circuit 30 shown in FIG.
Are shown. Gate voltage control circuit 30 of FIG.
In a, a variable voltage generation circuit 80 is provided instead of the replica resistors 33 and 38 in FIG. The variable voltage generation circuit 80 detects the bias voltage Vm of the cable, and detects the first and second variable voltages Vj and Vw from the bias voltage Vm.
Is a circuit for generating. Here, the voltage difference Vj-Vm
And Vm−Vw represent a voltage drop (for example, 2 mA × 55Ω = 0.11 V) at the terminating resistor Rt.

FIG. 6 shows the internal configuration of the variable voltage generation circuit 80 in FIG. Variable voltage generation circuit 80 of FIG.
Is provided with first and second replica resistors 94 and 95 that constitute a replica of the terminating resistor Rt. A constant current flows through both replica resistors 94 and 95, and the first replica resistor 9
4 generates the first variable voltage Vj by adding the voltage drop at 4 to the bias voltage Vm, and generates the second variable voltage Vw by subtracting the voltage drop at the second replica resistor 95 from the bias voltage Vm. It is. These addition and subtraction are performed by the operational amplifier 93.
This is performed by an adder-subtractor circuit composed of the replica resistors 94 and 95. The other components in FIG. 6 constitute a constant current source similar to that in FIG. 2 for allowing a constant current to flow through both replica resistors 94 and 95. 81 is a BGR circuit, 82, 8
6 is an operational amplifier, 83 is a resistor, 84, 85, 88, 89
Is a replica resistor constituting a replica of the terminating resistor Rt, 8
7, 90 are PMOS transistors, 91, 92 are NMO
It is an S transistor.

FIG. 7 shows a modification of FIG. FIG.
The variable voltage generation circuit 80a includes first and second replica resistors 94 and 98 that constitute replicas of the terminating resistor Rt, and supplies a constant current to both replica resistors 94 and 98, respectively, and the first replica resistor 94 The first variable voltage Vj is added by adding the voltage drop in the resistor 94 to the bias voltage Vm, and the second variable voltage is added by subtracting the voltage drop in the second replica resistor 98 from the bias voltage Vm.
Are generated respectively. 96 is a PMOS transistor, and 97 is an operational amplifier.

FIG. 8 shows another modification of FIG.
The variable voltage generation circuit 80b of FIG. 8 includes first and second replica resistors 103, 1 forming a replica of the terminating resistor Rt.
04, a constant current is applied to both replica resistors 103 and 104, and a voltage drop at the first replica resistor 103 is added to the bias voltage Vm to thereby convert the first variable voltage Vj to the second replica resistor 103. A second variable voltage Vw is generated by subtracting the voltage drop at 104 from the bias voltage Vm. 99 and 100 are PMOS transistors, 101 and 1
02 is an NMOS transistor.

FIG. 9 shows another configuration example of the constant current output circuit according to the present invention. The driver 10a, the activation transistor number control circuit 25, and the gate voltage control circuit 30b in FIG. 9 constitute a constant current output circuit for outputting a constant current to the cable 20. The driver 10a is a driver including a plurality of drive transistors connected in parallel to each other. The activation transistor number control circuit 25 includes:
The driver 1 according to the bias voltage Vm of the cable 20
This is a circuit for digitally controlling the number of activated drive transistors in Oa. Gate voltage control circuit 30
b is a circuit for analogly controlling the gate voltage of a specific drive transistor in the driver 10a.

FIG. 10 shows the internal configuration of the driver 10a in FIG. The driver 10a has a common power supply Vdd
And a fourth power supply drive transistor 11, 11a, 11b, 11c having a source electrode coupled to the second power supply and a drain electrode commonly coupled to each other, and a common power supply Vss.
, And first to fourth NMOS drive transistors 14, 14a, 14b, and 14c each having a source electrode coupled to the gate electrode and a drain electrode commonly coupled to each other. The gate electrode of the first PMOS drive transistor 11 applies the gate voltage Vgp controlled steplessly to the second to fourth PMOs.
The gate electrodes of the S drive transistors 11a, 11b, 11c receive the activation logic signals Nap, Nbp, Ncp, respectively. These four PMOS drive transistors 1
1, 11a, 11b and 11c have a common drain electrode,
It is coupled to a first signal line of the cable 20 via a first PMOS switching transistor 12 and to a second signal line of the cable 20 via a second PMOS switching transistor 13, respectively. Therefore, these four PMOS drive transistors 11, 11a, 11
b and 11c constitute a PMOS driver 17 for flowing the current Idp into the cable 20. First NMO
The gate electrode of the S drive transistor 14 receives a steplessly controlled gate voltage Vgn, and the gate electrodes of the second to fourth NMOS drive transistors 14a, 14b, 14c receive activation logic signals Nan, Nbn, Ncn, respectively. receive.
These four NMOS drive transistors 14, 14a,
The common drain electrode of the first NMO 14b, 14c
Cable 20 via S switching transistor 15
Are coupled to the second signal line of the cable 20 via the second NMOS switching transistor 16, respectively. Therefore, these four NMOs
The S drive transistors 14, 14a, 14b, 14c
The NMOS driver 18 for drawing the current Idn from the cable 20 is configured. Activation logic signals Nap, Nb
p, Ncp, Nan, Nbn and Ncn are supplied from the activation transistor number control circuit 25, and the gate voltages Vgp and Vgn are supplied from the gate voltage control circuit 30b. Where 4
, PMOS drive transistors 11, 11a, 11b,
The voltage between the common drain electrode and the common source electrode of 11c is Vdsp, and the voltage between the common drain electrode and the common source electrode of the four NMOS drive transistors 14, 14a, 14b and 14c is Vdsn. And

FIG. 11 shows the gate voltage control circuit 3 shown in FIG.
0b shows the internal configuration. The gate voltage control circuit 30b in FIG. 11 is a circuit obtained by removing the operational amplifiers 35 and 40 and the variable voltage control circuit 80 from the configuration of the gate voltage control circuit 30a in FIG. The PMOS replica transistor 31 has a drain electrode and a gate electrode short-circuited to each other, and the voltage Vgp of these electrodes is supplied to the gate electrode of the first PMOS drive transistor 11. NMO
The S replica transistor 36 has a drain electrode and a gate electrode shorted to each other, and the voltage Vgn of these electrodes is
Is supplied to the gate electrode of the first NMOS drive transistor 14.

FIG. 12 shows an internal configuration of the activation transistor number control circuit 25 in FIG. The activation transistor number control circuit 25 shown in FIG. 12 detects the bias voltage Vm of the cable, and generates a first and second variable voltages Vj and Vw from the bias voltage Vm. 5 to 8) and first to sixth comparators 111 to 116.

First, the first to third comparators 111 to 111
The function of 113 will be described. First comparator 11
1 supplies the L level activation logic signal Nap to the gate electrode of the second PMOS drive transistor 11a when the first variable voltage Vj satisfies the condition Vj> Vdd-γap, and otherwise supplies the H level signal Nap. Is what you do.
The second comparator 112 determines that Vj satisfies the condition Vj> Vdd-γ
When bp is satisfied, the L level activation logic signal Nbp is
Otherwise, the H level signal Nbp is changed to the third PMO
This is supplied to the gate electrode of the S drive transistor 11b. The third comparator 113 determines that Vj satisfies the condition Vj>
When Vdd-γcp is satisfied, the L-level activation logic signal Ncp is output.
To the gate electrode of the PMOS drive transistor 11c. Here, voltage drops caused by flowing a constant current through the resistors R1, R2, and R3 are represented by γap, γbp, and γ.
When cp is used, the voltage V
dd-γap, Vdd-γbp and Vdd-γcp can be generated. The ON voltage of the first and second PMOS switching transistors 12 and 13 is set to Vswp, and certain set voltages are set to Vap, Vbp, Vcp (for example, Vap = 0.8V, Vbp = 0.
4V, Vcp = 0.2V), γap = Vswp + Va
The values of the resistors R1, R2, and R3 are set so that p, γbp = Vswp + Vbp, and γcp = Vswp + Vcp are satisfied. Since the voltage Vdsp in FIG. 10 is equal to Vdd−Vswp−Vj, if Vdsp ≧ Vap, all of the second to fourth PMOS drive transistors 11a, 11b, 11c are turned off, and if Vbp ≦ Vdsp <Vap, the voltage Vdsp is equal to Vdd−Vswp−Vj. The second PMOS drive transistor 11a is turned on, and if Vcp ≦ Vdsp <Vbp, the second and third PMOS drive transistors 11a and 11b are turned on.
Turns on, and if Vdsp <Vcp, the second, third and fourth Ps
The number of activation transistors in driver 10a is determined according to bias voltage Vm so that MOS drive transistors 11a, 11b, 11c are turned on.

Next, the fourth to sixth comparators 114 to
The function of 116 will be described. Fourth comparator 11
4 supplies an H level activation logic signal Nan when the second variable voltage Vw satisfies the condition Vw <Vss + γan, and otherwise supplies an L level signal Nan to the gate electrode of the second NMOS drive transistor 14a. It is.
The fifth comparator 115 determines that Vw is equal to or less than Vw <Vss + γ.
When bn is satisfied, the activation logic signal Nbn at H level is
Otherwise, the L-level signal Nbn is output to the third NMO
This is supplied to the gate electrode of the S drive transistor 14b. The sixth comparator 116 determines that Vw is the condition Vw <
When Vss + γcn is satisfied, the H level activation logic signal Ncn is output. Otherwise, the L level signal Ncn is output to the fourth level.
To the gate electrode of the NMOS drive transistor 14c. Here, the voltage drop caused by flowing a constant current through the resistors R4, R5, R6 is represented by γan, γbn, γ
cn, the voltage V
ss + γan, Vss + γbn, and Vss + γcn can be generated. When the ON voltage of the first and second NMOS switching transistors 15 and 16 is Vswn and certain set voltages are Van, Vbn, and Vcn (Van>Vbn> Vcn), γ
an = Vswn + Van, γbn = Vswn + Vbn, γcn = Vswn +
The respective values of the resistors R4, R5 and R6 are set so that Vcn is satisfied. The voltage Vdsn in FIG. 10 is Vw−Vswn−
Vss≥Van, the second to fourth N
All of the MOS drive transistors 14a, 14b, 14c are turned off, and if Vbn ≦ Vdsn <Van, the second NMO
The S drive transistor 14a turns on, and Vcn ≦ Vdsn <Vb
If n, the second and third NMOS drive transistors 14
a, 14b are turned on, and if Vdsn <Vcn, the second, third and fourth NMOS drive transistors 14a, 14b, 1
The number of activation transistors in driver 10a is determined according to bias voltage Vm so that 4c is turned on.

FIG. 13 shows the PMOS driver 1 shown in FIG.
7 shows the voltage-current characteristics. According to this example, Vds
If p ≧ Vap, the first PMOS drive transistor 11 bears all of the output current Idp of the PMOS driver 17 as in the conventional case. However, if Vdsp <Vap, the number of activation transistors in the PMOS driver 17 increases as Vdsp decreases. Therefore, the output current Idp of the PMOS driver 17 can be maintained at a substantially constant value as shown by the solid line in the figure.

FIG. 14 shows the NMOS driver 1 shown in FIG.
8 shows a voltage-current characteristic. According to this example, Vds
If n ≧ Van, the first NMOS drive transistor 14 bears all of the output current Idn of the NMOS driver 18 as in the conventional case. However, if Vdsn <Van, the number of activation transistors in the NMOS driver 18 increases as Vdsn decreases. Therefore, the output current Idn of the NMOS driver 18 can be maintained at a substantially constant value.

The PMOS driver 17 and the NMOS driver
The number of drive transistors constituting each of the drivers 18 is arbitrary. The gate width of each drive transistor may be set as appropriate. Further, the magnitude of the gate voltage for activating each driving transistor may be different from each other.

FIG. 15 shows still another configuration example of the constant current output circuit according to the present invention. Driver 10 in FIG.
a, the activation transistor number control circuit 25a, the gate voltage control circuit 30c, and the state machine 26 constitute a constant current output circuit for outputting a constant current to the cable 20. The driver 10a is a driver having the internal configuration described in FIG. State machine 2
Numeral 6 is for providing system information indicating prediction of fluctuation of the bias voltage Vm to the activation transistor number control circuit 25a and the gate voltage control circuit 30c. This system information is created from the actual fluctuation detection result of the bias voltage Vm of the cable 20, or is created from the information described below that is not based on the detection of the bias voltage Vm. The activation transistor number control circuit 25a controls the activation logic signals Nap, Nbp, Ncp according to the system information given from the state machine 26 so as to digitally control the number of activated driving transistors in the driver 10a. , Nan, Nbn
And Ncn to the driver 10a. The gate voltage control circuit 30c is, for example, a functional extension of the gate voltage control circuit 30 shown in FIG. 1 or the gate voltage control circuit 30a shown in FIG. 5, and has a gate voltage Vgp of a specific driving transistor in the driver 10a. And Vgn
For analog control according to the bias voltage Vm of the cable 20 or system information given from the state machine 26.

FIG. 16 shows a configuration example of a data transmission system using the constant current output circuit of FIG. FIG.
In this system, data is transmitted from the driver D1 of the first device 200 to the receiver R of the second device 201 via the first twisted pair cable 203, and the data is transmitted from the driver D2 of the first device 200 to the third device 202. May be transmitted via the second twisted pair cable 204 to the receiver R. For example, the driver D1 has the configuration shown in FIG. In the present system, by changing the cable bias voltage Vm, speed signaling information for setting a data transmission rate and power management information for shifting the present system to a sleep state can be transmitted. The system information (FIG. 15) indicating the prediction of the fluctuation of the bias voltage Vm is created from the detection result of the actual fluctuation of the bias voltage Vm at the time of transmitting the speed signaling information or the power management information, or is obtained by detecting the bias voltage Vm. It is created from information such as a timer (TIM), power supply voltage fluctuation (Vdd), and temperature fluctuation (T).

FIG. 17 shows how the cable bias voltage Vm varies in the system shown in FIG. FIG. 17 shows three modes of the system. "Mode 1" is for connecting and disconnecting cables,
This is a mode in which the device power is turned on and off. The system supports live insertion and removal of twisted pair cables. “Mode 2” is a mode in which the fluctuation of the bias voltage Vm occurs. For example, the bias voltage Vm may fluctuate significantly due to an artificial operation in mode 1, or the bias voltage Vm may fluctuate intentionally for transmission of speed signaling information or power management information. Also, the bias voltage Vm may fluctuate due to fluctuations in the power supply voltage or temperature of the device.
“Mode 3” is a mode in which effective data transmission is performed.

FIG. 18 shows the state machine 26 in FIG.
3 shows the state transition. The state machine 26 detects a transition between the modes 1, 2, and 3. When a cable is connected or the power supply of the device is turned on, the bias voltage Vm changes suddenly. At this time, the state machine 26 supplies the bias voltage Vm
Is slightly increased, a transition from mode 1 (initial state) to mode 2 (transient state) is detected, and system information indicating the predicted fluctuation of the bias voltage Vm is created. In response to this system information, the activation transistor number control circuit 25a and the gate voltage control circuit 30c
0a is adjusted. However, the gate voltage V
If the bias voltage Vm fluctuates so rapidly that the feedback control of gp and Vgn cannot follow, the operation of the gate voltage control circuit 30c is frozen to prevent unstable operation, and only the activation transistor number control circuit 25a is used. May be operated. Further, the gate voltage control circuit 30c may change the gate voltages Vgp and Vgn according to the system information. Then, when the bias voltage Vm becomes a regular value, data transmission starts. At this time, the state machine 26 detects a transition from mode 2 (transition state) to mode 3 (transmission state). In the mode 3, the gate voltage control circuit 30c mainly adjusts the current driving capability of the driver 10a so as to compensate for a minute change in the bias voltage Vm. The state machine 26 may operate the gate voltage control circuit 30c intermittently according to the timer information. At the time of transmitting the speed signaling information, the bias voltage Vm fluctuates greatly. At this time, the state machine 26 supplies the bias voltage Vm
, A transition from mode 3 (transmission state) to mode 2 (transient state) is detected based on the actual fluctuation detection result, and system information indicating fluctuation prediction of the bias voltage Vm is created. Further, when the bias voltage Vm fluctuates greatly during transmission of the power management information, the state machine 26 sets the bias voltage Vm
, A transition from mode 3 (transmission state) to mode 2 (sleep state) is detected based on the actual fluctuation detection result, and system information indicating fluctuation prediction of the bias voltage Vm is created.
Further, even when there is a power supply voltage fluctuation or a temperature fluctuation in mode 3, the state machine 26 creates system information indicating a prediction of the fluctuation of the bias voltage Vm. The activation transistor number control circuit 25a and the gate voltage control circuit 30c adjust the current driving capability of the driver 10a in response to the system information. Even when the cable is disconnected or the power supply of the device is turned off, the current drivability of the driver 10a is adjusted in response to the system information indicating the predicted fluctuation of the bias voltage Vm.

Although an example of a constant current output circuit for differential data transmission has been described above, the present invention is also applicable to a constant current output circuit for single-ended data transmission.

[0035]

As described above, according to the present invention, in a constant current output circuit for outputting a constant current to a cable coupled to a bias voltage via a terminating resistor,
At least one drive transistor for outputting a current to a cable is provided, and when a drain-source voltage of the drive transistor changes due to a change in a bias voltage of the cable, an output of the drive transistor accompanying the change in the voltage is provided. Since the current drive capability of the drive transistor is adjusted to compensate for a change in current, a constant current output circuit that can maintain a constant current drive capability regardless of fluctuations in cable bias voltage is provided. can do.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration example of a constant current output circuit according to the present invention.

FIG. 2 is a block diagram showing a configuration example of a constant current source in FIG.

FIG. 3 is a diagram showing how an operating point of a PMOS drive transistor in FIG. 1 moves.

FIG. 4 is a diagram showing how an operating point of an NMOS drive transistor in FIG. 1 moves.

FIG. 5 is a circuit diagram showing a modification of the gate voltage control circuit in FIG. 1;

FIG. 6 is a circuit diagram showing an internal configuration of a variable voltage generation circuit in FIG.

FIG. 7 is a circuit diagram showing a modification of FIG. 6;

FIG. 8 is a circuit diagram showing another modification of FIG. 6;

FIG. 9 is a block diagram showing another configuration example of the constant current output circuit according to the present invention.

FIG. 10 is a circuit diagram showing an internal configuration of a driver in FIG. 9;

11 is a circuit diagram showing an internal configuration of a gate voltage control circuit in FIG.

12 is a circuit diagram showing an internal configuration of an activation transistor number control circuit in FIG.

13 is a diagram showing voltage-current characteristics of the PMOS driver in FIG.

14 is a diagram showing voltage-current characteristics of the NMOS driver in FIG.

FIG. 15 is a block diagram showing still another configuration example of the constant current output circuit according to the present invention.

16 is a block diagram illustrating a configuration example of a data transmission system using the constant current output circuit of FIG.

FIG. 17 is a time chart showing how the cable bias voltage changes in the system shown in FIG. 16;

18 is a state transition diagram of the state machine in FIG.

[Explanation of symbols]

10, 10a driver 11, 11a, 11b, 11c PMOS drive transistor 12, 13 PMOS switching transistor 14, 14a, 14b, 14c NMOS drive transistor 15, 16 NMOS switching transistor 17 PMOS driver 18 NMOS driver 20 Twisted pair cable 25, 25a Activation Transistor number control circuit 26 State machine 30, 30a, 30b, 30c Gate voltage control circuit 31, 36 Driving transistor replica 32, 37 Switching transistor replica 33, 38 Terminating resistor replica 34, 39 Constant current source 35, 40 Operational amplifier Reference Signs List 50 constant voltage generation circuit 60 constant current generation circuit 70 current mirror circuit 80, 80a, 80b variable voltage generation circuit 93, 97 operational amplifier 9 , 95, 98, 103, 104 Replicas of terminating resistors 111-116 Comparators 200, 201, 202 Devices 203, 204 Twisted pair cable Idp Drain current of PMOS drive transistor Idn Drain current of NMOS drive transistor Ik Constant current Np, Nn Reference node Rt Termination resistance Vdd, Vss Power supply Vdsp Drain-source voltage of PMOS drive transistor Vdsn Drain-source voltage of NMOS drive transistor Vgp Gate voltage of PMOS drive transistor Vgn Gate voltage of NMOS drive transistor Vj, Vw Variable voltage Vm Cable bias voltage Vo1, Vo2 Output node voltage of driver

Claims (21)

[Claims] 1. A constant current output circuit for outputting a constant current to a cable coupled to a bias voltage via a terminating resistor, comprising: a gate electrode; a source electrode coupled to a power supply; A drive transistor having a drain electrode, and when the voltage between the drain electrode and the source electrode changes due to the change in the bias voltage, the drain current of the drive transistor associated with the change in the voltage Adjusting means for adjusting the current driving capability of the driving transistor so that the change is compensated and the drain current of the driving transistor substantially matches the constant current. Output circuit. 2. The constant current output circuit according to claim 1, wherein said adjusting means has a function of adjusting a current drive capability of said drive transistor based on a result of detecting a change in said bias voltage. Constant current output circuit. 3. The constant current output circuit according to claim 1, wherein said adjusting means has a function of adjusting a current driving capability of said driving transistor based on system information indicating a prediction of a fluctuation of said bias voltage. Constant current output circuit. 4. The constant current output circuit according to claim 1, wherein said adjusting means includes a gate voltage control circuit for controlling a voltage of said gate electrode of said drive transistor. circuit. 5. The constant current output circuit according to claim 4, wherein the gate voltage control circuit includes: a unit for detecting the bias voltage; and a gate voltage control circuit of the drive transistor interposed between the power supply and a reference node. A series circuit of a replica transistor forming a replica and a replica resistor forming a replica of the terminating resistor; a current source for flowing a constant current through the series circuit; a voltage of the reference node and the detected bias Means for comparing the voltage with a voltage, controlling the gate voltage of the replica transistor based on the result of the comparison, and supplying the controlled gate voltage to the gate electrode of the driving transistor. Characteristic constant current output circuit. 6. The constant current output circuit according to claim 5, wherein the constant current output circuit further includes a switching transistor connected in series to the drive transistor between the power supply and the cable, and The control circuit further includes another replica transistor that is connected in series with the replica transistor and the replica resistor between the power supply and the reference node and that constitutes a replica of the switching transistor. Current output circuit. 7. The constant current output circuit according to claim 4, wherein the gate voltage control circuit includes: a unit for detecting the bias voltage; A replica transistor constituting a replica, a current source for flowing a constant current to the replica transistor, and a variable voltage representing a voltage drop at the terminating resistor from a difference between the detected bias voltage and the detected bias voltage. A variable voltage generating circuit for comparing the voltage of the reference node with the generated variable voltage, controlling a gate voltage of the replica transistor based on a result of the comparison, and controlling the controlled gate voltage. And a means for supplying the driving transistor to the gate electrode of the driving transistor. 8. The constant current output circuit according to claim 7, wherein the constant current output circuit further includes a switching transistor connected in series with the drive transistor between the power supply and the cable, and the gate voltage The constant current output circuit, further comprising another replica transistor that is connected in series with the replica transistor between the power supply and the reference node and that forms a replica of the switching transistor. 9. The constant current output circuit according to claim 7, wherein the variable voltage generation circuit includes: a replica resistor forming a replica of the termination resistor; and the replica resistor when a constant current flows through the replica resistor. Means for adding a voltage drop in the replica resistor to the detected bias voltage or subtracting a voltage drop in the replica resistor from the detected bias voltage. 10. A constant current output circuit for outputting a constant current to a cable coupled to a bias voltage via a terminating resistor, comprising: a gate electrode; a source electrode coupled to a common power supply; A driver including a plurality of drive transistors having a drain electrode commonly coupled to a cable; and a driver between the common drain electrode and the common source electrode of the plurality of drive transistors due to the variation of the bias voltage. When the voltage changes, the change in the output current of the driver accompanying the change in the voltage is compensated, and the current driving capability of the driver is adjusted so that the output current of the driver substantially matches the constant current. A constant current output circuit, comprising: adjusting means for adjusting. 11. The constant current output circuit according to claim 10, wherein said adjusting means has a function of adjusting a current driving capability of said driver based on a result of detecting a change in said bias voltage. Current output circuit. 12. The constant current output circuit according to claim 10, wherein said adjusting means has a function of adjusting a current driving capability of said driver based on system information indicating prediction of fluctuation of said bias voltage. Constant current output circuit. 13. The constant current output circuit according to claim 10, wherein said adjusting means includes an activation transistor number control circuit for controlling the number of activated transistors among said plurality of driving transistors. A constant current output circuit characterized in that: 14. The constant current output circuit according to claim 13, wherein said activation transistor number control circuit comprises: means for detecting said bias voltage; and a transistor to be activated among said plurality of driving transistors. And a means for determining the number of times according to the detected bias voltage. 15. The constant current output circuit according to claim 13, wherein said activation transistor number control circuit estimates the number of transistors to be activated among said plurality of driving transistors and predicts fluctuation of said bias voltage. A constant current output circuit, comprising: means for determining based on system information indicated. 16. The constant current output circuit according to claim 13, wherein said activation transistor number control circuit outputs an activation logic signal to each gate electrode of transistors to be activated among said plurality of driving transistors. A constant current output circuit comprising logic means for supplying. 17. The constant current output circuit according to claim 10, wherein said adjusting means includes a gate voltage control circuit for continuously controlling a voltage of a gate electrode of a specific transistor among said plurality of driving transistors. A constant current output circuit, comprising: 18. The constant current output circuit according to claim 17, wherein the gate voltage control circuit includes: a unit for detecting the bias voltage; and a voltage to be supplied to the gate electrode of the specific transistor. Means for determining the bias current in accordance with the detected bias voltage. 19. The constant current output circuit according to claim 17, wherein the gate voltage control circuit determines a voltage to be supplied to the gate electrode of the specific transistor on the basis of system information indicating fluctuation prediction of the bias voltage. A constant current output circuit, comprising means for determining the current value. 20. A data transmission system comprising: a cable coupled to a bias voltage via a terminating resistor; and a constant current output circuit for outputting a constant current to the cable, wherein the constant current output circuit is A drive transistor having a gate electrode, a source electrode coupled to a power supply, and a drain electrode coupled to the cable; and a voltage between the drain electrode and the source electrode due to the variation of the bias voltage. Is changed, the change in the drain current of the driving transistor accompanying the change in the voltage is compensated, and the current driving capability of the driving transistor is substantially equal to the constant current. A data transmission system comprising: adjusting means for adjusting the data transmission. 21. The data transmission system according to claim 20, wherein said cable is a twisted pair cable.