WO2016185847A1 - Circuit d'interface d'entrée/sortie - Google Patents

Circuit d'interface d'entrée/sortie Download PDF

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Publication number
WO2016185847A1
WO2016185847A1 PCT/JP2016/062289 JP2016062289W WO2016185847A1 WO 2016185847 A1 WO2016185847 A1 WO 2016185847A1 JP 2016062289 W JP2016062289 W JP 2016062289W WO 2016185847 A1 WO2016185847 A1 WO 2016185847A1
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WO
WIPO (PCT)
Prior art keywords
driver
signal
circuit
receiver
line
Prior art date
Application number
PCT/JP2016/062289
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English (en)
Japanese (ja)
Inventor
大塚　寛治
藤井　文明
秋山　豊
佐藤　陽一
Original Assignee
長瀬産業株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 長瀬産業株式会社 filed Critical 長瀬産業株式会社
Publication of WO2016185847A1 publication Critical patent/WO2016185847A1/fr

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines

Definitions

  • the anti-phase CMOS inverter 12 of the driver 10 includes an nMOS transistor 12a and a pMOS transistor 12b.
  • the pMOS transistor 12b is inserted on the power supply side and becomes a pull-up element.
  • an nMOS transistor 12a is inserted on the ground side to serve as a pull-down element.
  • the nMOS transistor 12a and the pMOS transistor 12b are set to have the same on-resistance value.
  • the negative phase CMOS inverter 12 of the driver 10 outputs a negative phase signal (/ Q) that is opposite in phase to the input digital signal (S).
  • the operation of the I / O circuit 1 having the above configuration will be described.
  • the nMOS transistor 11a is switched from OFF to ON, and the pMOS transistor 11b is switched from ON to OFF.
  • the pMOS transistor 12b is switched from ON to OFF, and the nMOS transistor 12a is switched from OFF to ON.
  • the complementary signal energy is supplied from the CMOS differential driver 10 to the pair transmission line 20.
  • a pair of complementary signals (Q, / Q) obtained by complementing the digital signal (S) can be transmitted to the CMOS differential receiver 30 via the pair transmission line 20.
  • the transmission and reception electromagnetic wave traveling time tpd of the internal circuit or the inter-repeater circuit is, for example, a clock of 28 Gbps when the wiring length is such that tr ⁇ 7 tpd.
  • the wiring length corresponding to 3.3 ps is 500 ⁇ m. Similarly, it becomes 1.4 mm at 10 Gbps.
  • the resistance value (Resd) of each of the resistors 41 to 44 has a large value compared to the on-resistance (Ron) of the MOS transistor, so that the signal waveform propagated through the pair transmission line 20 is almost affected. You do n’t have to. Accordingly, the resistance value (Resd) of each of the resistors 41 to 44 is preferably in the range of 500 ⁇ to 2 k ⁇ , and particularly preferably in the range of 1 k ⁇ to 2 k ⁇ .
  • the on-resistance value (Ron) of the MOS transistor substantially matches the specified value equal to the characteristic impedance (Z0) of the transmission line 120.
  • the on-resistance (Ron) of the MOS transistor may be matched within a range of ⁇ 30% with respect to the specified value (Z0).
  • the on-resistance (Ron) of the MOS transistor is preferably within a range of ⁇ 10% with respect to the specified value (Z0), particularly preferably ⁇ 5%, and within a range of ⁇ 1%. It is ideal to be.
  • the I / O circuit 100 has resistors 141 and 143 having resistance values of 500 ⁇ or more on the external connection side of the driver 110 and the receiver 130, respectively. More specifically, the driver-side resistor 141 is inserted in the transmission line 120 on the external connection side of the driver 110, and is connected to the power source and the ground. The resistor 143 on the receiver side is inserted in the transmission line 120 on the external connection side of the receiver 130, and is connected to the power source and the ground. In this way, ESD can be avoided by providing the resistors 141 and 143 having large resistance values of 500 ⁇ or more on the driver 110 side and the receiver 130 side, respectively.
  • the value of “(1 / Ron) + (1 / Resd)” may be within a range of ⁇ 30% of the specified value of “1 / Z0”.
  • the value of “(1 / Ron) + (1 / Resd)” is preferably within a range of ⁇ 10% with respect to the specified value (1 / Z0), and particularly preferably ⁇ 5%.
  • it is ideal to be within a range of ⁇ 1%.
  • the same resistance adjusting means 150 can be provided in the pMOS transistor 111b which is located on the ground side and forms a pull-down element.
  • the I / O circuit 100 shown in FIG. 7 may further include characteristic impedance measurement means, on-resistance measurement means, and voltage control means.
  • the characteristic impedance measuring means is connected to the transmission line 120 and measures the characteristic impedance (Z0) of the transmission line 120.
  • the on-resistance measuring unit measures the on-resistance values (Ron) of the MOS transistors 111a and 111b constituting the driver 110.
  • the voltage control means sets the on-resistance value (Ron) to the specified value (Z0). Determine whether you are doing it. When it is determined that the on-resistance value (Ron) is lower than the specified value (Z0), the voltage control unit determines that the resistance value (Ron) matches the specified value (Z0). Vadjust).
  • the transistor Q4 functions in the same way, and either the transistor Q3 or the transistor Q4 constituting the differentiation circuit is ON, so that the matching absorption is performed even if the reflected wave returns.
  • the differentiation circuit Q3, Q4
  • the differential I / O circuit 1 constructed based on the above design was operated.
  • this I / O circuit 1 the waveforms of the complementary signals detected by the receiver 30 are shown for each operation speed of the driver 10 as shown in FIG.
  • the waveform of the complementary signal was not distorted and the eye pattern was firmly opened. Therefore, even when the driver 10 is operated at 25 Gbps, it can be said that the complementary signal can be properly detected by the receiver 30.
  • Example 1 it was confirmed that the operation was possible up to 25 Gbps. This is a performance that exceeds the simulation limit of 15 Gbps.
  • a high-speed signal having a clock frequency of 15 Gbps or more can be transmitted.
  • each source is connected to the ground of a 20 ⁇ m wide power source / ground pair line descending vertically while being aligned with a total width of 40 ⁇ m with a gate width of 5 ⁇ m.
  • the line is directly connected to the gates of 80 ⁇ m wide pMOS arranged in two upper and lower rows, and the end of the line is open.
  • the source of each pMOS is connected to the power supply line that has come down vertically.
  • the output is connected laterally from the drains of the respective nMOS and pMOS, that is, is pulled out to the right side while maintaining the line structure, and becomes a transmission line having a characteristic impedance of 100 ⁇ from the position away from the pMOS.
  • the nMOS and the pMOS are arranged in a horizontal line, but the nMOS and the pMOS may be arranged vertically.
  • the nMOS and the pMOS itself can be arranged in two upper and lower stages or three upper and lower stages. With such a short distance, the delay time of the line can be ignored with respect to the clock. Therefore, by arranging the nMOS and pMOS in upper and lower rows, there is an advantage that the DC resistance is lowered for two reasons: the wiring branches and the wiring becomes shorter.
  • the present invention relates to an input / output interface circuit. Therefore, the present invention can be widely used in computer related industries.

Abstract

Le problème décrit par l'invention est de pourvoir à un circuit d'entrée/sortie (E/S) qui soit rapide et qui ait une faible consommation d'énergie. La solution de l'invention porte sur un circuit E/S du type différentiel, qui est pourvu : d'un circuit d'attaque 10 qui distribue en sortie des signaux complémentaires correspondant à un signal d'entrée; d'une paire de lignes de transmission 20 qui comprend une première ligne 21 et une seconde ligne 22, et qui transmet les signaux complémentaires distribués en sortie par le circuit d'attaque; et d'un récepteur 30 à l'entrée duquel sont appliqués les signaux complémentaires transmis par la paire de lignes de transmission. Le circuit d'attaque comporte : un inverseur CMOS de phase positive 11 qui fournit, à la première ligne, un signal de phase positive ayant la même phase que le signal d'entrée; et un inverseur CMOS de phase inverse 12 qui fournit, à la seconde ligne, un signal de phase inverse ayant la phase inverse de celle du signal d'entrée. L'inverseur CMOS de phase positive et l'inverseur CMOS de phase inverse sont configurés comprenant des transistors nMOS et des transistors pMOS. Les valeurs de résistance à l'état passant des transistors nMOS et des transistors pMOS correspondent respectivement à une valeur spécifiée qui est la moitié de l'impédance caractéristique de la paire de lignes de transmission, ou sont adaptées à l'intérieur d'une plage de ±30 % de la valeur spécifiée.
PCT/JP2016/062289 2015-05-18 2016-04-18 Circuit d'interface d'entrée/sortie WO2016185847A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2015-101080 2015-05-18
JP2015101080A JP2016219948A (ja) 2015-05-18 2015-05-18 入出力インターフェース回路

Publications (1)

Publication Number Publication Date
WO2016185847A1 true WO2016185847A1 (fr) 2016-11-24

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PCT/JP2016/062289 WO2016185847A1 (fr) 2015-05-18 2016-04-18 Circuit d'interface d'entrée/sortie

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WO (1) WO2016185847A1 (fr)

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6847249B2 (ja) * 2017-10-11 2021-03-24 三菱電機株式会社 演算増幅回路およびａｄ変換器
US11309014B2 (en) 2020-01-21 2022-04-19 Samsung Electronics Co., Ltd. Memory device transmitting small swing data signal and operation method thereof

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02246613A (ja) * 1989-03-20 1990-10-02 Fujitsu Ltd 静電破壊保護回路
JPH0385015A (ja) * 1989-08-28 1991-04-10 Oki Electric Ind Co Ltd Ｍｏｓ出力回路
JPH10242835A (ja) * 1997-02-27 1998-09-11 Hitachi Ltd 出力回路、半導体集積回路、及び電子回路装置
JP2005217999A (ja) * 2004-02-02 2005-08-11 Hitachi Ltd デジタルデータ伝送回路
JP2006340266A (ja) * 2005-06-06 2006-12-14 Sony Corp 差動信号伝送回路および差動信号伝送装置
JP2009105857A (ja) * 2007-10-25 2009-05-14 Ricoh Co Ltd 出力装置、多値出力装置、及び半導体集積装置

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02246613A (ja) * 1989-03-20 1990-10-02 Fujitsu Ltd 静電破壊保護回路
JPH0385015A (ja) * 1989-08-28 1991-04-10 Oki Electric Ind Co Ltd Ｍｏｓ出力回路
JPH10242835A (ja) * 1997-02-27 1998-09-11 Hitachi Ltd 出力回路、半導体集積回路、及び電子回路装置
JP2005217999A (ja) * 2004-02-02 2005-08-11 Hitachi Ltd デジタルデータ伝送回路
JP2006340266A (ja) * 2005-06-06 2006-12-14 Sony Corp 差動信号伝送回路および差動信号伝送装置
JP2009105857A (ja) * 2007-10-25 2009-05-14 Ricoh Co Ltd 出力装置、多値出力装置、及び半導体集積装置

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