US7902872B2 - Data transmitters and methods thereof - Google Patents
Data transmitters and methods thereof Download PDFInfo
- Publication number
- US7902872B2 US7902872B2 US11/892,434 US89243407A US7902872B2 US 7902872 B2 US7902872 B2 US 7902872B2 US 89243407 A US89243407 A US 89243407A US 7902872 B2 US7902872 B2 US 7902872B2
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- Prior art keywords
- emphasis
- channel
- transmission
- transmitted signal
- circuit
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Classifications
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0175—Coupling arrangements; Interface arrangements
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0175—Coupling arrangements; Interface arrangements
- H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
- H03K19/018507—Interface arrangements
- H03K19/018521—Interface arrangements of complementary type, e.g. CMOS
- H03K19/018528—Interface arrangements of complementary type, e.g. CMOS with at least one differential stage
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
Definitions
- swing ranges of higher frequency signals may decrease more than lower frequency signals.
- a pre-emphasis technique in which a swing range of higher frequency signals may be set larger than a swing range of low frequency signals may be used.
- a half-VDD line driver may be used to decrease current.
- the half-VDD line driver may reduce power consumption in half. Such a half-VDD line driver, however, may not achieve a desired bandwidth.
- Example embodiments relate to data transmission technology, for example, data transmitters and methods for adjusting a pre-emphasis level of a line driver used in transmitting data.
- Example embodiments are directed to data transmitters operable in a required bandwidth range.
- Example embodiments are also directed to data transmitters capable of compensating for reduction of high frequency components in data transmission.
- An example embodiment provides a data transmitter.
- a main line driver circuit may transmit an input signal to a receiver via a channel.
- a pre-emphasis circuit may emphasize, boost or raise a voltage level of the transmitted input signal.
- a pre-emphasis controller may control the pre-emphasis circuit. The pre-emphasis controller inputs a transmission condition of the channel and adjusts a pre-emphasis level of the pre-emphasis circuit to increase an amount of current supplied into the channel at a transition time of the input signal in accordance with the transition condition of the channel.
- At least one other example embodiment provides a data transmitter.
- a main line driver circuit may transmit an input signal to a receiver via a channel.
- a pre-emphasis circuit may adjust a characteristic of the transmitted input signal.
- a pre-emphasis controller may determine a transmission condition of the channel, and control the pre-emphasis circuit to adjust the characteristic of the pre-emphasis circuit to increase an amount of current supplied to the channel at a transition time of the input signal based on the determined transmission condition of the channel.
- the pre-emphasis circuit may pre-emphasize, boost or increase the input signal to compensate for reduction of high frequency components of the input signal during transmission of the input signal.
- the pre-emphasis circuit may boost, increase or raise the value of a signal characteristic to compensate for reduction of high frequency components of the input signal.
- the pre-emphasis circuit may increase a bandwidth of the input signal during transmission of the input signal.
- the pre-emphasis circuit may increase a voltage swing range of the input signal during transmission of the input signal.
- the pre-emphasis circuit may increase a slew rate of the input signal during transmission of the input signal.
- the pre-emphasis controller may generate a control signal informing of the transmission condition of the channel and the pre-emphasis circuit may adjust the pre-emphasis level in response to the control signal.
- the pre-emphasis circuit may increase or decrease the pre-emphasis level based on the control signal. For example, the pre-emphasis circuit may increase the pre-emphasis level if the control signal indicates that the transmission condition of the channel is good. Alternatively, the pre-emphasis circuit may decrease the pre-emphasis level if the control signal indicates that the transmission condition of the channel is bad.
- Another example embodiment provides a method of transceiving data by a data transmitter including a pre-emphasis circuit.
- a test transmission may be performed, and a transmission condition of a channel may be determined based on the test transmission.
- a pre-emphasis level may be decreased if the transmission condition is good, or the pre-emphasis level may be increased until the transmission condition is good.
- Another example embodiment provides a method in which a test transmission may be performed.
- a transmission condition of a channel may be determined based on the test transmission, and a characteristic of a transmitted signal may be adjusted to increase an amount of current supplied to the channel at a transition time of the transmitted signal based on the determined transmission condition of the channel.
- FIG. 1 is a block diagram of a data transceiving system according to an example embodiment
- FIG. 2 is a circuit diagram of the data transmitter shown in FIG. 1 ;
- FIG. 3 is a timing diagram showing an example pattern of data transmission through a main line driver according to an example embodiment
- FIG. 4 is a timing diagram showing an example pattern of applying a pre-emphasis device for output voltage of data from the main line driver according to an example embodiment
- FIG. 5 is a flow chart illustrating a method for adjusting a pre-emphasis level in accordance with a channel condition according to an example embodiment
- FIG. 6 is a timing diagram illustrating an output signal, and signals Vi and Evi shown in FIG. 2 ;
- FIG. 7 is a circuit diagram illustrating an example operation of an example embodiment during periods t 1 and t 2 shown in FIG. 6 ;
- FIG. 1 is a block diagram of a data transceiving system according to an example embodiment.
- a data transmitter 100 may include a main line driver circuit 10 , a pre-emphasis circuit 20 , a pre-emphasis controller 30 and/or an input circuit 40 .
- the input circuit 40 may convert relatively low-speed parallel input signals into relatively high-speed serial input signals Vi and Vib.
- the high-speed serial input signals Vi and Vib may be transferred to the main line driver circuit 10 .
- the input circuit 40 may also generate input signals Evi and Evib of the pre-emphasis circuit 20 .
- the main line driver circuit 10 may transfer the high-speed serial input signals Vi and Vib to a receiver 200 .
- a data signal may be reduced in a high frequency band.
- the pre-emphasis circuit 20 may adjust signal characteristics of the data signal in the high frequency band. For example, the pre-emphasis circuit 20 may increase an amount of current of the data signal in the high frequency band, thereby raising a slew rate in the high frequency band to satisfy desired bandwidth conditions.
- the pre-emphasis controller 30 may determine a condition of the transmission line (or channel) 300 by way of a test transmission and adjust a pre-emphasis level of the pre-emphasis circuit 20 accordingly.
- FIG. 2 is a circuit diagram of the data transmitter 100 shown in FIG. 1 .
- the data transmitter 100 may include the main line driver circuit 10 and the pre-emphasis circuit 20 .
- the main line driver circuit 10 may be operable in a smaller current range by connecting NMOS transistors to PMOS transistors and fixing a swinging center node to a voltage half-VDD.
- the data transmitter 100 may operate at a relatively low switching rate, which may not be sufficient for a required bandwidth.
- the pre-emphasis circuit 20 may be associated with the main line driver circuit 10 .
- the main line driver circuit 10 may utilize the input signals Vi and Vib, output signals Out and Outb, a power source current I main , and may include a plurality of transistors.
- the main line driver circuit 10 may include two NMOS transistors 14 and 15 and two PMOS transistors 12 and 13 .
- example embodiments are discussed herein with regard to a specific arrangement of NMOS and PMOS transistors, such an explanation is for example purposes, and example embodiments should not be limited thereto.
- Drains of the PMOS transistors 12 and 13 may be connected to drains of the NMOS transistors 14 and 15 . Gates of the PMOS and NMOS transistors 12 ⁇ 15 may be coupled to the input signals Vi and Vib. Sources of the PMOS transistors 12 and 13 may receive the power source current I main . The drains of the PMOS transistors 12 and 13 may be connected to the output signals Out and Outb and resistors R 1 and R 2 linking with a half power source voltage (half-VDD).
- the pre-emphasis circuit 20 may raise a slew rate by summing a current of the main line driver circuit 10 and a current from the pre-emphasis circuit 20 when there is a data transition.
- the data transmitter 100 may be operable in the required bandwidth and may be able to compensate for reduction of higher frequency components of data in channel transmission.
- the pre-emphasis circuit 20 may utilize the input signals Vi, Vib, Evi, and Evib, the output signals Out and Outb, a power source current I pre , and may include a plurality of transistors.
- the pre-emphasis circuit 20 may include two NMOS transistors 24 and 25 , two PMOS transistors 22 and 23 , and two multiplexers 27 and 28 .
- example embodiments are discussed herein with regard to a specific arrangement of NMOS and PMOS transistors, such an explanation is for example purposes, and example embodiments should not be limited thereto.
- Drains of the PMOS transistors 22 and 23 may be connected to drains of the NMOS transistors 24 and 25 . Gates of the PMOS transistors 22 and 23 may be coupled to the input signals Evi and Evib. Gates of the NMOS transistors 24 and 25 may be coupled to outputs of the multiplexers 27 and 28 .
- the multiplexers 27 and 28 receive the input signals Evi and Vi and a control signal Sel.
- the power source current I pre may flow into the sources of the PMOS transistors 22 and 23 .
- the output signals Out and Outb may be generated from the drains of the PMOS transistors 22 and 23 .
- FIG. 3 is a timing diagram showing an example pattern of data transmission through only the main line driver according to an example embodiment.
- the line driver may use a pre-emphasis circuit to compensate reduction to high frequency component of data.
- FIG. 4 is a timing diagram showing an example pattern in which a pre-emphasis device according to an example embodiment is applied.
- an output voltage may be amplified by establishing the next stage pre-emphasis with high frequency components. Transmitting data with amplified, high frequency components of the data may be reduced less than in the conventional art without a pre-emphasis circuit.
- a reduction rate of high frequency components in transmitted data may depend on a transmission condition of the channel. Better channel conditions may result in less loss, while worse channel conditions result in more loss. Thus, a pre-emphasis level may be adjusted in accordance with or based on channel conditions.
- FIG. 5 is a flow chart illustrating a method for adjusting a pre-emphasis level according to an example embodiment.
- the pre-emphasis controller 30 may conduct or perform a test transmission to determine a transmission condition of the channel 300 .
- the pre-emphasis controller 30 may check or evaluate a transmission condition of the channel 300 . If the channel condition is determined to be good (e.g., sufficient or acceptable for transmission), high frequency components of transmitted data may be reduced less. If the channel condition is bad (e.g., insufficient or unacceptable for transmission), high frequency components of transmitted data may be reduced more.
- the pre-emphasis controller 30 may adjust a pre-emphasis level by based on the determined transmission condition of the channel 300 .
- the pre-emphasis level of the pre-emphasis circuit 20 is lowered at S 120 . If the channel condition is determined to be bad, the pre-emphasis level of the pre-emphasis circuit 20 is raised at S 130 .
- FIG. 6 is a timing diagram illustrating the output signal, and the signals Vi and Evi shown in FIG. 2 .
- Vi is the data input signal.
- the input signal Evi may be obtained by inverting a signal shifted from the signal Vi by a 1-cycle delay.
- 1-cycle refers to a time period in which a relatively short data transition in a data stream occurs.
- a resultant current equal or substantially equal to the current I main of the main line driver circuit 10 and a current I pre of the pre-emphasis circuit 20 may flow through the resistors R 1 and R 2 .
- An increase of the current I main +I pre flowing through the resistors R 1 and R 2 by way of the pre-emphasis circuit 20 may cause a slew rate to increase.
- An increase of slew rate may improve bandwidth.
- This difference of pre-emphasis levels may be represented in Equations 1 and 2 as follows.
- V A 2 R *( I main +I pre )
- V B 2 R *( I main ⁇ I pre )
- V A ⁇ V B 2 R *2 I pre [Equation 1]
- V A ′ 2 R *( I main +I pre )
- a pre-emphasis level may be adjusted to a half its original level based on the signal Sel.
- FIG. 7 is a circuit diagram illustrating an example operation of an example embodiment during time periods t 1 and t 2 shown in FIG. 6 .
- the period t 1 is a high frequency period and the period t 2 is a low frequency period.
- the pre-emphasis may increase a current of the next cycle after transitions of all data.
- a high frequency current may increase in the high frequency period, while a current of the former cycle may increase in the low frequency period.
- the control signal Sel of the pre-emphasis controller 30 may be generated to have the same or substantially the same value regardless of input value.
- the power source currents I main and I pre of the main lone driver circuit 10 and the pre-emphasis circuit 20 may flow in the same direction.
- the output signal Out may be summed I main +I pre .
- the input signals Vi, Vib, Evi, and Evib may enable the PMOS and NMOS transistors 12 , 23 , 15 , and 24 to turn on.
- the power source current I main of the main line driver circuit 10 may flow in a different direction than the power source current I pre of the pre-emphasis circuit 20 .
- the output signal Out may be I main ⁇ I pre .
- the control signal Sel of the pre-emphasis controller 30 when the control signal Sel of the pre-emphasis controller 30 is 1, the input signals Vi, Vib, Evi, and Evib may enable the PMOS and NMOS transistors 12 , 23 , 15 , and 25 to turn on.
- the power source current I main of the main line driver circuit 10 may flow.
- the output signal Out may be I main .
- the data transmitter 100 may control an amount of output current in accordance with the control signal Sel by the pre-emphasis controller 30 .
- Example embodiments may achieve a required bandwidth and/or voltage swing range by adding a pre-emphasis structure to a line driver including a half-VDD. Moreover, because reduction rate of high frequency components in transmitted data is dependent on a channel condition, a pre-emphasis level may be adjusted using a signal not a current.
- example embodiments may provide data transmitters operable in a required bandwidth and/or voltage swing range and/or capable of adjusting a pre-emphasis level.
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- Mathematical Physics (AREA)
- Power Engineering (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Dc Digital Transmission (AREA)
Abstract
Description
V A=2R*(I main +I pre)
V B=2R*(I main −I pre)
V A −V B=2R*2I pre [Equation 1]
V A′=2R*(I main +I pre)
V B′=2R*I main
V A ′−V B′=2R*I pre [Equation 2]
Claims (6)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
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KR1020060079933A KR20080017973A (en) | 2006-08-23 | 2006-08-23 | Data transmitter and method thereof |
KR10-2006-0079933 | 2006-08-23 |
Publications (2)
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US20080048720A1 US20080048720A1 (en) | 2008-02-28 |
US7902872B2 true US7902872B2 (en) | 2011-03-08 |
Family
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Application Number | Title | Priority Date | Filing Date |
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US11/892,434 Active 2028-08-03 US7902872B2 (en) | 2006-08-23 | 2007-08-23 | Data transmitters and methods thereof |
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US (1) | US7902872B2 (en) |
KR (1) | KR20080017973A (en) |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
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KR20100134285A (en) * | 2009-06-15 | 2010-12-23 | 삼성전자주식회사 | Signal transmitting method, signal transmitting apparatus and signal transmitting system |
KR101290080B1 (en) * | 2011-01-28 | 2013-07-26 | 주식회사 실리콘웍스 | A pre-emphasis circuit and differential current signaling system having the same |
CN102545884B (en) * | 2012-02-17 | 2014-04-16 | 无锡芯骋微电子有限公司 | Voltage type data transmitter with high-efficiency pre-emphasis balance |
KR101405241B1 (en) * | 2012-07-27 | 2014-06-10 | 고려대학교 산학협력단 | Transmitter for data communication |
Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6288581B1 (en) | 2001-01-05 | 2001-09-11 | Pericom Semiconductor Corp. | Low-voltage differential-signalling output buffer with pre-emphasis |
US20020061072A1 (en) | 2000-11-17 | 2002-05-23 | Andrew Pickering | Systems for data transmission |
US20020135404A1 (en) * | 2001-03-21 | 2002-09-26 | Payne Robert F. | High speed voltage mode differential digital output driver with edge-emphasis and pre-equalization |
US20040124888A1 (en) | 2002-12-23 | 2004-07-01 | Alcatel | Low voltage differential signaling [LVDS] driver with pre-emphasis |
JP2005217999A (en) | 2004-02-02 | 2005-08-11 | Hitachi Ltd | Digital data transmission circuit |
US7126378B2 (en) * | 2003-12-17 | 2006-10-24 | Rambus, Inc. | High speed signaling system with adaptive transmit pre-emphasis |
US20060255829A1 (en) * | 2005-05-12 | 2006-11-16 | Samsung Electronics Co., Ltd. | Semiconductor memory device having pre-emphasis signal generator |
-
2006
- 2006-08-23 KR KR1020060079933A patent/KR20080017973A/en not_active Application Discontinuation
-
2007
- 2007-08-23 US US11/892,434 patent/US7902872B2/en active Active
Patent Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20020061072A1 (en) | 2000-11-17 | 2002-05-23 | Andrew Pickering | Systems for data transmission |
US6288581B1 (en) | 2001-01-05 | 2001-09-11 | Pericom Semiconductor Corp. | Low-voltage differential-signalling output buffer with pre-emphasis |
US20020135404A1 (en) * | 2001-03-21 | 2002-09-26 | Payne Robert F. | High speed voltage mode differential digital output driver with edge-emphasis and pre-equalization |
US20040124888A1 (en) | 2002-12-23 | 2004-07-01 | Alcatel | Low voltage differential signaling [LVDS] driver with pre-emphasis |
US7126378B2 (en) * | 2003-12-17 | 2006-10-24 | Rambus, Inc. | High speed signaling system with adaptive transmit pre-emphasis |
JP2005217999A (en) | 2004-02-02 | 2005-08-11 | Hitachi Ltd | Digital data transmission circuit |
US20060255829A1 (en) * | 2005-05-12 | 2006-11-16 | Samsung Electronics Co., Ltd. | Semiconductor memory device having pre-emphasis signal generator |
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KR20080017973A (en) | 2008-02-27 |
US20080048720A1 (en) | 2008-02-28 |
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