CN102545884B - Voltage type data transmitter with high-efficiency pre-emphasis balance - Google Patents
Voltage type data transmitter with high-efficiency pre-emphasis balance Download PDFInfo
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- CN102545884B CN102545884B CN201210036315.2A CN201210036315A CN102545884B CN 102545884 B CN102545884 B CN 102545884B CN 201210036315 A CN201210036315 A CN 201210036315A CN 102545884 B CN102545884 B CN 102545884B
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Abstract
The invention discloses a voltage type data transmitter with high-efficiency pre-emphasis balance, which can be used for automatically configuring the weight of driving current between a main transmitting circuit and a pre-emphasis circuit according to the levels of a current position and a previous position for transmitting a data signal, effectively switching off the pre-emphasis circuit during transmission of a signal low-frequency component through a system, overcoming the defect of large energy waste during transmission of the signal low-frequency component with the conventional voltage type data transmitter with the pre-emphasis balance, greatly increasing the efficiency of the transmitter, and saving over 60 percent of power consumption under high pre-emphasis strength. The voltage type data transmitter comprises a main transmitting circuit consisting of a differential driving circuit with an adjustable bias voltage, a pre-emphasis circuit consisting of a differential driving circuit with an adjustable bias current, and a bias circuit which can be used for adaptively configuring the transmitter according to an output amplitude and pre-emphasis strength. The voltage type data transmitter can be applied to various data communication systems, and particularly has the characteristic of high efficiency in high-speed data communication.
Description
Technical field
The invention belongs to the technical field of data communication high-speed interconnect integrated circuit, it is a kind of voltage-type data transmitter with high-effect preemphasis equilibrium, the signal attenuation that compensated high-speed data communication brings because of channel width deficiency effectively, can, for various data communication transmitters or transceiver system, also can use as independent IP.
Background technology
Fig. 1 is a kind of typical high-speed data communication system, and this system is mainly by transmitter 100, transmission medium 105, AC coupled 106a(or direct-current coupling 106b), receiver 108 forms.Transmitting-receiving and the transport process of data are as follows: differential digital signal 109 is driven by transmitter 100, and by the transmission of transmission medium 105, signal arrives receiving terminal and receives and revert to differential digital signal 110 by receiver 108.For reducing the reflection of signal, conventionally can be configured at transmitting terminal, receiving terminal or two ends terminating resistor 107a and the 107b of coupling transmission medium channel impedance simultaneously.The bias potential V of described receiver end connecting resistance 107a and 107b
rXwhen direct-current coupling, can receive fixed potential or unsettled, but must connect fixed potential when AC coupled.Transmission medium 105 can include but not limited to following one or more combination: chip package, printed circuit board, backboard, connector, various types of cables etc.
Quick raising along with data signaling rate, several GHzs (GHz) or tens GHzs have been reached at present, the channel width of transmission medium 105 is significantly less than message transmission rate, and the decay based on signal frequency causing thus can make data integrity be badly damaged, and the error rate improves greatly.For the signal attenuation of compensation in transmission medium 105, adopt preemphasis balancing technique, before signal enters transmission medium 105, it is carried out to preliminary treatment, output difference sub-signal 111, improves its output amplitude 114 for the radio-frequency component in signal, and reduces output amplitude 113 for low-frequency component.Signal is through the transmission of transmission medium 105, and the decay of its radio-frequency component is greater than low-frequency component, and when signal arrives receiving terminal, the amplitude of low-and high-frequency composition reaches unanimity, and reaches balanced, forms the differential input signal 112 of receiving terminal.
The energy that the described voltage-type data transmitter 100 with preemphasis equilibrium can utilize more fully power supply to supply with when the radio-frequency component of output signal, efficiency is very high; But when the low-frequency component of output signal, but wasted a large amount of energy consumptions, efficiency is lower, and along with the raising of preemphasis intensity, efficiency fast-descending, seriously limit the ability of voltage-type data transmitter Circnit Layout preemphasis equilibrium with compensation transmission medium channel width deficiency, hindered this structure in data communication, particularly the extensive use in high-speed data communication field.
Summary of the invention
The present invention is directed to the lower defect of voltage-type transmitter usefulness with preemphasis equilibrium, proposed a kind of novel efficient electric die mould transmitter.Described transmitter is comprised of main transtation mission circuit, preemphasis circuit and biasing circuit, the low-frequency component of main transtation mission circuit transmitted signal, the radio-frequency component of preemphasis circuit transmitted signal together with main transtation mission circuit, biasing circuit provides suitable bias voltage and bias current to main transtation mission circuit and preemphasis circuit.
Described main transtation mission circuit is comprised of three PMOS transistors, three nmos pass transistors and two operational amplifiers.Wherein the transistorized source electrode of a PMOS connects power supply, and grid connects the output of the first operational amplifier, and drain electrode is joined with the transistorized source electrode of the second and the 3rd PMOS, and is connected to the normal phase input end of the first operational amplifier.The first nmos pass transistor source ground, grid is connected to the output of the second operational amplifier, and drain electrode is connected to second and the source electrode of the 3rd nmos pass transistor, and is connected to the normal phase input end of the second operational amplifier.The drain and gate of the 2nd PMOS transistor AND gate the second nmos pass transistor respectively correspondence joins, and the drain and gate of the 3rd PMOS transistor AND gate the 3rd nmos pass transistor respectively correspondence joins.
Set the inverting input bias voltage of the first operational amplifier of described main transtation mission circuit, the negative feedback forming by the first operational amplifier and a PMOS transistor, can form stable high potential at the transistorized source electrode of the second and the 3rd PMOS.Set the inverting input bias voltage of described the second operational amplifier, the negative feedback forming by the second operational amplifier and the first nmos pass transistor, can second and the source electrode of the 3rd nmos pass transistor form stable electronegative potential.Described high potential is identical with the inverting input bias voltage of the first operational amplifier, and described electronegative potential is identical with the inverting input bias voltage of the second operational amplifier.
Described second, third PMOS transistor of described main transtation mission circuit and second, third nmos pass transistor form the circuit structure of differential-input differential output, and described transistorized grid is differential input end, and described transistorized drain terminal is difference output end.
Described preemphasis circuit is comprised of three PMOS transistors and three nmos pass transistors.The transistorized source electrode of the 4th PMOS connects fixedly high potential, and grid connects bias voltage and sets the transistorized offset operation electric current of the 4th PMOS, and its drain electrode is connected to the transistorized source electrode of the 5th and the 6th PMOS.Described the 4th to the 6th PMOS transistor forms differential pair, and when the transistorized grid voltage of the 5th PMOS is during for low conducting, the transistorized electric current of the 4th PMOS flows out through the 5th PMOS transistor; When the transistorized grid voltage of the 6th PMOS is during for low conducting, the transistorized electric current of the 4th PMOS flows out through the 6th PMOS transistor.
The source electrode of the 4th nmos pass transistor of described preemphasis circuit connects fixedly electronegative potential, and grid connects the offset operation electric current that bias voltage is set the 4th nmos pass transistor, and its drain electrode is connected to the 5th and the source electrode of the 6th nmos pass transistor.Described the 4th to the 6th nmos pass transistor forms differential pair, and when the grid voltage of the 5th nmos pass transistor is during for height conducting, the electric current of the 4th nmos pass transistor flows into through the 5th nmos pass transistor; When the grid voltage of the 6th nmos pass transistor is during for height conducting, the electric current of the 4th nmos pass transistor flows into through the 6th nmos pass transistor.
Described the 5th PMOS of described preemphasis circuit and described the 5th nmos pass transistor drain terminal short circuit, and with the 2nd PMOS of described main transtation mission circuit and the drain terminal short circuit of the second nmos pass transistor; Described the 6th PMOS and described the 6th nmos pass transistor drain terminal short circuit, and with the 3rd PMOS of described main transtation mission circuit and the drain terminal short circuit of the 3rd nmos pass transistor.When the low-frequency component of described main transtation mission circuit transmitted signal, the the 5th and the 6th PMOS transistor, the 5th and the 6th nmos pass transistor all turn-off, and the amplitude of output signal is determined by back biased voltage, the described second and the 3rd PMOS transistor, the conducting equivalence pressure drop of the second and the 3rd nmos pass transistor and the output load of described main transtation mission circuit of described first and second operational amplifiers of main transtation mission circuit.When the radio-frequency component of described main transtation mission circuit transmitted signal, the the 5th and the 6th PMOS transistor, the 5th and the 6th nmos pass transistor can be set to respectively conducting or shutoff according to the signal transmitting, by described main transmitter difference output end correspondingly being injected and extracting electric current, improve the output amplitude of high-frequency signal.
Described the 5th PMOS of described preemphasis circuit, described the 5th nmos pass transistor, described the 6th PMOS and described the 6th nmos pass transistor all turn-off when the low-frequency component of main transtation mission circuit output signal, consumed energy is zero in the situation that ignoring transistor leakage, has greatly improved the usefulness of whole transmitter.
Described biasing circuit comprises the 7th and the 8th PMOS transistor, the 7th nmos pass transistor, identical four resistance of the first to the 4th resistance and the 3rd operational amplifier.The transistorized source electrode of the 7th PMOS connects fixedly high potential, grid is connected respectively output and the normal phase input end of the 3rd operational amplifier with draining, described the 7th PMOS transistor drain is sequentially connected in series the described first to the 4th resistance, and the other end of the 4th resistance connects electronegative potential.The electronegative potential that regulates the inverting input biasing of described the 3rd operational amplifier to be connected with the 4th resistance, can set the different operating current of described the 7th PMOS transistor.
The 8th PMOS transistor of described biasing circuit is connected respectively with grid with the transistorized source electrode of the 7th PMOS, forms mirror current source, and its operating current is identical with the 7th PMOS transistor and change thereupon.The source electrode of described the 7th nmos pass transistor connects electronegative potential, drain and gate short circuit transistorized drain electrode is connected with described the 8th PMOS, and the thereupon variation identical with the 8th PMOS transistor of its operating current.
Described the 4th PMOS transistor gate of the transistorized grid of described the 7th PMOS of described biasing circuit and described preemphasis circuit is connected, described the 4th PMOS transistor and described the 7th PMOS transistor form mirror current source, its operating current is identical with the 7th PMOS transistor and change thereupon, further can by dimension scale, zoom in or out image current with the different size of the 7th PMOS transistor by setting the 4th PMOS transistor.Described the 4th nmos pass transistor grid of the grid of described the 7th nmos pass transistor of described biasing circuit and described preemphasis circuit is connected, described the 4th nmos pass transistor and described the 7th nmos pass transistor form mirror current source, its operating current is identical with the 7th nmos pass transistor and change thereupon, further can by dimension scale, zoom in or out image current with the different size of the 7th nmos pass transistor by setting the 4th nmos pass transistor.
Accompanying drawing explanation
Fig. 1 is typical high-speed data communication system.
Fig. 2 is the existing two tap voltage type transmitters with preemphasis equilibrium.
Fig. 3 is the input and output signal waveform of the existing two tap voltage type transmitters with preemphasis equilibrium.
Equivalent electric circuit when Fig. 4 is the existing two tap voltage type transmitter output signal radio-frequency component with preemphasis equilibrium.
Equivalent electric circuit when Fig. 5 is the existing two tap voltage type transmitter output signal low-frequency component with preemphasis equilibrium.
Fig. 6 is the two tap voltage type transmitter architecture figure with high-effect preemphasis equilibrium that the present invention proposes.
Fig. 7 is the equivalent electric circuit of the two tap voltage type transmitters with high-effect preemphasis equilibrium that propose of the present invention.
Fig. 8 is the voltage-type transmitter and the power consumption ratio of existing voltage-type transmitter under different preemphasis intensity that the present invention proposes.
Embodiment
Fig. 2 is the typical structure of the existing two tap voltage type data transmitters 100 with preemphasis equilibrium, a main transtation mission circuit and a preemphasis circuit, consists of, and the circuit structure of many tap voltages type transmitter can simply be expanded based on this.Described main transtation mission circuit comprises MOS transistor 201 to 204, and described preemphasis circuit comprises MOS transistor 205 to 208.IP and IN are the differential input end of transmitter, the conducting resistance of MOS transistor 201 to 208 when conducting must and the impedance matching of transmission medium 105, being set with but being not limited to following method of conducting resistance: regulate MOS transistor raceway groove breadth length ratio, regulate input differential signal V
iPand V
iNamplitude etc.
Fig. 3 is the input and output signal waveform with two tap voltage type transmitters of preemphasis equilibrium.The input differential signal V of described differential input end IP and IN
iPand V
iNas shown in the first row waveform, input signal is " 1,1,1 ,-1 ,-1,1,1,1 ,-1 ,-1 ... ", V
iPand V
iNpostpone to produce the signal waveform V shown in the second row after a bit
iP* Z
-1and V
iN* Z
-1.If V
iPand V
iP* Z
-1be all height, corresponding V
iNand V
iN* Z
-1be all low, described MOS transistor 202,203,205,208 conductings.Due to MOS transistor 203 and 205 contrary for the driving effect of output ON, transistor 202 and 208 contrary for the driving effect of output OP, so output signal V
oPand V
oNamplitude reduce, as 113 of fourth line waveform in Fig. 3; As described signal V
iPand V
iP* Z
-1be all low, corresponding V
iNand V
iN* Z
-1be all when high, similar analysis can draw output signal V
oPand V
oNamplitude also reduce.As described V
iPfor height and V
iP* Z
-1corresponding V on the contrary,
iNfor low and and V
iN* Z
-1when also contrary, MOS transistor 202,203,206,207 conductings, MOS transistor 203 and the 207 driving effects for output signal ON are that homophase is strengthened, and MOS transistor 202 and the 206 driving effects for output signal OP are also that homophase is strengthened, so signal V
oPand V
oNoutput amplitude strengthen, as 114 of fourth line waveform in Fig. 3.
For calculating the existing power consumption with the balanced two tap voltage type data transmitters 100 of preemphasis, circuit diagram need to be equivalent to the resistor network corresponding under different operating condition.As described V
iPand V
iNwhen the current bit of signal is contrary with last bit, transmitter 100 can be equivalent to the resistor network of Fig. 4; As described V
iPand V
iNwhen the current bit of signal is identical with last bit signal, transmitter 100 can be equivalent to the resistor network of Fig. 5.Wherein solid line represents is the equivalent electric circuit being output as in the situation of high level " 1 ", dotted line represents is the equivalent electric circuit being output as in the situation of low level " 1 ", resistance 303 be transmission medium 105 as the equiva lent impedance of load, be output as " 1 " still " 1 " resistance 303 all conducting exist.
Equivalent resistance network when Fig. 5 is the existing two tap voltage type transmitter output signal low-frequency component with preemphasis equilibrium, might as well suppose to be output as the situation of " 1 ".Now MOS transistor 202 and 203 conducting resistance 301 are R
1, MOS transistor 205 and 208 conducting resistance 302 be R
2, transistor 201,204,206 and 207 is closed.R
1and R
2resistance can be by Kirchhoff's current law (KCL) (KCL) and R
1//R
2=R
tsimultaneous is obtained:
, because V
r=A*V
p-p, V
oP-V
oN=V
p-p/ 2, V
oPand V
oNcommon-mode voltage be V
r/ 2, try to achieve
so,,
, calculate
.
Definition transition density (Transition Density, the not identical data bit of present bit and last position accounts for the percentage of whole data volume) is D, the gross power P that transmitter consumes
1can be calculated by following formula
.
Fig. 6 is that the present invention proposes the two tap voltage type transmitter architecture figure with high-effect preemphasis equilibrium, main transtation mission circuit 401, preemphasis circuit 402 and biasing circuit 403, consist of, many tap voltages type data transmitter circuit structure can be expanded and realize by simple structure.
Main transtation mission circuit 401 described in Fig. 6 is comprised of PMOS transistor 406 to 408, nmos pass transistor 413 to 415, operational amplifier 421 and 422.Described main transtation mission circuit 401 is for generation of the low frequency part of signal, the adjusting of the feedback control loop forming by operational amplifier 421 and PMOS transistor 406, V
rHmagnitude of voltage is set as external voltage V
h; The adjusting of the feedback control loop forming by operational amplifier 422 and nmos pass transistor 413, V
rLmagnitude of voltage is set as external voltage V
l.The input signal IP of described main transmitter 401 and IN are differential digital signal, by the control to transistor 407,408,414 and 415, drive difference output OP and ON.The conducting resistance input impedance general and transmission medium 105 of described PMOS transistor 407,408 and nmos pass transistor 414,415 is mated.The input difference impedance of transmission medium 105 can be equivalent to and be connected across between OP and ON and resistance is 2R
tresistance.No matter the output difference sub-signal of OP and ON is high or low, V
rHand V
rLbetween all can be equivalent to total resistance be 4R
tresistance, so V
oP-V
oNthe peak-to-peak value of differential signal be V
h-V
l, the V of fifth line in Fig. 3
oPand V
oNdifferential signal low frequency part amplitude peak-to-peak value is made as V
p-P, can obtain V
h-V
lfor V
p-p.
The fixed potential V of main transtation mission circuit 401 described in Fig. 6
rHand V
rLalso can adopt other circuit structures that can directly or indirectly set, include but not limited to the combination of following one or more methods: directly by V
rHand V
rLtwo nodes are all received fixed potential; V
rHand V
rLone or two connected current biasing circuit of two nodes or the output of voltage offset electric circuit; For stablizing output common mode voltage, at output V
oPand V
oNbetween can be connected in series two resistance, according to the intermediate node of two resistance, regulate bias current or voltage.
In Fig. 6, biasing circuit is comprised of PMOS transistor 404 to 405, nmos pass transistor 412, operational amplifier 420 and resistance 419.The reference voltage V of operational amplifier 420
hby feedback control loop by the drain potential clamper of described PMOS transistor 404 at V
h.The resistance of four resistance 419 is R
tthereby, in transistor 404, produced value for (V
h-V
l)/(4R
t) reference current, i.e. V
p-p/ (4R
t).The grid short circuit of PMOS transistor 405 and described PMOS transistor 404, produces the electric current of supplying with nmos pass transistor 412, and its value is also V
p-p/ (4R
t).In actual design, also can change the resistance of four resistance 419, for example, increase their resistance, can reduce the operating current of PMOS transistor 404 in biasing circuit and 405 to save power consumption.Described four resistance also can be realized with a resistance with equivalent resistance.
In Fig. 6, preemphasis circuit 402 is comprised of PMOS transistor 409 to 411, nmos pass transistor 416 to 418.The grid of PMOS transistor 409 is regulated by the output of operational amplifier 420 in described biasing circuit 403, produces I
bthe electric current of size, the nmos pass transistor 412 in nmos pass transistor 418 and described biasing circuit 403 forms current mirror, obtains I
bthe image current of size.PMOS transistor 410 and 411, nmos pass transistor 416 and 417 are all equivalent to switch, and their conducting resistance is less, are subject to respectively V
pREN_BAR, V
pREP_BAR, V
pREP, V
pRENfour voltage control, V
pREP, V
pRENwaveform as shown in the waveform of Fig. 3 the third line, V wherein
pREPfor
, V
pRENfor
, V
pREP_BARand V
pREN_BARbe respectively V
pREPand V
pRENinversion signal.The difference output end of preemphasis circuit 402 and described main transtation mission circuit 401 difference output end OP and ON short circuit, improve output difference sub-signal amplitude by injecting preemphasis electric current to transmission medium 105, reaches V
p-P* A.
For meeting the requirement of described main transtation mission circuit 401 and biasing circuit 420 DC points, V
bH-V
bLbe at least A* (V
h-V
l), be also A*V
p-p.
Fig. 7 is the equivalent electric circuit of the two tap voltage type transmitters with high-effect preemphasis equilibrium that propose of the present invention, wherein transistor 410,411,416 and 417 is equivalent to respectively switch 507,508,509 to 510, shown in solid line for output high level " 1 " equivalent situation.When being output as the low-frequency component of signal, four switches 507 to 510 of preemphasis circuit 402 all turn-off, so the pressure drop in transmission medium equivalence differential resistor 303 is (V
h-V
l)/2, i.e. V
p-p/ 2; When being output as the radio-frequency component of signal, switch 508 and 509 closures, current source 505 and 506 two ends OP and ON to transmission medium equivalence differential resistor 303 inject respectively or extract electric current out, make V
oP-V
oNoutput amplitude increase and realize the preemphasis to high-frequency signal.
When preemphasis intensity A≤2, V
oP-V
oNoutput peak-to-peak value is A*Vp-p, so have
, by setting, the PMOS transistor 409 of preemphasis circuit 402 and the breadth length ratio of nmos pass transistor 418 are respectively the PMOS transistor 404 of biasing circuit 403 and 2 (A-1) of nmos pass transistor 412 doubly can obtain the bias current I of required current value
b.Concrete mode can for but be not limited to regulate PMOS transistor 409 and nmos pass transistor 418 size, change the number in parallel of PMOS transistor 409 and nmos pass transistor 418, adjust the breadth length ratio etc. of PMOS transistor 404.Total power consumption P
2for
.
When preemphasis intensity A >2, due to V
oP-V
oNbe greater than V
h-V
l, output driving current is provided by preemphasis circuit, V
oP-V
oNoutput peak-to-peak value is A*Vp-p, can calculate I
b=A*V
p-p/ 4R
t, by setting the breadth length ratio of the PMOS transistor 409 of preemphasis circuit 402, be the bias current I that the A of the PMOS transistor 404 of biasing circuit 403 doubly can obtain required current value
b.Concrete mode can for but be not limited to regulate PMOS transistor 409 and nmos pass transistor 418 size, increase the number in parallel of PMOS transistor 409 and nmos pass transistor 418, adjust the breadth length ratio etc. of PMOS transistor 404.Can calculate the gross power P of its consumption thus
2for
.
For comparing voltage-type transmitter of the present invention and the power consumption ratio of existing voltage-type transmitter under different preemphasis intensity, can calculate P
2/ P
1:
.
When assessment data communication system performance, be widely used PRBS pseudo-random binary sequence, the transition density D of PRBS is 0.5, changes preemphasis intensity, can obtain voltage-type transmitter of the present invention shown in Fig. 8 and the power consumption ratio of existing voltage-type transmitter under different preemphasis intensity.Under larger preemphasis strength condition, the present invention can save the power consumption that surpasses 60%, shows dynamical feature.
Claims (6)
1. the voltage-type data transmitter with high-effect preemphasis equilibrium, it is characterized in that: comprise a main transtation mission circuit, one or more preemphasis circuit and biasing circuit, the difference output end of main transtation mission circuit and preemphasis circuit is short circuit respectively, realizes the preemphasis of output signal balanced; Main transtation mission circuit wherein at least comprises first, second, third PMOS transistor and first, second, third nmos pass transistor and first, second operational amplifier; The transistorized source electrode of the one PMOS connects power supply, and grid connects the output of the first operational amplifier, and drain electrode is joined with the transistorized source electrode of the second and the 3rd PMOS, and is connected to the normal phase input end of the first operational amplifier; The first nmos pass transistor source ground, grid is connected to the output of the second operational amplifier, and drain electrode is connected to second and the source electrode of the 3rd nmos pass transistor, and is connected to the normal phase input end of the second operational amplifier; The transistorized source shorted of the second and the 3rd PMOS, second and the source shorted of the 3rd nmos pass transistor, the drain and gate of the 2nd PMOS transistor AND gate the second nmos pass transistor respectively correspondence joins, the drain and gate of the 3rd PMOS transistor AND gate the 3rd nmos pass transistor respectively correspondence joins, and the conducting resistance input impedance equal and transmission medium of the 2nd PMOS transistor, the 3rd PMOS transistor, the second nmos pass transistor, the 3rd nmos pass transistor is mated; Preemphasis circuit wherein at least comprises the 4th, the 5th, the 6th PMOS transistor and the 4th, the 5th, the 6th nmos pass transistor; The 5th is connected with the transistorized source electrode of the 6th PMOS, and the 5th is connected with the source electrode of the 6th nmos pass transistor, and the transistorized drain electrode of the 5th PMOS is connected with the drain electrode of the 5th nmos pass transistor, and the transistorized drain electrode of the 6th PMOS is connected with the drain electrode of the 6th nmos pass transistor; The transistorized source electrode of the 4th PMOS connects fixedly high potential, and grid connects bias voltage, and drain electrode is connected to the transistorized source electrode of the 5th and the 6th PMOS; The source electrode of the 4th nmos pass transistor connects fixedly electronegative potential, and grid connects bias voltage, and drain electrode is connected to the 5th and the source electrode of the 6th nmos pass transistor; Biasing circuit wherein comprises the 7th and the 8th PMOS transistor, the 7th nmos pass transistor, the first resistance, the second resistance, the 3rd resistance, the 4th resistance, the 3rd operational amplifier; The transistorized source electrode of the 7th PMOS connects fixedly high potential, and grid is connected respectively output and the normal phase input end of the 3rd operational amplifier with draining, and drain electrode is sequentially connected in series the described first to the 4th resistance, and the other end of the 4th resistance connects electronegative potential; The 8th PMOS transistor is connected respectively with grid with the transistorized source electrode of the 7th PMOS, and the source electrode of the 7th nmos pass transistor connects electronegative potential, and also transistorized drain electrode is connected drain and gate short circuit with the 8th PMOS; First, second, third, fourth resistance is four identical resistance, the resistance of four resistance and the impedance matching of transmission medium, the transistorized bias current of the 7th PMOS is that the peak-to-peak value of low frequency part amplitude of output difference sub-signal is divided by the differential impedance of the transmission medium of twice; Described the 4th PMOS transistor gate of the transistorized grid of described the 7th PMOS of described biasing circuit and described preemphasis circuit is connected, and described the 4th nmos pass transistor grid of the grid of described the 7th nmos pass transistor of described biasing circuit and described preemphasis circuit is connected.
2. voltage-type data transmitter according to claim 1, is characterized in that, the source electrode of the 2nd PMOS of described main transtation mission circuit is received a high bias potential V
rH, the source electrode of the 2nd NMOS is received a low bias potential V
rL, the production method of high and low bias potential can be below two kinds of methods one of them, or the combination of two kinds of methods: directly by V
rHand V
rLtwo nodes are all received fixed potential; V
rHand V
rLone or two in two nodes is connected to the output of current biasing circuit or voltage offset electric circuit.
3. voltage-type data transmitter according to claim 1, is characterized in that, described main transtation mission circuit passes through at output V
oPand VO
nbetween be connected in series the 5th resistance and the 6th resistance, can regulate the intermediate node of two resistance to regulate bias current or voltage to stablize output common mode voltage.
4. voltage-type data transmitter according to claim 1, it is characterized in that, described preemphasis circuit can increase a PMOS transistor identical with the 4th PMOS transistor, this transistor and the 4th PMOS transistor be respectively the 5th and two branch roads of the 6th PMOS transistor controls electric current is provided; Can increase by one with the identical nmos pass transistor of the 4th nmos pass transistor, this transistor and the 4th nmos pass transistor are respectively two branch roads that the 5th and the 6th nmos pass transistor controls electric current are provided.
5. voltage-type data transmitter according to claim 1, is characterized in that, the transistorized source electrode of the 5th and the 6th PMOS of described preemphasis circuit is high potential biasing V
bH, the 5th and the source electrode of the 6th nmos pass transistor be electronegative potential biasing V
bL, directly by the 5th and the 6th PMOS transistor and the 5th and the turn-on and turn-off of the 6th nmos pass transistor realize the preemphasis of described main transmitter balanced.
6. voltage-type data transmitter according to claim 1, it is characterized in that, the 4th PMOS transistor of described preemphasis circuit and the operating current of the 4th nmos pass transistor are less than or equal at 2 o'clock in preemphasis intensity, are respectively the 2(A-1 of the operating current of the 7th PMOS transistor and the 7th nmos pass transistor in described biasing circuit) doubly; When preemphasis intensity is greater than 2, be respectively the A of the 7th PMOS transistor and the 7th nmos pass transistor operating current in described biasing circuit doubly.
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|---|---|---|---|
| CN201210036315.2A CN102545884B (en) | 2012-02-17 | 2012-02-17 | Voltage type data transmitter with high-efficiency pre-emphasis balance |
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|---|---|---|---|
| CN201210036315.2A CN102545884B (en) | 2012-02-17 | 2012-02-17 | Voltage type data transmitter with high-efficiency pre-emphasis balance |
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| CN105207660B (en) * | 2015-09-11 | 2018-06-19 | 中国科学院微电子研究所 | A kind of differential mode feedback circuit |
| CN105262475A (en) * | 2015-10-22 | 2016-01-20 | 北京大学 | Swing adjustable SST-type data transmitter with pre-emphasis equalization |
| TWI748976B (en) * | 2016-02-02 | 2021-12-11 | 日商新力股份有限公司 | Sending device and communication system |
| TWI722090B (en) * | 2016-02-22 | 2021-03-21 | 日商新力股份有限公司 | Transmission device, transmission method and communication system |
| CN116505933A (en) * | 2023-06-21 | 2023-07-28 | 艾创微(上海)电子科技有限公司 | MOS tube on-resistance matching circuit |
| CN117319125B (en) * | 2023-11-28 | 2024-02-20 | 北京国科天迅科技股份有限公司 | Data transceiving circuit, system and method |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101741360A (en) * | 2008-11-12 | 2010-06-16 | 东部高科股份有限公司 | Differential pre-emphasis driver |
| CN102263575A (en) * | 2010-05-25 | 2011-11-30 | 索尼公司 | Transmitter device, receiver device, transmission method, reception method, and transmitter/receiver device |
| CN202652186U (en) * | 2012-02-17 | 2013-01-02 | 无锡芯骋微电子有限公司 | Voltage type data transmitter with high-efficiency pre-emphasis equalization |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20080017973A (en) * | 2006-08-23 | 2008-02-27 | 삼성전자주식회사 | Data transmitter and method thereof |
| JP5049982B2 (en) * | 2007-02-14 | 2012-10-17 | パナソニック株式会社 | AC coupling interface circuit |
-
2012
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101741360A (en) * | 2008-11-12 | 2010-06-16 | 东部高科股份有限公司 | Differential pre-emphasis driver |
| CN102263575A (en) * | 2010-05-25 | 2011-11-30 | 索尼公司 | Transmitter device, receiver device, transmission method, reception method, and transmitter/receiver device |
| CN202652186U (en) * | 2012-02-17 | 2013-01-02 | 无锡芯骋微电子有限公司 | Voltage type data transmitter with high-efficiency pre-emphasis equalization |
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