JP2019114943A - Transmission circuit and control method of transmission circuit - Google Patents

Abstract

To provide a transmission circuit capable of signal transmission with higher speed and a transmission circuit capable of de-emphasis with higher accuracy.SOLUTION: A transmission circuit of the present invention includes: a current output circuit that is connected in parallel with a termination resistor and controls the magnitude and direction of current flowing through the termination resistor; and a control circuit that generates a first control signal pair and a second control signal pair about which the first control signal pair is logically inverted and delayed on the basis of an input signal. The current output circuit includes a current superposition circuit that is controlled according to the first control signal pair and the second control signal pair and superposes injection current on output current of the current output circuit.SELECTED DRAWING: Figure 2

Description

  The present invention relates to a transmission circuit and a control method of the transmission circuit, and more particularly to a transmission circuit used for high-speed serial transmission and a control method of the transmission circuit.

  Among transmission and reception technologies used for high-speed serial transmission, for example, standards such as Low Voltage Differential Signaling (LVDS) and mini-LVDS are adopted. LVDS is a digital wired transmission technology for short distances standardized in 1994 by the American National Standards Institute (ANSI). The transceiver circuit according to LVDS is a differential signal system using a pair of transmission paths, specifically, the transmitter transmits differential signals having two different potentials, and the receiver transmits the two signals. The logic state of the signal is determined by comparing the potential differences of Thus, the transceiver circuit according to LVDS can transmit differential signals at high speed with small amplitude and low power consumption. Also, mini-LVDS is a standard derived from LVDS, and has a smaller voltage amplitude than LVDS, thereby reducing power consumption.

  As a technique used for transmission and reception according to LVDS, a signal adjustment technique called pre-emphasis or de-emphasis that compensates for attenuation characteristics of a transmission line is known for speeding up and increasing a transmission line. Both pre-emphasis and de-emphasis are used to compensate for high frequency components that are attenuated in the transmission path acting as a low pass filter, and are signal conditioning techniques performed on the transmission side. Both pre-emphasis and de-emphasis are common in adjusting the output voltage such that the voltage of the high frequency component of the signal is relatively larger than the voltage of the low frequency component, but the method is different. Specifically, pre-emphasis amplifies and transmits the voltage of the high frequency component of the signal, while de-emphasis attenuates and transmits the voltage of the low frequency component.

  The following Patent Documents 1 to 5 disclose techniques related to pre-emphasis. Specifically, Patent Document 1 discloses a pre-emphasis circuit that performs pre-emphasis at the rise and fall of a transmission signal using a delay signal obtained by delaying an output signal and a signal obtained by inverting the delay signal. Do.

  Patent Document 2 discloses a pre-emphasis circuit that performs pre-emphasis at the rise and fall of a signal using a buffer circuit for pre-emphasis.

  Further, Patent Document 3 includes a second transconductance amplifier for converting a differential input signal through a band pass filter circuit into a differential current output, and the second transconductance amplifier outputs a second differential current output. Disclosed is a pre-emphasis circuit that adds differential current outputs of a transconductance amplifier to perform pre-emphasis.

  Further, Patent Document 4 discloses an emphasis signal generation circuit which performs pre-emphasis by adding and subtracting an emphasis component signal obtained by delaying an input signal and adjusting an amplitude to and from an output signal at a predetermined ratio.

  Patent Document 5 discloses a pre-emphasis circuit including a boost pull-up circuit for precharging a PMOS transistor of an inverter output circuit and a boost pull-down circuit for precharging an NMOS transistor of the inverter output circuit.

JP, 2004-312614, A Unexamined-Japanese-Patent No. 2006-311446 JP, 2009-147512, A JP, 2012-104953, A Japanese Patent Application Publication No. 2014-526206

  Since the pre-emphasis amplifies the voltage of the high frequency component of the signal and transmits it, the voltage amplitude of the output signal becomes large, and it takes time for signal transition by that much, so it is low in realizing higher speed transmission. De-emphasis which attenuates and transmits the voltage of the frequency component is more suitable.

  However, as the demand for faster signal transmission is increasing, delay in signal transition is also becoming a problem in de-emphasis.

  The present invention has been made in view of such circumstances, and an object thereof is to provide a transmission circuit capable of faster signal transmission.

  Another object of the present invention is to provide a transmitter circuit capable of higher precision de-emphasis.

  The present invention for solving the above-mentioned problems includes the invention-specifying matters or technical features shown below.

  That is, according to one aspect of the present invention, there is provided a current output circuit connected in parallel to a termination resistor and controlling the magnitude and direction of the current flowing in the termination resistor, and a first control signal pair and the above based on an input signal. And a control circuit that generates a second control signal pair obtained by inverting and delaying the first control signal pair. The current output circuit includes a current superposition circuit controlled according to the first control signal pair and the second control signal pair and superposing an injection current on the output current of the current output circuit.

  In the output current of the current output circuit, the response of signal transition is improved by superimposing the injection current. Therefore, by superimposing the injection current on the output current of the current output circuit at the timing when the delay of the signal transition may occur in the de-emphasis, the deterioration of the output signal waveform due to the delay of the signal transition can be reduced. This enables faster signal transmission and more accurate de-emphasis.

  The current output circuit is connected in parallel to a termination resistor, supplies a predetermined current to the termination resistor, and controls the direction of the current according to the first control signal pair, and the termination resistor. And a second driver circuit connected in parallel and supplying a predetermined current to the termination resistor and controlling the direction of the current according to the second control signal pair. The first driver circuit includes a first differential circuit, a first constant current circuit for controlling a constant current flowing from a power supply to the first differential circuit, and a ground from the first differential circuit. And second constant current circuit for constant current control of the current flowing therethrough. The current superposition circuit includes a first injection circuit that forms a current path in parallel with the first constant current circuit, and a second injection circuit that forms a current path in parallel with the second constant current circuit. May be included.

  The current flowing from the power supply to the first differential circuit is the current flowing through the first injection circuit current path through the constant current flowing through the first constant current circuit while the current path of the first injection circuit is configured. Add and increase. Similarly, the current flowing from the first differential circuit to the ground changes the current path of the second injection circuit to the constant current flowing through the second constant current circuit while the current path of the second injection circuit is configured. The flowing current is added and increased. That is, by forming another current path in parallel in the constant current path by the first and second injection circuits, the output current of the first differential circuit is increased during that time, and the rise response of the signal transition is improved. improves. Therefore, by configuring the current paths of the first and second injection circuits at timing when the delay of the rising of the signal transition may occur in the de-emphasis, the deterioration of the output signal waveform due to the delay of the rising of the signal transition is reduced. be able to. This enables faster signal transmission and more accurate de-emphasis.

  The second driver circuit includes a second differential circuit, a third constant current circuit that performs constant current control on a current flowing from the power supply to the second differential circuit, and the second differential circuit. A fourth constant current circuit for constant current control of the current flowing to the ground, a third injection circuit for forming a current path in parallel with the third constant current circuit, and a fourth constant current circuit in parallel And a fourth injection circuit forming a current path.

  The current flowing from the power supply to the second differential circuit is the current flowing through the third injection circuit in the constant current flowing through the third constant current circuit while the current path of the third injection circuit is configured. Add and increase. Similarly, the current flowing from the second differential circuit to the ground changes the current path of the fourth injection circuit to the constant current flowing through the fourth constant current circuit while the current path of the fourth injection circuit is configured. The flowing current is added and increased. That is, by forming another current path in parallel in the constant current path by the third and fourth injection circuits, the output current of the second differential circuit also increases during that time, and the rise response of the signal transition is achieved. Will be further improved. Therefore, by further configuring the current paths of the third and fourth injection circuits at the timing at which the delay of the rising of the signal transition may occur in the de-emphasis, the deterioration of the output signal waveform due to the delay of the rising of the signal transition is further added. It can be reduced.

  The control circuit is operated for a predetermined time from the timing when the direction of the current flowing from the first driver circuit to the termination resistor and the direction of the current flowing from the second driver circuit to the termination resistor switch in the same direction from the opposite direction. The current paths of the first to fourth injection circuits may be configured.

  This timing changes from a relatively small amplitude of the output voltage (voltage of the termination resistor) (a state in which de-emphasis is performed) to a relatively large state (a state in which de-emphasis is not performed). Because of this, it is likely to cause a delay in the rising of the signal transition. Therefore, by forming the current paths of the first to fourth injection circuits for a predetermined time from this timing, the deterioration of the output signal waveform due to the delay in the rising of the signal transition can be accurately reduced.

  The control circuit may control the first to fourth injection circuits based on the first control signal pair and the second control signal pair.

  As a result, it becomes possible to easily configure the current paths of the first to fourth injection circuits at proper timing.

  The control circuit controls a first injection control circuit that controls the first and third injection circuits based on the first control signal pair and the second control signal pair, and the first control signal. And a second injection control circuit that controls the second and fourth injection circuits based on the pair and the second control signal pair.

  That is, the injection circuit (first and third injection circuits) on the power supply side and the injection circuit (second and fourth injection circuits) on the ground side may be controlled by separate injection control circuits. As a result, even when the injection circuit on the power supply side and the injection circuit on the ground side have different circuit configurations, the timing of injection control can be easily made to coincide with each other, so that the flexibility of the circuit configuration can be further improved.

  Each of the first to fourth injection circuits may include a plurality of current paths having different current values.

  As a result, the current value of the current path configured by the first to fourth injection circuits can be adjusted, so that more accurate injection control becomes possible.

  The current superposition circuit constitutes a fifth injection circuit that constitutes a current path from the output of the first constant current circuit to the ground, and a current path from the output of the second constant current circuit to the ground And the sixth injection circuit.

  The current flowing from the power supply to the first differential circuit is the current flowing through the first constant current circuit from the constant current flowing through the first constant current circuit to the current path flowing through the fifth injection circuit while the current path of the fifth injection circuit is configured. It is subtracted and decreased. Similarly, the current flowing from the first differential circuit to the ground corresponds to the current path from the constant current flowing through the second constant current circuit to the current path from the sixth injection circuit while the current path of the sixth injection circuit is configured. The flowing current is subtracted and reduced. That is, by forming the current paths of the fifth and sixth injection circuits, the output current of the first differential circuit is reduced during that time, and the fall response of the signal transition is improved. Therefore, by forming the current paths of the fifth and sixth injection circuits at the timing when the delay of the fall of the signal transition may occur in the de-emphasis, the deterioration of the output signal waveform due to the delay of the fall of the signal transition is realized. It can be reduced. This enables faster signal transmission and more accurate de-emphasis.

  The current superposition circuit constitutes a seventh injection circuit that constitutes a current path from the power supply to the input of the third constant current circuit, and a current path from the power supply to the input of the fourth constant current circuit And an eighth injection circuit.

  The current flowing from the power supply to the second differential circuit is the current flowing through the third constant current circuit from the constant current flowing through the third constant current circuit to the current path flowing through the seventh injection circuit while the current path of the seventh injection circuit is configured. It is subtracted and decreased. Similarly, the current flowing from the second differential circuit to the ground corresponds to the current path from the constant current flowing through the fourth constant current circuit to the current path from the eighth injection circuit while the current path of the eighth injection circuit is configured. The flowing current is subtracted and reduced. That is, by further configuring the current paths of the seventh and eighth injection circuits, the output current of the second differential circuit is also reduced during that time, and the fall response of the signal transition is further improved. Therefore, by further configuring the current paths of the seventh and eighth injection circuits at the timing at which the delay of the falling of the signal transition may occur in the de-emphasis, the deterioration of the output signal waveform due to the delay of the falling of the signal transition. Can be further reduced.

  The control circuit is operated for a predetermined time from the timing when the direction of the current flowing from the first driver circuit to the termination resistor and the direction of the current flowing from the second driver circuit to the termination resistor switch from the same direction to the opposite direction. The current paths of the fifth to eighth injection circuits may be configured.

  This timing is the timing at which the amplitude of the output voltage (the voltage of the termination resistor) changes from a relatively large state (state without de-emphasis) to a relatively small state (state with de-emphasis) Therefore, the fall of the signal transition is likely to be delayed. Therefore, by forming the current paths of the fifth to eighth injection circuits for a predetermined time from this timing, the deterioration of the output signal waveform due to the delay of the falling of the signal transition can be accurately reduced.

  The control circuit may be configured to control the fifth to eighth injection circuits based on the first control signal pair and the second control signal pair.

  As a result, it becomes possible to easily configure the current paths of the fifth to eighth injection circuits at appropriate timing.

  A third injection control circuit for controlling the fifth and seventh injection circuits based on the first control signal pair and the second control signal pair; and the first control signal. And a fourth injection control circuit that controls the sixth and eighth injection circuits based on the pair and the second control signal pair.

  That is, the injection circuit (fifth and seventh injection circuits) on the power supply side and the injection circuit (sixth and eighth injection circuits) on the ground side may be controlled by separate injection control circuits. As a result, even when the injection circuit on the power supply side and the injection circuit on the ground side have different circuit configurations, the timing of injection control can be easily made to coincide with each other, so that the flexibility of the circuit configuration can be further improved.

  Each of the fifth to eighth injection circuits may include a plurality of current paths having different current values.

  As a result, the current value of the current path configured by the fifth to eighth injection circuits can be adjusted, so that more accurate injection control becomes possible.

  The control circuit may delay the timing of outputting the first control signal pair and the second control signal pair to the first driver circuit and the second driver circuit.

  Thereby, if the timings when the current paths of the first to fourth injection circuits are formed do not get in time with the proper timing due to the delay time generated in the logical operation circuit or the like that generates the injection control signal pair, It is possible to delay the operation timing of the first driver circuit and the second driver circuit to match the timing.

  The first differential circuit and the second differential circuit may be differential circuits of complementary outputs. The first control signal pair includes the input signal and a signal obtained by logically inverting the input signal, and the second control signal pair logically inverts the input signal and the input signal, and It may include a delayed signal.

  Thereby, a faster transmission circuit can be provided.

  Furthermore, according to another aspect of the present invention, there is provided a control method of a transmitter circuit including a current output circuit connected in parallel to a termination resistor and controlling the magnitude and direction of a current flowing in the termination resistor, And generating a second control signal pair that is obtained by inverting and delaying the first control signal pair and the first control signal pair, and according to the first control signal pair and the second control signal pair, A control method of a transmission circuit, which controls the current output circuit and superposes an injection current on the output current of the current output circuit.

  In the output current of the current output circuit, the response of signal transition is improved by superimposing the injection current. Therefore, by superimposing the injection current on the output current of the current output circuit at the timing when the delay of the signal transition may occur in the de-emphasis, the deterioration of the output signal waveform due to the delay of the signal transition can be reduced. This enables faster signal transmission and more accurate de-emphasis.

  According to the present invention, it is possible to provide a transmission circuit capable of faster signal transmission.

  Further, according to the present invention, it is possible to provide a transmitting circuit capable of higher precision de-emphasis.

It is a block diagram showing composition of a transmitting and receiving system concerning the present invention. It is the circuit diagram which showed the circuit structure of the transmitter which concerns on this invention. FIG. 6 is a circuit diagram showing an example of the operating state of the transmitter according to the present invention, showing the operating state when the values of control signals INP and INN_1UI are 0 and the values of control signals INN and INP_1UI are 1. . FIG. 5 is a circuit diagram showing an example of the operating state of the transmitter according to the present invention, showing the operating state when the values of control signals INP and INP_1UI are 0 and the values of control signals INN and INN_1UI are 1. . FIG. 8 is a circuit diagram showing an example of the operating state of the transmitter according to the present invention, illustrating the operating state when the values of control signals INN and INN_1UI are 0 and the values of control signals INP and INP_1UI are 1. . FIG. 5 is a circuit diagram showing an example of the operating state of the transmitter according to the present invention, showing the operating state when the values of control signals INN and INP_1UI are 0 and the values of control signals INP and INN_1UI are 1. . It is the timing chart which showed the operation of the transmitter concerning the present invention. FIG. 2 is a circuit diagram showing a configuration of a first injection control circuit. It is the timing chart which showed the operation of the 1st injection control circuit. FIG. 6 is a circuit diagram showing a configuration of a second injection control circuit. It is the timing chart which showed the operation of the 2nd injection control circuit. It is a timing chart showing the output voltage of a transmitter, and shows the output voltage when not performing injection control. It is a timing chart which showed the output voltage of a transmitter, and shows the output voltage in the case of performing injection control. It illustrates the simulation result of the output voltage waveform of the transmitter. FIG. 6 is a circuit diagram showing another embodiment of the circuit configuration of the transmitter according to the present invention. It is a circuit diagram showing the composition of the 3rd injection control circuit. It is the timing chart which showed the operation of the 3rd injection control circuit. It is a circuit diagram showing the composition of the 4th injection control circuit. 14 is a timing chart showing the operation of the fourth injection control circuit.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. However, the embodiments described below are merely examples, and there is no intention to exclude the application of various modifications and techniques not explicitly stated below. The present invention can be implemented with various modifications (for example, combining the respective embodiments) without departing from the scope of the present invention. In the following description of the drawings, the same or similar parts are denoted by the same or similar reference numerals. The drawings are schematic and do not necessarily match the actual dimensions, ratios, etc. There may be parts where the dimensional relationships and proportions differ among the drawings.

  The configuration of the transmission / reception circuit according to the present invention will be described with reference to FIG.

  FIG. 1 is a block diagram showing the configuration of a transmission / reception system according to the present invention. One embodiment of a transmitting and receiving system according to the present invention is a transmitting and receiving system for transmitting and receiving signals by differential signals in accordance with the LVDS standard, and includes a transmitter 100 and a receiver 200.

  The transmitter 100 includes a driver unit 10 and a transmission side termination resistor RT1. The transmission side termination resistor RT1 is, for example, a 100Ω resistor. The transmission side termination resistor RT1 may be a variable resistor including a ladder resistor or the like. One end of the transmission side termination resistor RT1 is connected to the output terminal OUTP, and the other end is connected to the output terminal OUTN. A pair of output signal lines of the driver unit 10 are connected to both ends of the transmission side termination resistor RT1.

  The receiver 200 includes input terminals IN1 and IN2 and a reception-side termination resistor RT2 connected between the input terminal IN1 and the input terminal IN2. The reception side termination resistor RT2 is, for example, a 100 Ω resistor. The receiving side termination resistor RT2 may be a variable resistor. The input terminals IN1 and IN2 are respectively connected to the output terminals OUTP and OUTN of the transmitter 100 through a cable or the like. The reception side termination resistor RT2 constitutes a termination resistor RT which is a parallel combined resistance with the transmission side termination resistor RT1 of the driver unit 10. The receiver 200 can use a known one, and therefore illustration and description of its specific circuit configuration will be omitted.

  FIG. 2 is a circuit diagram showing a circuit configuration of the transmitter 100 according to the present invention.

  The transmitter 100 as a “transmission circuit” according to the present invention includes a driver unit 10, a bias circuit 20, and a control circuit 30.

  The driver unit 10 as a "current output circuit" is a circuit that controls the magnitude and direction of the current flowing through the termination resistor RT, and includes a main driver unit 10m and an emphasis driver unit 10e.

  The bias circuit 20 as a "constant current control circuit" is a circuit that performs constant current control of the output current of each of the main driver unit 10m and the emphasis driver unit 10e. Since the bias circuit 20 can suppress the variation of the output current of each of the main driver unit 10m and the emphasis driver unit 10e, the variation of the voltage amplitude of the output signal due to the variation of the output current can be reduced.

  The control circuit 30 is, for example, a known microcomputer control circuit, and controls the main driver unit 10m, the emphasis driver unit 10e, and the bias circuit 20 based on an input signal. More specifically, control circuit 30 delays control signals INP and INN as a "first control signal pair" and a "second control signal pair" delayed based on the input signal. Control signals INP_1UI and INN_1UI as a control signal pair are generated and output. The control signal INP is an input signal, and the control signal INN is a signal obtained by logically inverting the input signal. The control signal INP_1UI is a signal obtained by delaying the input signal, and the control signal INN_1UI is a signal obtained by delaying the input signal. Although the delay amount of the control signals INP_1UI and INN_1UI is 1 UI (Unit Interval) in this embodiment, it is not particularly limited to this.

  Two resistors R1 and R2 are connected in parallel to the termination resistor RT. More specifically, one end of the resistor R1 is connected to one end of the termination resistor RT, the other end of the resistor R1 is connected to one end of the resistor R2, and the other end of the resistor R2 is connected to the other end of the termination resistor RT . The resistances of the resistors R1 and R2 are preferably 10 kΩ, for example, which are sufficiently larger than the resistances of the transmission end resistor RT1 and the reception end resistor RT2. Further, the resistance values of the resistors R1 and R2 may be the same resistance value or different resistance values.

  The main driver unit 10m as a "first driver circuit" is a circuit connected in parallel to the termination resistor RT and supplying a predetermined current to the termination resistor RT and controlling the direction of the current according to the control signals INP and INN. .

  The main driver unit 10m is, for example, a constant current differential circuit of complementary outputs, and includes eight transistors Pm1 to Pm4 and Nm1 to Nm4 and a comparator 11. The transistors Pm1 to Pm4 are P-type MOS field effect transistors. The transistors Nm1 to Nm4 are N-type MOS field effect transistors. The comparator 11 may be, for example, an OTA (operational transconductor amplifier).

  The transistor Pm1 has a source connected to the power supply, a drain connected to the node PTAIL, and a gate to which a constant current control signal PBIAS output from the bias circuit 20 is input.

  The source of the transistor Pm2 is connected to the node PTAIL, and the drain is connected to the drain of the transistor Nm2. The source of the transistor Nm2 is connected to the node NTAIL. The connection point between the drain of the transistor Pm2 and the drain of the transistor Nm2 is connected to one end of the termination resistor RT. The control signal INP is input to the gates of the transistors Pm2 and Nm2.

  The source of the transistor Pm3 is connected to the node PTAIL, and the drain is connected to the drain of the transistor Nm3. The source of the transistor Nm3 is connected to the node NTAIL. The connection point between the drain of the transistor Pm3 and the drain of the transistor Nm3 is connected to the other end of the termination resistor RT. The control signal INN is input to the gates of the transistors Pm3 and Nm3.

  The transistor Nm1 has a drain connected to the node NTAIL, a source connected to the ground, and a gate to which the reference potential control signal NBIAS output from the comparator 11 is input. The non-inverted input of the comparator 11 is connected to the connection point of the resistor R1 and the resistor R2, and the reference voltage VOC is input to the inverted input of the comparator 11. The comparator 11 compares the voltage at the connection point between the resistor R1 and the resistor R2 with the reference voltage VOC, and outputs a reference potential control signal NBIAS according to the difference.

  The transistor Pm4 has a source connected to the power supply, a drain connected to the node PTAIL, and a gate to which the injection control signal INJ_P output from the control circuit 30 is input. The transistor Nm4 has a drain connected to the node NTAIL, a source connected to the ground, and a gate to which an injection control signal INJ_N output from the control circuit 30 is input.

  The emphasis driver unit 10e as a "second driver circuit" is a circuit connected in parallel to the termination resistor RT and supplying a predetermined current to the termination resistor RT and controlling the direction of the current according to the control signals INP_1UI and INN_1UI. .

  The emphasis driver unit 10 e is, for example, a constant current differential circuit of complementary output, and includes eight transistors Pe 1 to Pe 4 and Ne 1 to Ne 4 and a comparator 11. The transistors Pe1 to Pe4 are P-type MOS field effect transistors. The transistors Ne1 to Ne4 are N-type MOS field effect transistors.

  The transistor Pe1 has a source connected to the power supply, a drain connected to the node PTAIL_1UI, and a gate to which a constant current control signal PBIAS output from the bias circuit 20 is input.

  The source of the transistor Pe2 is connected to the node PTAIL_1UI, and the drain is connected to the drain of the transistor Ne2. The source of the transistor Ne2 is connected to the node NTAIL_1UI. The connection point between the drain of the transistor Pe2 and the drain of the transistor Ne2 is connected to one end of the termination resistor RT. The control signal INN_1UI is input to the gates of the transistors Pe2 and Ne2.

  The source of the transistor Pe3 is connected to the node PTAIL_1UI, and the drain is connected to the drain of the transistor Ne3. The source of the transistor Ne3 is connected to the node NTAIL_1UI. The connection point between the drain of the transistor Pe3 and the drain of the transistor Ne3 is connected to the other end of the termination resistor RT. The control signal INP_1UI is input to the gates of the transistors Pe3 and Ne3.

  The transistor Ne1 has a drain connected to the node NTAIL_1UI, a source connected to the ground, and a gate to which the reference potential control signal NBIAS output from the comparator 11 is input. The non-inverted input of the comparator 11 is connected to the connection point of the resistor R1 and the resistor R2, and the reference voltage VOC is input to the inverted input of the comparator 11. The comparator 11 compares the voltage at the connection point between the resistor R1 and the resistor R2 with the reference voltage VOC, and outputs a reference potential control signal NBIAS according to the difference.

  The transistor Pe4 has a source connected to the power supply, a drain connected to the node PTAIL_1UI, and a gate to which an injection control signal INJ_P output from the control circuit 30 is input. The transistor Ne4 has a drain connected to the node NTAIL_1UI, a source connected to the ground, and a gate to which the injection control signal INJ_N output from the control circuit 30 is input.

  The output current of main driver unit 10m is a constant current by transistor Pm1 (first constant current circuit) operating according to constant current control signal PBIAS, and transistor Nm1 (second constant current circuit) operating according to reference potential control signal NBIAS The control is performed to obtain a predetermined current. Similarly, the output current of the emphasis driver unit 10e is a transistor Pe1 (third constant current circuit) operating according to a constant current control signal PBIAS, and a transistor Ne1 (fourth constant current circuit) operating according to a reference potential control signal NBIAS. It is controlled to become a predetermined current by the constant current control by.

  The transistor Pm4 as the “first injection circuit” configures a current path in parallel with the transistor Pm1 in accordance with the injection control signal INJ_P. The transistor Nm4 as the “second injection circuit” configures a current path in parallel with the transistor Nm1 in accordance with the injection control signal INJ_N. The transistor Pe4 as the "third injection circuit" configures a current path in parallel with the transistor Pe1 in accordance with the injection control signal INJ_P. The transistor Ne4 as the "fourth injection circuit" forms a current path in parallel with the transistor Ne1 in accordance with the injection control signal INJ_N.

  3 to 6 are circuit diagrams showing an example of the operation state of the transmitter 100 according to the present invention.

  FIG. 3 shows the operating state when the values of the control signals INP and INN_1UI are 0 (voltage is low) and the values of the control signals INN and INP_1UI are 1 (voltage is high).

  In this operating state, in the main driver unit 10m, the transistors Pm2 and Nm3 are turned on, and the transistors Pm3 and Nm2 are turned off. Thereby, the output current Imain of the main driver unit 10m flows in the forward direction from the transistor Pm1 to the termination resistance RT through the transistor Pm2, and flows from the termination resistance RT to the transistor Nm1 through the transistor Nm3. Further, in the emphasis driver unit 10e, the transistors Pe2 and Ne3 are turned on, and the transistors Pe3 and Ne2 are turned off. Thereby, the output current Iemp of the emphasis driver unit 10e flows from the transistor Pe1 through the transistor Pe2 in the forward direction to the termination resistor RT, and from the termination resistor RT through the transistor Ne3 to the transistor Ne1.

  Therefore, in the operating state shown in FIG. 3, the direction in which the output current Imain flows in the termination resistance RT and the direction in which the output current Iemp flows in the termination resistance RT are both the same in the forward direction. A forward current in which the output current Iemp is added to Imain flows. Therefore, the voltage of the termination resistor RT is a forward voltage of a value obtained by multiplying the output current Imain by the output current Iemp and the resistance value of the termination resistor RT.

  FIG. 4 shows an operation state when the values of the control signals INP and INP_1UI are 0 and the values of the control signals INN and INN_1UI are 1.

  In this operating state, in the main driver unit 10m, the transistors Pm2 and Nm3 are turned on, and the transistors Pm3 and Nm2 are turned off. Thereby, the output current Imain of the main driver unit 10m flows in the forward direction from the transistor Pm1 to the termination resistance RT through the transistor Pm2, and flows from the termination resistance RT to the transistor Nm1 through the transistor Nm3. On the other hand, in the emphasis driver unit 10e, the transistors Pe3 and Ne2 are turned on, and the transistors Pe2 and Ne3 are turned off. Thereby, the output current Iemp of the emphasis driver unit 10e flows from the transistor Pe1 through the transistor Pe3 in the reverse direction to the termination resistor RT, and from the termination resistor RT to the transistor Ne1 through the transistor Ne2.

  Therefore, in the operating state shown in FIG. 4, the direction in which the output current Imain flows in the termination resistance RT is forward, and the direction in which the output current Iemp flows in the termination resistance RT is opposite and opposite to each other. Is a forward current obtained by subtracting the output current Iemp from the output current Imain. Therefore, the voltage of the termination resistor RT is a voltage obtained by multiplying the current value obtained by subtracting the output current Iemp from the output current Imain by the resistance value of the termination resistor RT.

  FIG. 5 shows an operation state when the values of the control signals INN and INN_1UI are 0 and the values of the control signals INP and INP_1UI are 1.

  In this operating state, in the main driver unit 10m, the transistors Pm3 and Nm2 are turned on, and the transistors Pm2 and Nm3 are turned off. Thereby, the output current Imain of the main driver unit 10m flows from the transistor Pm1 through the transistor Pm3 in the reverse direction to the termination resistor RT, and from the termination resistor RT to the transistor Nm1 through the transistor Nm2. On the other hand, in the emphasis driver unit 10e, the transistors Pe2 and Ne3 are turned on, and the transistors Pe3 and Ne2 are turned off. Thereby, the output current Iemp of the emphasis driver unit 10e flows from the transistor Pe1 through the transistor Pe2 in the forward direction to the termination resistor RT, and from the termination resistor RT through the transistor Ne3 to the transistor Ne1.

  Therefore, in the operating state shown in FIG. 5, the direction in which the output current Imain flows in the termination resistance RT is reverse, and the direction in which the output current Iemp flows in the termination resistance RT is opposite, and the termination resistance RT Is a reverse current obtained by subtracting the output current Iemp from the output current Imain. Therefore, the voltage of the termination resistor RT is a reverse voltage of a value obtained by multiplying the current value obtained by subtracting the output current Iemp from the output current Imain by the resistance value of the termination resistor RT.

  FIG. 6 shows an operation state when the values of the control signals INN and INP_1UI are 0 and the values of the control signals INP and INN_1UI are 1.

  In this operating state, in the main driver unit 10m, the transistors Pm3 and Nm2 are turned on, and the transistors Pm2 and Nm3 are turned off. Thereby, the output current Imain of the main driver unit 10m flows from the transistor Pm1 through the transistor Pm3 in the reverse direction to the termination resistor RT, and from the termination resistor RT to the transistor Nm1 through the transistor Nm2. Further, in the emphasis driver unit 10e, the transistors Pe3 and Ne2 are turned on, and the transistors Pe2 and Ne3 are turned off. Thereby, the output current Iemp of the emphasis driver unit 10e flows from the transistor Pe1 through the transistor Pe3 in the reverse direction to the termination resistor RT, and from the termination resistor RT to the transistor Ne1 through the transistor Ne2.

  Therefore, in the operating state shown in FIG. 6, the direction in which the output current Imain flows in the termination resistance RT and the direction in which the output current Iemp flows in the termination resistance RT are the same in opposite directions, and the output current is A reverse current in which the output current Iemp is added to Imain flows. Therefore, the voltage of the termination resistor RT is a reverse voltage of a value obtained by multiplying the output current Imain by the output current Iemp and the resistance value of the termination resistor RT.

  FIG. 7 is a timing chart showing the operation of the transmitter 100 according to the present invention.

  At timing (1 UI Transition) at which the input signal transitions for each UI, the control signal INP and the control signal INN_1UI have the same logic, and the control signal INN and the control signal INP_1UI have the same logic (timing T1 to T2 and timing T4 or later). At this timing, as described above, the output current Imain of the main driver unit 10m and the output current Iemp of the emphasis driver unit 10e are in the same direction, so the voltage VOD of the termination resistor RT (output terminal OUTP and output terminal OUTN Voltage) becomes a relatively high voltage.

  On the other hand, at the timing (timing T2 to T4) at which the input signal has the same continuous bit pattern (CID: Consecutive Identical Digits), the logic after the second bit (timing T3 to T4), the control signal INP and the control signal INN_1UI are different. The control signal INN and the control signal INP_1UI have different logic. At this timing, as described above, the direction of the output current Imain of the main driver unit 10m and the direction of the output current Iemp of the emphasis driver unit 10e are opposite to each other, so the voltage VOD of the termination resistor RT is relatively low. Become.

  That is, when the input signal has the same continuous bit pattern, a de-emphasis effect in which the voltage VOD of the termination resistor RT is attenuated from the second bit onward is obtained.

  Further, the magnitude of the voltage VOD of the termination resistor RT changes depending on whether the output current Iemp of the emphasis driver unit 10e is added to or subtracted from the output current Imain of the main driver unit 10m. Therefore, the output current Imain of the main driver unit 10m and the output current Iemp of the emphasis driver unit 10e do not change even when the control signal INP and the control signal INN_1UI have the same logic or different logic. The timings at which the control signal INN and the control signal INP_1UI have the same logic or the timings at which they have different logic do not change. Therefore, since the power consumption of the transmitter 100 is always constant, it is possible to perform de-emphasis control with very little fluctuation of the power consumption.

  FIG. 8 is a circuit diagram showing the configuration of the first injection control circuit 40. As shown in FIG.

  The control circuit 30 generates an injection control signal INJ_P based on the control signals INP and INN_1UI, and controls a transistor Pm4 (first injection circuit) and a transistor Pe4 (third injection circuit). Including 40.

  The first injection control circuit 40 includes an exclusive OR gate 41, a selector 42, five NOT gates 43 to 47, and a NAND gate 48.

  The control signal INP and INN_1UI are input to the exclusive OR gate 41, and the output is connected to the selection signal input S of the selector 42. The selector 42 receives the low level (ground potential) signal L and the high level (power supply voltage level) signal H, and selectively outputs either the signal L or H according to the potential of the selection signal input S. More specifically, the output of the selector 42 is high when the selection signal input S is low, and is low when the selection signal input is high.

  The NOT gate 43 has an input connected to the output of the selector 42 and an output connected to the input of the NOT gate 44. The output of NOT gate 44 is connected to the input of NOT gate 45. The NOT gates 43 to 45 are delay circuits provided to obtain a signal obtained by delaying the output signal of the selector 42, and the delay time is determined according to the number of connection stages (odd stages) of the NOT gate.

  The NAND gate 48 receives the output signal of the selector 42 and the output signal of the NOT gate 45, and the output is connected to the input of the NOT gate 46. The output of NOT gate 46 is connected to the input of NOT gate 47. The output signal of the NOT gate 47 is the injection control signal INJ_P. The NOT gates 46 and 47 mainly function as buffers and are not necessary in the logical operation processing, and therefore may not be provided.

  FIG. 9 is a timing chart showing the operation of the first injection control circuit 40.

  Since the output signal O_XOR of the exclusive OR gate 41 is an exclusive OR of the input signal, it is high when the logic of the control signal INP and the logic of the control signal INN_1UI do not match (before timing T11 and timing T13 to T14). When the logic of the control signal INP matches the logic of the control signal INN_1UI (after the timings T11 to T13 and T14), the level is low. The output signal O_MUX of the selector 42 is high when the output signal O_XOR is low, and is low when the output signal O_XOR is high.

  The output signal O_MUX_DELAY of the NOT gate 45 is a signal obtained by logically inverting and delaying the output signal O_MUX an odd number of times. Therefore, the output signal O_MUX_DELAY goes from high level to low level at a timing (timing T12 and T15) after a predetermined delay time from the timing (timing T11 and T14) when the output signal O_MUX goes from low level to high level.

  Since the output signal O_NAND of the NAND gate 48 is a NAND of the input signals, the output signal O_NAND is at the low level only while both the output signal O_MUX and the output signal O_MUX_DELAY are at the high level. Therefore, the injection control signal INJ_P also becomes low level only while both the output signal O_MUX and the output signal O_MUX_DELAY are high level (timing T11 to T12 and T14 to T15).

  The time when the injection control signal INJ_P goes low is defined by the delay time of the delay circuit configured by the NOT gates 43-45. This time is the injection pulse width IPW of the injection control signal INJ_P, and is the time when the transistor Pm4 and the transistor Pe4 are turned on.

  FIG. 10 is a circuit diagram showing a configuration of second injection control circuit 50. Referring to FIG.

  The control circuit 30 generates an injection control signal INJ_N based on the control signals INN and INP_1UI, and controls the transistor Nm4 (second injection circuit) and the transistor Ne4 (fourth injection circuit). Including 50.

  The second injection control circuit 50 includes an exclusive OR gate 51, a selector 52, five NOT gates 53 to 57, and a NOR gate 58.

  The control signal INN and INP_1UI are input to the exclusive OR gate 51, and the output is connected to the selection signal input S of the selector 52. The selector 52 receives the high level signal H and the low level signal L, and selectively outputs either the signal H or L according to the potential of the selection signal input S. More specifically, the output of the selector 52 becomes low level when the selection signal input S is low level, and becomes high level when the selection signal input is high level.

  The NOT gate 53 has an input connected to the output of the selector 52 and an output connected to the input of the NOT gate 54. The output of NOT gate 54 is connected to the input of NOT gate 55. The NOT gates 53 to 55 are delay circuits provided to obtain a signal obtained by delaying the output signal of the selector 52, and the delay time is determined according to the number of connection stages (odd stages) of the NOT gate.

  The NOR gate 58 receives the output signal of the selector 52 and the output signal of the NOT gate 55, and the output is connected to the input of the NOT gate 56. The output of the NOT gate 56 is connected to the input of the NOT gate 57. The output signal of the NOT gate 57 is the injection control signal INJ_N. The NOT gates 56 and 57 mainly function as a buffer and are not necessary in the logical operation processing, and thus may not be provided.

  FIG. 11 is a timing chart showing the operation of the second injection control circuit 50.

  Since the output signal O_XOR of the exclusive OR gate 51 is an exclusive OR of the input signal, it is high when the logic of the control signal INN and the logic of the control signal INP_1UI do not match (before timing T21 and timing T23 to T24). When the logic of the control signal INN matches the logic of the control signal INP_1UI (after the timings T21 to T23 and T24), the level becomes low. The output signal O_MUX of the selector 52 is low when the output signal O_XOR is low, and is high when the output signal O_XOR is high.

  The output signal O_MUX_DELAY of the NOT gate 55 is a signal obtained by logically inverting and delaying the output signal O_MUX an odd number of times. Therefore, the output signal O_MUX_DELAY goes from the low level to the high level at a timing (timing T22 and T25) after a predetermined delay time from the timing when the output signal O_MUX goes from high level to low level (timing T21 and T24).

  Since the output signal O_NOR of the NOR gate 58 is the NOR of the input signals, it is high only while both the output signal O_MUX and the output signal O_MUX_DELAY are low. Therefore, the injection control signal INJ_N also becomes high level only while both the output signal O_MUX and the output signal O_MUX_DELAY are low level (timing T21 to T22 and T24 to T25).

  The time when the injection control signal INJ_N goes high is defined by the delay time of the delay circuit configured of the NOT gates 53-55. This time is the injection pulse width IPW of the injection control signal INJ_N, and is the time when the transistor Nm4 and the transistor Ne4 are turned ON.

  12 and 13 are timing charts showing the output voltage of the transmitter 100. FIG. FIG. 12 shows an output voltage when the injection control is not performed, and FIG. 13 shows an output voltage when the injection control is performed. FIG. 14 shows a simulation result (near end) of an output voltage waveform of the transmitter 100. FIG. 14 (A) executes injection control when injection control is not performed. Each case is shown.

  When the injection control is not performed, a delay in signal transition is likely to occur at timing when the amplitude changes due to de-emphasis control, particularly when the amplitude increases (timing T31 to T32 and T33 to T34). The transmitter 100 according to the present invention enables injection control in which the injection current is superimposed on the output current at that timing. The transmitter 100 according to the present invention performs injection control at the timing when the amplitude of the voltage VOD of the termination resistor RT changes by de-emphasis control, so that the injection current is superimposed on the output current and increases. The rise response is improved, and delay in rising of the signal transition can be reduced (timing T41 to T42 and T45 to T46). As a result, it is possible to reduce deterioration of the output signal waveform due to the delay in rising of the signal transition, thereby enabling faster signal transmission and more accurate de-emphasis.

  More specifically, referring to FIG. 2 again, the current flowing from the power supply to main driver unit 10m is the current path while transistor Pm4 is turned on and the current path from the power supply to node PTAIL is configured. The injection current I1 flowing through the transistor Pm1 is added to the constant current flowing through the transistor Pm1 and increases. Similarly, the current flowing from main driver unit 10m to ground is a constant current flowing through transistor Nm1 through injection current I2 flowing through transistor Nm4 while transistor Nm4 is turned on to form a current path from node NTAIL to ground. Add and increase. That is, when the transistors Pm4 and Nm4 are turned on to form another current path in parallel with the constant current path, the output current of the main driver unit 10m increases during that time, and the rise response of the signal transition is improved.

  Further, the current flowing from the power supply to the emphasis driver unit 10e is added to the constant current flowing through the transistor Pe1 through the injection current I3 flowing through the transistor Pe1 while the current path from the power supply to the node PTAIL_1UI is configured. To be increased. Similarly, the current flowing from the emphasis driver unit 10e to the ground is a constant current flowing through the transistor Ne1 through the injection current I4 flowing through the transistor NT4 while the current path from the node NTAIL_1UI to the ground is configured. Add and increase. Since the transistors Pe4 and Ne4 are turned on to form another current path in parallel with the constant current path, the output current of the emphasis driver unit 10e is also increased during that time, and the rise response of the signal transition is further improved.

  The timing at which the control circuit 30 executes the above-described injection control is, for example, a predetermined time from the timing at which the direction of the output current Imain flowing to the termination resistor RT and the direction of the output current Iemp switch from the opposite direction to the same direction. This timing is a timing at which the amplitude of the voltage VOD of the termination resistance RT changes from a relatively small state (a state in which de-emphasis is performed) to a relatively large state (a state in which de-emphasis is not performed). Therefore, as described above, delay in rising of the signal transition is likely to occur (timing T41 to T42 and timing T45 to T46). Therefore, by executing the above-mentioned injection control for a predetermined time from this timing, it is possible to properly reduce the deterioration of the output signal waveform caused by the delay in the rising of the signal transition.

  FIG. 15 is a circuit diagram showing another embodiment of the circuit configuration of the transmitter 100 according to the present invention.

  The circuit configuration of the transmitter 100 of FIG. 15 is the transmission of FIG. 2 except that transistors Pm5, Nm5, Pe5 and Ne5 are provided instead of the transistors Pm4, Nm4, Pe4 and Ne4 of the transmitter 100 of FIG. It is the same as the circuit configuration of the machine 100. Alternatively, in addition to the transmitter 100 of FIG. 2, transistors Pm5, Nm5, Pe5 and Ne5 may be further provided.

  The transistors Pm5 and Pe5 are P-type MOS field effect transistors. The transistors Nm5 to Ne5 are N-type MOS field effect transistors.

  The transistor Pm5 has a drain connected to ground, a source connected to the node PTAIL, and a gate to which the injection control signal INJ2_P output from the control circuit 30 is input. In the transistor Nm5, the source is connected to the node NTAIL, the drain is connected to the power supply, and the injection control signal INJ2_N output from the control circuit 30 is input to the gate.

  The transistor Pe5 has a drain connected to ground, a source connected to the node PTAIL_1UI, and a gate to which an injection control signal INJ2_P output from the control circuit 30 is input. The transistor Ne5 has a source connected to the node NTAIL_1UI, a drain connected to the power supply, and a gate to which the injection control signal INJ2_N output from the control circuit 30 is input.

  The transistor Pm5 as the “fifth injection circuit” configures a current path from the output (drain) of the transistor Pm1 to the ground according to the injection control signal INJ2_P. The transistor Nm5 as the “sixth injection circuit” configures a current path from the power supply to the input (drain) of the transistor Nm1 in accordance with the injection control signal INJ2_N. The transistor Pe5 as the “seventh injection circuit” configures a current path from the output (drain) of the transistor Pe1 to the ground according to the injection control signal INJ2_P. The transistor Ne5 as the “eighth injection circuit” configures a current path from the power supply to the input (drain) of the transistor Ne1 in accordance with the injection control signal INJ2_N.

  FIG. 16 is a circuit diagram showing the configuration of the third injection control circuit 60. As shown in FIG.

  Control circuit 30 generates injection control signal INJ2_P based on control signals INP and INN_1UI, and controls a transistor Pm5 (fifth injection circuit) and transistor Pe5 (seventh injection circuit). Including 60.

  The third injection control circuit 60 includes an exclusive OR gate 61, a selector 62, five NOT gates 63 to 67, and a NAND gate 68.

  The control signal INP and INN — 1UI are input to the exclusive OR gate 61, and the output is connected to the selection signal input S of the selector 62. The selector 62 receives the low level (ground potential) signal L and the high level (power supply voltage level) signal H, and selectively outputs either the signal L or H according to the potential of the selection signal input S. More specifically, the output of the selector 62 is low when the selection signal input S is low, and is high when the selection signal input is high.

  The NOT gate 63 has an input connected to the output of the selector 62 and an output connected to the input of the NOT gate 64. The output of the NOT gate 64 is connected to the input of the NOT gate 65. The NOT gates 63 to 65 are delay circuits provided to obtain a signal obtained by delaying the output signal of the selector 62, and the delay time is determined according to the number of connection stages (odd stages) of the NOT gate.

  The NAND gate 68 receives the output signal of the selector 62 and the output signal of the NOT gate 65, and the output is connected to the input of the NOT gate 66. The output of the NOT gate 66 is connected to the input of the NOT gate 67. The output signal of the NOT gate 67 is the injection control signal INJ2_P. The NOT gates 66 and 67 mainly function as buffers, and can be omitted because they are unnecessary in logical operation processing.

  FIG. 17 is a timing chart showing the operation of the third injection control circuit 60.

  Since the output signal O_XOR of the exclusive OR gate 61 is an exclusive OR of the input signals, it is high when the logic of the control signal INP and the logic of the control signal INN_1UI do not match (before timing T51 and timing T52 to T54). When the logic of the control signal INP matches the logic of the control signal INN_1UI (after the timings T51 to T52 and T54), the level is low. The output signal O_MUX of the selector 62 is low when the output signal O_XOR is low, and is high when the output signal O_XOR is high.

  The output signal O_MUX_DELAY of the NOT gate 65 is a signal obtained by logically inverting and delaying the output signal O_MUX an odd number of times. Therefore, the output signal O_MUX_DELAY goes from the high level to the low level at a timing (timing T53) after a predetermined delay time from the timing when the output signal O_MUX goes from low level to high level (timing T52).

  Since the output signal O_NAND of the NAND gate 68 is a NAND of the input signals, the output signal O_NAND is low only while both the output signal O_MUX and the output signal O_MUX_DELAY are high. Therefore, the injection control signal INJ2_P also becomes low level only while both the output signal O_MUX and the output signal O_MUX_DELAY are high level (timing T52 to T53).

  The time for which the injection control signal INJ2_P goes low is defined by the delay time of the delay circuit configured of the NOT gates 63 to 65. This time is the injection pulse width IPW of the injection control signal INJ2_P, and is the time when the transistor Pm5 and the transistor Pe5 are turned ON.

  FIG. 18 is a circuit diagram showing the configuration of the fourth injection control circuit 70. As shown in FIG.

  Control circuit 30 generates an injection control signal INJ2_N based on control signals INN and INP_1UI, and controls a transistor Nm5 (sixth injection circuit) and a transistor Ne5 (eighth injection circuit). Including 70.

  The second injection control circuit 70 includes an exclusive OR gate 71, a selector 72, five NOT gates 73 to 77 and a NOR gate 78.

  The control signal INN and INP_1UI are input to the exclusive OR gate 71, and the output is connected to the selection signal input S of the selector 72. The selector 72 receives the high level signal H and the low level signal L, and selectively outputs either the signal H or L according to the potential of the selection signal input S. More specifically, the output of the selector 72 is high when the selection signal input S is low, and is low when the selection signal input is high.

  The NOT gate 73 has an input connected to the output of the selector 72 and an output connected to the input of the NOT gate 74. The output of NOT gate 74 is connected to the input of NOT gate 75. The NOT gates 73 to 75 are delay circuits provided to obtain a signal obtained by delaying the output signal of the selector 72, and the delay time is determined according to the number of connection stages (odd stages) of the NOT gate.

  The NOR gate 78 receives the output signal of the selector 72 and the output signal of the NOT gate 75, and the output is connected to the input of the NOT gate 76. The output of the NOT gate 76 is connected to the input of the NOT gate 77. The output signal of the NOT gate 77 is the injection control signal INJ2_N. The NOT gates 76 and 77 mainly function as buffers, and are not necessary in the logical operation processing, and therefore may not be provided.

  FIG. 19 is a timing chart showing the operation of the fourth injection control circuit 70.

  Since the output signal O_XOR of the exclusive OR gate 71 is an exclusive OR of the input signals, it is high when the logic of the control signal INN and the logic of the control signal INP_1UI do not match (before timing T61 and timing T62 to T64). When the logic of the control signal INN matches the logic of the control signal INP_1UI (after the timings T61 to T62 and T64), the level becomes low. The output signal O_MUX of the selector 72 is high when the output signal O_XOR is low, and is low when the output signal O_XOR is high.

  The output signal O_MUX_DELAY of the NOT gate 75 is a signal obtained by logically inverting and delaying the output signal O_MUX an odd number of times. Therefore, the output signal O_MUX_DELAY goes from the low level to the high level at a timing (timing T63) after a predetermined delay time from the timing when the output signal O_MUX goes from high level to low level (timing T62).

  Since the output signal O_NOR of the NOR gate 78 is the negative logical sum of the input signals, it is high only while both the output signal O_MUX and the output signal O_MUX_DELAY are low. Therefore, the injection control signal INJ_N also becomes high level only while both the output signal O_MUX and the output signal O_MUX_DELAY are low level (timing T62 to T63).

  The time when the injection control signal INJ2_N becomes high level is defined by the delay time of the delay circuit constituted by the NOT gates 73-75. This time is the injection pulse width IPW of the injection control signal INJ2_N, and is the time when the transistor Nm5 and the transistor Ne5 are turned ON.

  Thus, the timing when the control circuit 30 executes the above-described injection control is, for example, a predetermined time from the timing when the direction of the output current Imain flowing to the termination resistance RT and the direction of the output current Iemp switch from the same direction to the opposite direction. It is also good. This timing is a timing at which the amplitude of the voltage VOD of the termination resistance RT changes from a relatively large state (state without de-emphasis) to a relatively small state (state with de-emphasis). Therefore, the fall of the signal transition is likely to be delayed (timing T43 to T44). Therefore, by executing the above-mentioned injection control for a predetermined time from this timing, it is possible to properly reduce the deterioration of the output signal waveform caused by the delay of the falling of the signal transition.

  More specifically, referring to FIG. 15 again, the current flowing from the power supply to main driver unit 10m is the current path while transistor Pm5 is turned on and the current path from node PTAIL to the ground is formed. Is reduced from the constant current flowing through the transistor Pm1. Similarly, the current flowing from main driver unit 10m to ground is a constant current flowing from transistor Nm1 through injection current I6 flowing through transistor Nm5 while current path from the power supply to node NTAIL is configured. It is subtracted and decreased. In other words, the transistors Pm5 and Nm5 are turned on to form a current path in the reverse direction to the constant current path, so that the output current of the main driver unit 10m is reduced during that time, and the response of the signal transition fall is improved. Do.

  Further, the current flowing from the power supply to the emphasis driver unit 10e is such that the injection current I7 flowing through the current path is subtracted from the constant current flowing through the transistor Pe1 while the transistor Pe5 is turned on to form a current path from the node PTAIL_1UI to the ground. Be reduced. Similarly, the current flowing from the emphasis driver unit 10e to ground is a constant current flowing through the transistor Ne1 through the injection current I8 flowing through the current path while the current path from the power supply to the node NTAIL_1UI is configured by turning on the transistor Ne5. It is subtracted and decreased. Since the transistors Pe5 and Ne5 are turned on to form a current path reverse to the constant current path, the output current of the emphasis driver unit 10e is also reduced during that time, and the fall response of the signal transition is further improved.

  In the transmitter 100 according to the present invention, the injection currents I1 to I8 can be obtained, for example, by adjusting the size (gate width etc.) of each of the transistors Pm4, Nm4, Pe4 and Ne4 and the transistors Pm5, Nm5, Pe5 and Ne5. It can be set to an appropriate current value. An appropriate current value can be determined, for example, from the result of circuit simulation. In order to reduce high frequency noise caused by the injection pulse, it is preferable that the injection control signal INJ_P and the injection control signal INJ_N match the timing and the injection pulse width IPW as precisely as possible. Similarly, in order to reduce high frequency noise caused by the injection pulse, it is preferable that the injection control signal INJ2_P and the injection control signal INJ2_N match the timing and the injection pulse width IPW as precisely as possible. The injection pulse width IPW is preferably sufficiently smaller than, for example, the width of 1 UI, and preferably does not exceed 1 UI, in order to prevent overshoot in the amplitude of the voltage VOD of the termination resistor RT.

  In the transmitter 100 according to the present invention, the control circuit 30 delays the timing of outputting the control signals INP and INN to the main driver unit 10m and the timing of outputting the control signals INP_1UI and INN_1UI to the emphasis driver unit 10e. It is also good. Thereby, due to the delay time generated in first injection control circuit 40, second injection control circuit 50, third injection control circuit 60 and fourth injection control circuit 70, injection control signals INJ_P and INJ_N are generated. If the output timing and the output timings of the injection control signals INJ2_P and INJ2_N do not meet the proper timing, the operation timings of the main driver unit 10m and the emphasis driver unit 10e can be delayed to match the timing.

  Further, in the transmitter 100 according to the present invention, the main driver unit 10m may further include another transistor or the like in addition to the transistor Pm4 as an injection circuit forming a current path from the power supply to the node PTAIL. Furthermore, as an injection circuit forming a current path from node NTAIL to the ground, another transistor or the like may be included in addition to transistor Nm4. Similarly, the emphasis driver unit 10e may further include another transistor or the like in addition to the transistor Pe4 as an injection circuit that configures a current path from the power supply to the node PTAIL_1UI. Furthermore, as an injection circuit forming a current path from node NTAIL_1UI to the ground, another transistor or the like may be included in addition to the transistor Ne4. As a result, since the current values of the injection currents I1 to I4 can be adjusted, more accurate injection control becomes possible.

  In addition, in the transmitter 100 according to the present invention, the main driver unit 10m may further include another transistor or the like in addition to the transistor Pm5 as an injection circuit configuring a current path from the node PTAIL to the ground. Furthermore, in addition to the transistor Nm5, another transistor or the like may be included as an injection circuit forming a current path from the power supply to the node NTAIL. Similarly, the emphasis driver unit 10e may further include another transistor or the like in addition to the transistor Pe5 as an injection circuit forming a current path from the node PTAIL_1UI to the ground. Furthermore, in addition to the transistor Ne5, another transistor or the like may be included as an injection circuit forming a current path from the power supply to the node NTAIL_1UI. As a result, the current values of the injection currents I5 to I8 can be adjusted, so that more accurate injection control becomes possible.

  Each of the above-described embodiments is an example for describing the present invention, and the present invention is not limited to the embodiments. The present invention can be practiced in various forms without departing from the scope of the invention.

  For example, in the method disclosed herein, the steps, operations or functions may be performed in parallel or in different orders, as long as the results are not inconsistent. The steps, operations and functions described are merely provided as examples, and some of the steps, operations and functions may be omitted without departing from the scope of the invention, and may be combined with one another. One or more steps, operations or functions may be added.

  In addition, although various embodiments are disclosed herein, the specific features (technical matters) in one embodiment may be added to the other embodiments or modified while appropriately improving the technical features. Specific features in the form can be substituted, and such form is also included in the scope of the present invention.

  The invention can be widely used in the field of transmitter circuits.

10 driver unit 10 e emphasis driver unit 10 m main driver unit 20 bias circuit 30 control circuit 40 first injection control circuit 50 second injection control circuit 60 third injection control circuit 70 fourth injection control circuit 100 transmitter 200 reception Machine

Claims (16)

A current output circuit connected in parallel to a termination resistor to control the magnitude and direction of the current flowing in the termination resistor;
A control circuit that generates a first control signal pair and a second control signal pair obtained by inverting and delaying the first control signal pair based on an input signal,
The transmission circuit, wherein the current output circuit includes a current superposition circuit controlled according to the first control signal pair and the second control signal pair and superposing an injection current on an output current of the current output circuit. The transmitter circuit according to claim 1, wherein
The current output circuit is
A first driver circuit connected in parallel to a termination resistor, supplying a predetermined current to the termination resistor, and controlling the direction of the current according to the first control signal pair;
A second driver circuit connected in parallel to the termination resistor, supplying a predetermined current to the termination resistor and controlling the direction of the current according to the second control signal pair;
The first driver circuit is
A first differential circuit,
A first constant current circuit for constant current control of a current flowing from a power supply to the first differential circuit;
And second constant current circuit for performing constant current control of current flowing from the first differential circuit to the ground,
The current superposition circuit is
A first injection circuit forming a current path in parallel with the first constant current circuit;
A second injection circuit which forms a current path in parallel with the second constant current circuit. The transmitter circuit according to claim 2, wherein the second driver circuit is
A second differential circuit,
A third constant current circuit for constant current control of a current flowing from the power supply to the second differential circuit;
A fourth constant current circuit for performing constant current control on a current flowing from the second differential circuit to the ground;
A third injection circuit forming a current path in parallel with the third constant current circuit;
And a fourth injection circuit forming a current path in parallel with the fourth constant current circuit.   The transmission circuit according to claim 3, wherein the control circuit is configured such that the direction of the current flowing from the first driver circuit to the termination resistor is opposite to the direction of the current flowing from the second driver circuit to the termination resistor. A transmission circuit, which constitutes a current path of the first to fourth injection circuits for a predetermined time from the timing of switching from the direction to the same direction.   The transmission circuit according to claim 3 or 4, wherein the control circuit controls the first to fourth injection circuits based on the first control signal pair and the second control signal pair. , Transmitter circuit.   6. The transmission circuit according to claim 5, wherein the control circuit controls the first and third injection circuits based on the first control signal pair and the second control signal pair. And an injection control circuit for controlling the second and fourth injection circuits based on the first control signal pair and the second control signal pair. .   The transmitter circuit according to any one of claims 3 to 6, wherein each of the first to fourth injection circuits includes a plurality of current paths having different current values. The transmission circuit according to any one of claims 3 to 7, wherein the current superposition circuit is
A fifth injection circuit forming a current path from the output of the first constant current circuit to the ground;
A sixth injection circuit that constitutes a current path from the output of the second constant current circuit to the ground. The transmitter circuit according to claim 8, wherein the current superposition circuit is
A seventh injection circuit forming a current path from the power supply to an input of the third constant current circuit;
And an eighth injection circuit that constitutes a current path from the power supply to the input of the fourth constant current circuit.   10. The transmission circuit according to claim 9, wherein the control circuit has the same direction of current flowing from the first driver circuit to the termination resistor and direction of current flowing from the second driver circuit to the termination resistor. The transmitter circuit which comprises the current path of the said 5th-8th injection circuit for a predetermined time from the timing switched to the opposite direction from a direction.   11. The transmission circuit according to claim 9, wherein said control circuit controls said fifth to eighth injection circuits based on said first control signal pair and said second control signal pair. , Transmitter circuit.   The transmission circuit according to claim 11, wherein the control circuit controls the fifth and seventh injection circuits based on the first control signal pair and the second control signal pair. And an injection control circuit for controlling the sixth and eighth injection circuits based on the first control signal pair and the second control signal pair. .   The transmitter circuit according to any one of claims 9 to 12, wherein each of the fifth to eighth injection circuits includes a plurality of current paths having different current values.   The transmitter circuit according to any one of claims 3 to 13, wherein the control circuit is configured to transmit the first control signal pair and the second control signal pair to the first driver circuit and the second driver circuit. A transmitter circuit that delays the timing of output to the driver circuit of. The transmitter circuit according to any one of claims 3 to 14, wherein the first differential circuit and the second differential circuit are differential circuits of complementary outputs,
The first control signal pair includes the input signal and a signal obtained by logically inverting the input signal, and the second control signal pair logically inverts the input signal and the input signal, and Transmit circuitry, including delayed signals. A control method of a transmitter circuit comprising a current output circuit connected in parallel to a termination resistor and controlling the magnitude and direction of a current flowing in the termination resistor,
Generating a first control signal pair and a second control signal pair obtained by inverting and delaying the first control signal pair based on the input signal;
A control method of a transmission circuit, wherein the current output circuit is controlled according to the first control signal pair and the second control signal pair, and an injection current is superimposed on the output current of the current output circuit.

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