CN115454190A - LVDS drive circuit - Google Patents
LVDS drive circuit Download PDFInfo
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- CN115454190A CN115454190A CN202211207876.4A CN202211207876A CN115454190A CN 115454190 A CN115454190 A CN 115454190A CN 202211207876 A CN202211207876 A CN 202211207876A CN 115454190 A CN115454190 A CN 115454190A
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
- G05F1/10—Regulating voltage or current
- G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
- G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
Abstract
The invention discloses an LVDS drive circuit, which comprises a reference circuit, a first voltage reference circuit, a second voltage reference circuit and a first voltage reference circuit, wherein the reference circuit is used for generating a first reference voltage and a second reference voltage; the drain voltage of the first field effect transistor and the drain voltage of the second field effect transistor are stabilized according to the first reference voltage and the second reference voltage; and the transmission gate logic circuit receives an input voltage signal of the LVDS, the drain voltage of the first field effect transistor and the drain voltage of the second field effect transistor and outputs a first common-mode voltage signal and a second common-mode voltage signal. The LVDS driving circuit provided by the invention can provide reference voltage for common-mode voltage, ensure the stability of output common-mode voltage and compensate attenuation and loss generated after long-distance transmission of high-speed signals.
Description
Technical Field
The invention belongs to the technical field of integrated circuits, and particularly relates to an LVDS driving circuit.
Background
With the rapid development and wide application of integrated circuits, LVDS (low voltage differential signaling) technology is an interface technology based on the demand of today's high-performance data transmission equipment, and the LVDS standard has become the most popular differential data transmission standard in industrial applications.
When transmitting a high-speed signal, the driver is a circuit module which couples the high-speed signal to the transmission line with the maximum power, and the LVDS driver can be divided into a voltage mode driving mode and a current mode driving mode according to different signal transmission modes. The current mode driving mode can be divided into a single current source driving mode and a double current source driving mode.
The LVDS driving circuit with the single current source mode is simple in structure and convenient to design, however, the value of the resistor R in the structure is often larger, so that a larger layout area is required to be occupied, and the design cost is greatly increased.
Compared with a single-current-source driving mode, the resistance R value required in the double-current-source driving mode is smaller, only hundreds of ohms are needed generally, the layout area can be greatly saved, and the reduction of the production cost is facilitated. Meanwhile, compared with a single-current-source driving mode, an upper current mirror and a lower current mirror are adopted in a double-current-source driving mode to provide output current, the two current mirrors form complementation, the stability of the output current is better facilitated, and a certain compensation effect can be provided for common-mode offset of the NMOS tube relative to the PMOS tube. The voltage driving mode is more favorable for the transmission of high-speed signals than the current driving mode, and the current driving mode has stronger noise suppression capability than the voltage driving mode.
However, in the actual transmission of high-speed signals, the following disadvantages still occur in the use of the LVDS drive circuit:
1) The inevitable offset and jitter of the chip output common mode level due to the changes of PVT (process, power supply voltage, temperature) and internal and external noises of the chip can cause the receiver end to acquire wrong voltage signals so as to generate bit errors;
2) When the drain ends of the constant current tubes are respectively and directly connected with the switching tubes, the voltage of the drain ends can generate offset and jitter along with the frequent switching-on and switching-off of the switching tubes, which can generate larger influence on the output voltage;
3) Since attenuation and loss inevitably occur in the long-distance transmission process of the high-speed signal, a receiving end cannot detect a correct data signal, and a large amount of intersymbol interference is generated.
If a practical LVDS drive circuit applicable to engineering needs to be designed, the performance of the LVDS drive circuit needs to be optimized according to the requirements of practical application.
Disclosure of Invention
Therefore, in view of at least one of the above drawbacks or needs of the prior art, an object of the present invention is to provide an improved LVDS driving circuit, which provides a reference voltage for a common-mode voltage, ensures a stable output common-mode voltage, compensates attenuation and loss generated after long-distance transmission of a high-speed signal, and solves the above drawbacks.
The invention discloses an LVDS drive circuit, the output signal of which is used for driving an LVDS main circuit, which is characterized in that the drive circuit comprises:
a reference circuit generating a first reference voltage and a second reference voltage;
the first reference voltage is input to a first input end of a first feedback amplifier, and a second input end of the first feedback amplifier is connected with a drain electrode of a first field effect transistor; the output end of the first feedback amplifier is connected with the grid electrode of the first field effect transistor; the source electrode of the first field effect transistor is connected with power voltage;
the second reference voltage is input to a first input end of a second feedback amplifier, and a second input end of the second feedback amplifier is connected with a drain electrode of a second field effect transistor; the output end of the second feedback amplifier is connected with the grid electrode of the second field effect transistor; the source electrode of the second field effect transistor is grounded;
the drain voltage of the first field effect transistor and the drain voltage of the second field effect transistor are stabilized according to the first reference voltage and the second reference voltage;
and the transmission gate logic circuit receives an input voltage signal, the drain voltage of the first field effect transistor and the drain voltage of the second field effect transistor and outputs a first common mode voltage signal and a second common mode voltage signal.
Furthermore, the reference circuit comprises a band-gap reference circuit used for generating a reference voltage, the reference voltage is connected to the input end of the error amplifier, and the other input end of the error amplifier is connected with the output end through a first divider resistor; the other input end of the error amplifier is connected with a second voltage-dividing resistor and a third voltage-dividing resistor, the first reference voltage is from the output of the error amplifier, and the second reference voltage is from the voltage signal output between the second voltage-dividing resistor and the third voltage-dividing resistor.
Furthermore, the LVDS driver circuit further includes a pre-emphasis circuit module, where the pre-emphasis circuit module includes a switch module, the switch module receives control of the LVDS main circuit, and the switch module is connected to an output of the LVDS main circuit, and selects to output the output of the LVDS main circuit in a switch gating or closing manner, or connects the pre-emphasis circuit module to compensate an output circuit signal.
Further, the bandgap reference circuit comprises a starting circuit, a PTAT current generating circuit and a reference generating circuit which are connected in sequence;
further, the proportion range of the pre-emphasis circuit is 5% -20%.
Furthermore, the first voltage-dividing resistor, the second voltage-dividing resistor and the third voltage-dividing resistor are resistors with adjustable resistance values.
Further, the control signal of the pre-emphasis circuit comprises four control switches.
Further, the PTAT current generating circuit comprises a bias circuit independent of a power supply and a bipolar transistor.
Further, the pre-emphasis circuit module is specifically that a first switch is connected with the grid of the field effect transistor MP6, a second switch is connected with the grid of the field effect transistor MP7, wherein the source electrodes of the field effect transistor MP6 and the field effect transistor MP7 are connected, and the drain electrodes of the field effect transistor MP6 and the field effect transistor MP7 are connected and connected to the source electrodes of the field effect transistor MP4 and the field effect transistor MP5 which are connected with each other; the drain electrodes of the field effect tube MP4 and the field effect tube MP5 are respectively connected with the drain electrodes of the field effect tube MN4 and the field effect tube MN5, and the source electrodes of the field effect tube MP4 and the field effect tube MP5 are connected with the connecting end connected with the drain electrodes of the field effect tube MN6 and the field effect tube MN 7; the third switch is connected with the source electrode of the field effect transistor MN6, and the fourth switch is connected with the source electrode of the field effect transistor MN 7;
the input voltage signal is respectively connected to the grids of the field effect tube MP4 and the field effect tube MP5, and the input voltage signal is also connected to the grids of the field effect tube MN4 and the field effect tube MN 5;
the first output signal is connected between the drain electrode connections of the field effect transistors MP4 and MN4, and the second output signal is connected between the drain electrode connections of the field effect transistors MP5 and MN 5.
Further, the switch module performs control at a transition edge of an input data signal, and the control time holds a time of at least one serial data bit.
In general, compared with the prior art, the above technical solution of the present invention can achieve the following beneficial effects:
in order to achieve the above object, the present invention provides an improved LVDS driving circuit, which mainly includes a common-mode feedback circuit, a reference generating circuit and a pre-emphasis circuit. A common mode feedback circuit is added to maintain the output common mode level constant, and an accurate reference voltage is also needed to be used as a reference for stabilizing the common mode level, so that a reference generating circuit is also needed. The switching noise becomes very obvious in a high-speed circuit, and a corresponding circuit is required to be added to inhibit the switching noise and ensure the stability of the output voltage. Decoupling processing is carried out at two ends of the constant current bias voltage to filter out switching noise, so that the influence of the switching noise on the circuit is minimized. Because attenuation and loss inevitably occur in the long-distance transmission process of the high-speed signal, a receiving end cannot detect a correct data signal, a large amount of intersymbol interference is generated, a pre-emphasis circuit is added to compensate the output data signal, and the probability of the intersymbol interference is reduced.
Drawings
Fig. 1 is a circuit configuration foundation of an LVDS driving circuit of a voltage driving mode implemented according to the present invention;
FIG. 2 is a diagram of an improved common mode feedback circuit implemented in accordance with the present invention;
FIG. 3 is a circuit diagram of an LDO-like circuit for generating a reference voltage signal, implemented in accordance with the present invention;
fig. 4 is a detailed structure of a pre-emphasis circuit diagram implemented in accordance with the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention. In addition, the technical features involved in the embodiments of the present invention described below may be combined with each other as long as they do not conflict with each other.
To achieve the above object, fig. 1 shows an LVDS driving circuit according to a voltage driving scheme improved according to the technical idea of the present invention. The constant current bias voltages Vref1 and Vref2 generated by the internal bias circuit are Vref1 and Vref2, so that MP3 and MN3 work in a saturated constant current region, and the difference between the drain voltages of the two transistors of MP3 and MN3 is controlled to be about 350mV, thereby providing a reference voltage for LVDS output.
MPl, MP2, MNl and MN2 are switching tubes, and when Vint1 is high level and Vint2 is low level, the output Vout1 and Vout2 are drain voltages of MNl and MP2 respectively. Conversely, when Vint1 is low and Vint2 is high, the output Vout1 and Vout2 are the drain voltages of MN2 and MP1, respectively. Thereby transmitting a valid "0" or "l" signal.
Due to the voltage driving mode, the LVDS signals meeting the requirements can be generated at the output end without resistors.
Fig. 2 is a diagram of an improved common mode feedback circuit that can be implemented to detect the output common mode voltage, compare it to a reference voltage, and send an error value back to the feedback network to adjust the output common mode level. The output common mode level of the transmitter is ensured to be fast and stable. FAI in fig. 2 is a feedback amplifier.
Specifically, as shown in fig. 2, the connection relationship between the circuits is specifically: a reference circuit that generates a reference voltage Vref1 and a reference voltage Vref2; a reference voltage Vref1 is input into a first input end of a feedback amplifier FA1, and a second input end of the feedback amplifier FA1 is connected with the drain electrode of a field effect transistor MP 13; the output end of the feedback amplifier FA1 is connected with the grid electrode of the field effect transistor MP 13; the source electrode of the field effect tube MP13 is connected with a power voltage Vdd; a reference voltage Vref2 is input into a first input end of a feedback amplifier FA2, and a second input end of the feedback amplifier FA2 is connected with a drain electrode of a field effect tube MN 13; the output end of the feedback amplifier FA2 is connected with the grid electrode of the field effect tube MN 13; the source electrode of the field effect tube MN13 is grounded; the drain voltage Vfp of the field effect transistor MP13 and the drain voltage Vfn of the field effect transistor MN13 are stabilized according to the reference voltage Vref1 and the reference voltage Vref2; the transmission gate logic circuit receives input voltage signals Vint1 and Vint2 of the LVDS, a drain voltage Vfp of the field effect transistor MP13 and a drain voltage Vfn of the field effect transistor MN13, and outputs a common mode voltage signal Vout1 and a common mode voltage signal Vout2.
The LVDS drive circuit can be regarded as a unit negative feedback control system composed of two stages of amplifiers, and functions to stabilize the MP13 drain voltage Vfp and the MN3 drain voltage Vfn at Vref1 and Vref2, respectively, where Vref1 and Vref2 are reference voltages generated by a reference circuit. MP11, MP12, MN11 and MN12 constitute transfer gate logic that functions to transfer Vfp, vfn to Vout1, vout2, respectively. The feedback control of the amplifier can achieve the effect of stabilizing the output common-mode voltage.
The common mode feedback circuit designed by the invention overcomes the defect that the traditional common mode feedback circuit needs to use a large resistor, and meanwhile, when the common mode voltage is extracted, the common mode voltage is not directly connected to an output port but passes through an FAI feedback amplifier circuit, so that the parasitic capacitance of the output port cannot be increased.
Fig. 3 is a LDO-like circuit for generating a reference voltage, which ensures that an output common mode voltage is constant within a predetermined range, and solves a problem that the output common mode voltage is easily affected by PVT variations. The common mode feedback circuit of the present invention requires two different reference voltages Vref1 and Vref2. The commonly used bandgap reference circuit consists of a start-up circuit, a PTAT current generating circuit and a reference generating circuit. The PTAT current generating circuit is formed by combining a bias circuit independent of a power supply and a bipolar transistor. The temperature coefficient of the output reference voltage can be ensured to be close to zero through reasonable parameter design. The conventional bandgap reference circuit can only provide a reference voltage of 1.25V, and if one is added, the circuit becomes complicated and the cost is increased. An additional stage LDO-like circuit is required to generate the two reference voltages required herein. Where EA is the error amplifier.
Specifically, as shown in fig. 3, the specific connection relationship between the circuits is: the reference circuit comprises a band-gap reference circuit and a voltage-stabilizing circuit, wherein the band-gap reference circuit is used for generating a reference voltage Vref, the reference voltage is connected to the input end of the error amplifier EA, and the other input end of the error amplifier EA is connected with the output end through a first divider resistor R0; the other input terminal of the error amplifier EA is connected to the second voltage dividing resistor R1 and the third voltage dividing resistor R2, the first reference voltage Vref1 is output from the error amplifier EA, and the second reference voltage Vref2 is output from a voltage signal between the second voltage dividing resistor R1 and the third voltage dividing resistor R2.
The reference voltage Vref generated by the band-gap reference circuit is connected to one input end of the error amplifier, and the other input end of the error amplifier is connected to the feedback voltage Vfp. When the output voltages Vref1 and Vref2 of the LDO-like circuit are increased due to PVT changes, vfp is correspondingly increased, so that the difference between the positive and negative input of the error amplifier is reduced, vref1 and Vref2 are also reduced, and the stability of the output voltage of the LDO-like circuit is ensured. And vice versa. By adjusting the proportional relation of the resistors R0, R1 and R2, the LDO circuit can output reference voltage meeting the requirements at will, and the practicability is greatly improved.
Fig. 4 shows that the pre-emphasis circuit is added in the invention, which is optimized on the basis of the traditional switch current operation mode, and the function of the structure is more perfect. In fig. 4, the input signals of the LVDS host circuit and the pre-emphasis circuit are Vint1 and Vint2, and the tail current source of the pre-emphasis circuit is controlled by four switching signals S1, S2, S3 and S4. When the input data signal has no change, S1= S2=1, S3= S4=0, and the current of the output end is only provided by the LVDS driving main circuit, so that the pre-emphasis effect is avoided; when the input data signal changes and PRE =0, at the transition edge of the input data signal, S1= S4=0, S2= S3=1 and the time of one serial data bit is kept, the output end current is provided by the LVDS driving main circuit and the PRE-emphasis circuit together, and the PRE-emphasis effect with the PRE-emphasis ratio of 5% is achieved; when the input data signal changes and PRE =1, at the transition edge of the input data signal, S1= S2=0, S3= S4=1 and the time of holding one serial data bit, the output end current is provided by the LVDS driving main circuit and the PRE-emphasis circuit together, and the PRE-emphasis effect with the PRE-emphasis ratio of 20% is achieved. The pre-emphasis circuit with adjustable pre-emphasis proportion can be realized through different combination relations of S1, S2, S3 and S4.
The LVDS driving circuit further comprises a pre-emphasis circuit module, the pre-emphasis circuit module comprises a switch module, the switch module is controlled by the LVDS main circuit, the switch module is connected with the output of the LVDS main circuit, the output of the LVDS main circuit is selected to be output in a switch gating or closing mode, or the pre-emphasis circuit module is connected to compensate signals of an output circuit.
As shown in fig. 4, the pre-emphasis circuit implemented according to the present invention includes a switch S1 connected to the gate of the field effect transistor MP6, a switch S2 connected to the gate of the field effect transistor MP7, wherein the sources of the MP6 and MP7 are connected, the drain is connected to the source terminals of the field effect transistor MP4 and the field effect transistor MP5, wherein Vint1 and Vint2 are respectively connected to the gates of the field effect transistor MP4 and the field effect transistor MP5, wherein Vint1 and Vint2 are also connected to the gates of the field effect transistor MN4 and the field effect transistor MN5, the drains of the field effect transistor MP4 and the field effect transistor MP5 are respectively connected to the drains of the field effect transistor MN4 and the field effect transistor MN5, the sources of the field effect transistor MP4 and the field effect transistor MP5 are connected to the connecting terminals of the drains of the field effect transistor MN6 and the field effect transistor MN7, a switch S3 is connected to the source of the field effect transistor MN6, a switch S4 is connected to the source of the field effect transistor MN7, and an output signal is connected to the drain of the field effect transistor MP4 and the field effect transistor MN 5.
The pre-emphasis circuit of the invention has no current when the input data is stable, thus greatly reducing the power consumption; the pre-emphasis proportion of the pre-emphasis circuit is adjustable, the pre-emphasis effect with a low pre-emphasis proportion (5%) can be selected during short-distance transmission, the pre-emphasis effect with a high pre-emphasis proportion (20%) can be selected during long-distance transmission, and compared with the pre-emphasis circuit in a switching current operation mode, the pre-emphasis circuit has the advantages that the power consumption is lower in practical application.
In signal transmission, due to the existence of parasitic resistance and parasitic capacitance, the transmission line can be equivalent to a low-pass filter, which causes high-frequency components in the signal to undergo attenuation and delay in the transmission process, resulting in insufficient individual data swing of the signal received by the receiver, and finally resulting in transmission data error, i.e. intersymbol interference fault. In order to eliminate intersymbol interference, a pre-emphasis circuit is added, and the working principle of the pre-emphasis circuit is as follows: when a transition occurs in the data signal, the signal is intentionally overdriven at the transition edge, which means that the high frequency component is compensated for because the high frequency component is generally concentrated at the transition edge of the data.
It will be understood by those skilled in the art that the foregoing is only a preferred embodiment of the present invention, and is not intended to limit the invention, and that any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the scope of the present invention.
The description is given for the sake of illustration only, and it is to be understood that various modifications and additions may be made or substituted in a similar manner by those skilled in the art without departing from the scope of the present invention as defined in the appended claims.
Claims (10)
1. An LVDS driving circuit, an output signal of which is used for driving an LVDS main circuit, the driving circuit comprising:
a reference circuit generating a first reference voltage (Vref 1) and a second reference voltage (Vref 2);
the first reference voltage is input to a first input end of a first feedback amplifier (FA 1), and a second input end of the first feedback amplifier (FA 1) is connected with a drain electrode of a first field effect transistor (MP 13); the output end of the first feedback amplifier (FA 1) is connected with the grid of the first field effect transistor (MP 13); the source electrode of the first field effect transistor (MP 13) is connected with a power supply voltage (Vdd);
the second reference voltage is input into a first input end of a second feedback amplifier (FA 2), and a second input end of the second feedback amplifier (FA 2) is connected with a drain electrode of a second field effect transistor (MN 13); the output end of the second feedback amplifier (FA 2) is connected with the grid of the second field effect transistor (MN 13); the source electrode of the second field effect transistor (MN 13) is grounded;
the drain voltage (Vfp) of the first field effect transistor (MP 13) and the drain voltage (Vfn) of the second field effect transistor (MN 13) are stabilized according to the first reference voltage (Vref 1) and the second reference voltage (Vref 2);
and the transmission gate logic circuit receives input voltage signals (Vint 1 and Vint 2), the drain voltage (Vfp) of the first field effect transistor (MP 13) and the drain voltage (Vfn) of the second field effect transistor (MN 13), and outputs a first common mode voltage signal (Vout 1) and a second common mode voltage signal (Vout 2).
2. The LVDS driver circuit according to claim 1, wherein the reference circuit comprises a bandgap reference circuit for generating a reference voltage (Vref) coupled to an input of an Error Amplifier (EA), another input of the Error Amplifier (EA) being coupled to the output via a first divider resistor (R0); the other input end of the Error Amplifier (EA) is connected with a second voltage division resistor (R1) and a third voltage division resistor (R2), the first reference voltage (Vref 1) is from the output of the Error Amplifier (EA), and the second reference voltage (Vref 2) is from the voltage signal output between the second voltage division resistor (R1) and the third voltage division resistor (R2).
3. The LVDS drive circuit according to claim 1 or 2, further comprising a pre-emphasis circuit module, wherein the pre-emphasis circuit module comprises a switch module, the switch module is controlled by the LVDS main circuit, the switch module is connected with the output of the LVDS main circuit, the switch module is used for selecting the output of the LVDS main circuit in a switch gating or closing manner, or the pre-emphasis circuit module is switched on to compensate the output circuit signal.
4. The LVDS drive circuit according to claim 3, wherein the bandgap reference circuit comprises a start-up circuit, a PTAT current generating circuit and a reference generating circuit connected in sequence.
5. The LVDS drive circuit according to claim 4, wherein the proportion of the pre-emphasis circuit is in a range of 5% to 20%.
6. The LVDS driver circuit according to claim 2, wherein the first voltage dividing resistor, the second voltage dividing resistor, and the third voltage dividing resistor are resistors with adjustable resistance values.
7. The LVDS drive circuit as set forth in claim 6, wherein the control signal for the pre-emphasis circuit includes four control switches.
8. The LVDS drive circuit according to claim 7, wherein the PTAT current generating circuit includes a power-independent bias circuit and a bipolar transistor in combination.
9. The LVDS driver circuit according to claim 7, wherein the pre-emphasis circuit module is embodied such that the first switch (S1) is connected to a gate of the fet MP6, the second switch (S2) is connected to a gate of the fet MP7, wherein sources of the fet MP6 and the fet MP7 are connected, drains of the fet MP6 and the fet MP7 are connected and connected to source terminals of the fet MP4 and the fet MP5 which are connected to each other; the drain electrodes of the field effect tube MP4 and the field effect tube MP5 are respectively connected with the drain electrodes of the field effect tube MN4 and the field effect tube MN5, and the source electrodes of the field effect tube MP4 and the field effect tube MP5 are connected with the connecting end connected with the drain electrodes of the field effect tube MN6 and the field effect tube MN 7; the third switch (S3) is connected with the source electrode of the field effect tube MN6, and the fourth switch (S4) is connected with the source electrode of the field effect tube MN 7;
the input voltage signals (Vint 1 and Vint 2) are respectively connected to the grids of the field effect tube MP4 and the field effect tube MP5, wherein the input voltage signals (Vint 1 and Vint 2) are also connected to the grids of the field effect tube MN4 and the field effect tube MN 5;
wherein the first output signal (Vout 1) is coupled between the drain connections of the fets MP4 and MN4, and the second output signal (Vout 2) is coupled between the drain connections of the fets MP5 and MN 5.
10. The LVDS driver circuit according to claim 3, wherein the switch module performs control at a transition edge of an input data signal, and the control time holds a time of at least one serial data bit.
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