CN115001462A - Rail-to-rail hysteresis comparison circuit and electronic equipment - Google Patents

Rail-to-rail hysteresis comparison circuit and electronic equipment Download PDF

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Publication number
CN115001462A
CN115001462A CN202210519640.8A CN202210519640A CN115001462A CN 115001462 A CN115001462 A CN 115001462A CN 202210519640 A CN202210519640 A CN 202210519640A CN 115001462 A CN115001462 A CN 115001462A
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China
Prior art keywords
rail
tube
pmos
nmos
signal
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Chinese (zh)
Inventor
宋阳
韩文涛
田永刚
周唯晔
赵鹏
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STMicroelectronics Shenzhen R&D Co Ltd
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STMicroelectronics Shenzhen R&D Co Ltd
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Priority to CN202210519640.8A priority Critical patent/CN115001462A/en
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/22—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral
    • H03K5/26—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being duration, interval, position, frequency, or sequence
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/01—Shaping pulses
    • H03K5/08—Shaping pulses by limiting; by thresholding; by slicing, i.e. combined limiting and thresholding
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

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  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Manipulation Of Pulses (AREA)

Abstract

The application belongs to the field of rail-to-rail hysteresis comparators and provides a rail-to-rail hysteresis comparison circuit and electronic equipment. The rail-to-rail input module is used for receiving an input signal and a bias power supply signal and generating a single-ended signal according to the input signal and the bias power supply signal, and the clamping current comparison module is connected with the rail-to-rail input module and used for receiving the single-ended signal and the bias power supply signal and clamping the voltage of the single-ended signal to generate a clamping current signal. The hysteresis buffer module is connected with the clamping current comparison module and used for receiving the clamping current signal and performing hysteresis buffer processing on the clamping current signal to generate a driving signal. The rail-to-rail input module can work normally when the common mode range of input signals is wide, and meanwhile the clamping current comparison module improves the working speed of the rail-to-rail hysteresis comparison circuit.

Description

Rail-to-rail hysteresis comparison circuit and electronic equipment
Technical Field
The application belongs to the field of rail-to-rail hysteresis comparators, and particularly relates to a rail-to-rail hysteresis comparison circuit and electronic equipment.
Background
Low Voltage Differential Signaling (LVDS) enables high speed transmission of Low swing input signals, provides fast edge driving output signals, and is often used to convey clock signals. Clock driving is widely applied to various computers and communication systems, and functions such as clock distribution and driving are achieved. In the high-speed differential driving technology, compared with CML and ECL structures, the LVDS input has the widest common-mode input range and lower output swing, which is beneficial to realizing low power consumption, and if the LVDS is a multi-channel LVDS clock driving chip, the advantages are more obvious.
However, the conventional rail-to-rail comparator has a problem that it cannot handle LVDS of a wide common mode range.
Disclosure of Invention
An object of the present application is to provide a rail-to-rail hysteresis comparison circuit and an electronic device, which are used to solve the problem that a rail-to-rail comparator cannot handle LVDS with a wide common mode range.
The present application provides in one aspect a rail-to-rail hysteresis comparison circuit, comprising:
the rail-to-rail input module is used for receiving an input signal and a bias power supply signal and generating a single-ended signal according to the input signal and the bias power supply signal;
the clamping current comparison module is connected with the rail-to-rail input module and used for receiving the single-ended signal and the bias power supply signal and clamping the voltage of the single-ended signal to generate a clamping current signal;
and the hysteresis buffer module is connected with the clamping current comparison module and used for receiving the clamping current signal and performing hysteresis buffer processing on the clamping current signal to generate a driving signal.
In one embodiment, the rail-to-rail hysteresis comparison circuit further comprises:
and the bias power supply module is connected with the rail-to-rail input module and the clamping current comparison module and is used for providing bias power supply signals for the rail-to-rail input module and the clamping current comparison module.
In one embodiment, the bias power supply module is a cascode current mirror.
In one embodiment, the rail-to-rail input module comprises: the NMOS transistor comprises a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a fifth PMOS transistor, a sixth PMOS transistor, a seventh PMOS transistor, an eighth PMOS transistor, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, a seventh NMOS transistor, an eighth NMOS transistor and a reference signal receiving NMOS transistor; wherein,
the control end of the first PMOS tube is connected with the first incoming end of the input signal, the second end of the first PMOS tube is connected with the first end of the third PMOS tube, the first end of the first PMOS tube is connected with the first end of the fifth NMOS tube, the first end of the second PMOS tube is connected with the first end of the sixth NMOS tube, the second end of the second PMOS tube is connected with the first end of the third PMOS tube, the control end of the second PMOS tube is connected with the second incoming end of the input signal, the first end of the first NMOS tube is connected with the second end of the seventh PMOS tube, the second end of the first NMOS tube is connected with the first end of the third NMOS tube, the control end of the first NMOS tube is connected with the first incoming end of the input signal, the first end of the second NMOS tube is connected with the second end of the eighth PMOS tube, and the second end of the second NMOS tube is connected with the first end of the third NMOS tube, the control end of the second NMOS transistor is connected to the second input end of the input signal, the second end of the third NMOS transistor is grounded, the control end of the third NMOS transistor is connected to the control end of the fourth NMOS transistor, the second end of the third PMOS transistor receives a power signal, the control end of the third PMOS transistor is connected to the control end of the fourth PMOS transistor, the first end of the fourth NMOS transistor is connected to the first end of the fourth PMOS transistor, the second end of the fourth NMOS transistor is grounded, and the second end of the fourth PMOS transistor receives the power signal;
the second end of the fifth PMOS tube receives the power supply signal, the first end of the fifth PMOS tube is connected with the seventh PMOS tube, the first end of the sixth PMOS tube is connected with the second end of the eighth PMOS tube, the second end of the sixth PMOS tube receives the power supply signal, and the control end of the sixth PMOS tube and the control end of the fifth PMOS tube are jointly connected with the first end of the seventh PMOS tube, the control end of the fifth NMOS tube and the control end of the sixth NMOS tube; the control end of the seventh PMOS tube and the control end of the eighth PMOS tube commonly receive a first bias power supply signal, the second end of the seventh NMOS tube is connected with the first end of the fifth NMOS tube, the second end of the eighth NMOS tube is connected with the first end of the sixth NMOS tube, the second end of the fifth NMOS tube is grounded, the second end of the sixth NMOS tube is grounded, the first end of the eighth PMOS tube and the second end of the eighth NMOS tube are also commonly connected with the clamping current comparison module, the control end of the reference signal receiving NMOS tube is connected with the control end of the seventh NMOS tube and the control end of the eighth NMOS tube, the first end of the reference signal receiving NMOS tube is connected with the control end of the eighth NMOS tube and the control end of the seventh NMOS tube and receives a second bias power supply signal, and the second end of the reference signal receiving NMOS tube is grounded.
In one embodiment, the clamp current comparison module includes:
the inverting unit is connected with the rail-to-rail input module and used for inverting the single-ended signal to generate the clamping current signal;
and the feedback unit is connected with the inverting unit and used for feeding back the clamping current signal at the output end of the inverting unit to the input end of the inverting unit so as to clamp the voltage of the single-ended signal.
In one embodiment, the clamp current comparison module further comprises:
and the switch unit is respectively connected with the phase inversion unit and the feedback unit and is used for controlling the connection state between the phase inversion unit and the power supply and the connection state between the feedback unit and the power supply according to a switch control signal.
In one embodiment, the inverting unit includes: a tenth NMOS transistor and a tenth PMOS transistor; wherein,
the first end of the tenth NMOS tube and the first end of the tenth PMOS tube are connected with the rail-to-rail input module together, the second end of the tenth PMOS tube receives the bias power supply signal, the second end of the tenth NMOS tube is grounded, and the control end of the tenth PMOS tube and the control end of the tenth NMOS tube are connected with the hysteresis buffer module and the feedback unit.
In one embodiment, the feedback unit includes: an eleventh PMOS tube and an eleventh NMOS tube; wherein,
the first end of the eleventh PMOS tube and the first end of the eleventh NMOS tube are connected with the phase inversion unit together, the second end of the eleventh PMOS tube receives a power supply signal, the second end of the eleventh NMOS tube is grounded, and the control end of the eleventh PMOS tube and the control end of the eleventh NMOS tube are connected with the rail-to-rail input module.
In one embodiment, the hysteresis buffer module comprises a twelfth PMOS tube, a twelfth NMOS tube, a thirteenth PMOS tube, a thirteenth NMOS tube, a fourteenth PMOS tube, a fourteenth NMOS tube, a first inverter and a second inverter; wherein,
a first end of the twelfth PMOS tube is connected with a second end of the thirteenth PMOS tube, a second end of the twelfth PMOS tube receives a power supply signal, a control end of the twelfth PMOS tube is connected with the clamping current comparison module, a first end of the thirteenth PMOS tube is connected with a first end of the thirteenth NMOS tube, a control end of the thirteenth PMOS tube is connected with the clamping current comparison module, a second end of the thirteenth NMOS tube is connected with a first end of the twelfth NMOS tube, a control end of the thirteenth NMOS tube is connected with the clamping current comparison module, a second end of the twelfth NMOS tube is grounded, a control end of the twelfth NMOS tube is connected with the clamping current comparison module, a first end of the twelfth PMOS tube and a second end of the thirteenth PMOS tube are connected with each other, a second end of the thirteenth NMOS tube and a first end of the twelfth NMOS tube are connected with a second end of the fourteenth NMOS tube, the first end of the fourteenth NMOS tube is grounded, the control end of the fourteenth PMOS tube is connected with the first end of the thirteenth PMOS tube MP13, the control end of the fourteenth NMOS tube is connected with the first end of the thirteenth PMOS tube MP13, the first end of the fourteenth NMOS tube is grounded, the input end of the first phase inverter is connected with the first end of the thirteenth PMOS tube, the output end of the first phase inverter is connected with the input end of the second phase inverter, and the output end of the second phase inverter outputs the driving signal.
The present application provides, in another aspect, an electronic device including the rail-to-rail hysteresis comparison circuit described in any of the above embodiments.
The rail-to-rail hysteresis comparison circuit comprises a rail-to-rail input module, a clamping current comparison module and a hysteresis buffer module. The rail-to-rail input module is used for receiving an input signal and a bias power supply signal and generating a single-ended signal according to the input signal and the bias power supply signal, and the clamping current comparison module is connected with the rail-to-rail input module and used for receiving the single-ended signal and the bias power supply signal and clamping the voltage of the single-ended signal to generate a clamping current signal. The hysteresis buffer module is connected with the clamping current comparison module and used for receiving the clamping current signal and performing hysteresis buffer processing on the clamping current signal to generate a driving signal. The rail-to-rail input module can work normally when the common mode range of input signals is wide, and meanwhile the clamping current comparison module improves the working speed of the rail-to-rail hysteresis comparison circuit.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
FIG. 1 is a functional block diagram of a rail-to-rail hysteresis comparison circuit provided in an embodiment of the present application;
FIG. 2 is a schematic circuit diagram of a rail-to-rail input comparison module according to an embodiment of the present disclosure;
fig. 3 is a schematic circuit diagram of a clamp current comparison module according to an embodiment of the present disclosure;
fig. 4 is a schematic circuit diagram of a rail-to-rail hysteresis comparison circuit according to an embodiment of the present disclosure.
Detailed Description
In order to make the technical problems, technical solutions and advantageous effects to be solved by the present application clearer, the present application is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present application and are not intended to limit the present application.
It will be understood that when an element is referred to as being "secured to" or "disposed on" another element, it can be directly on the other element or be indirectly on the other element. When an element is referred to as being "connected to" another element, it can be directly connected to the other element or be indirectly connected to the other element.
It will be understood that the terms "length," "width," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," and the like, refer to an orientation or positional relationship illustrated in the drawings for convenience in describing the present application and to simplify description, and do not indicate or imply that the referenced device or element must have a particular orientation, be constructed and operated in a particular orientation, and thus should not be construed as limiting the present application.
Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present application, "a plurality" means two or more unless specifically limited otherwise.
In the field of integrated circuits, LVDS can achieve high-speed transmission of clock driving signals, and in the high-speed differential driving technology, LVDS has a wide common-mode range and a low output swing, but signals in the wide common-mode range need to be processed by a rail-to-rail comparator, and a conventional rail-to-rail comparator cannot achieve rapid transmission of LVDS.
In order to solve the above problem, an embodiment of the present application provides a rail-to-rail hysteresis comparison circuit in one aspect, which includes a rail-to-rail input module 100, a clamp current comparison module 200, and a hysteresis buffer module 300, as shown in fig. 1. The rail-to-rail input module 100 is configured to receive input signals INP and INN and a bias power signal Ve, and generate a single-ended signal Vi according to the input signal and the bias power signal, the clamp current comparison module 200 is connected to the rail-to-rail input module 100, and is configured to receive the single-ended signal Vi and the bias power signal Ve, and clamp a voltage of the single-ended signal Vi to generate a clamp current signal Vl, and the hysteresis buffer module 300 is connected to the clamp current comparison module 200, and is configured to receive the clamp current signal Vl, and perform hysteresis buffer processing on the clamp current signal Vl to generate a driving signal Vc.
Specifically, with continued reference to fig. 1, the rail-to-rail input module 100 receives a first input signal INP and a second input signal INN, where the first input signal INP and the second input signal INN have the same amplitude and opposite phase, and the rail-to-rail input module 100 will operate normally when the common mode level of the input signal received by the rail-to-rail input module 100 is higher, lower or moderate. When the input signal is high level and the amplitude is large enough, the rail-to-rail input module 100 converts the first input signal INP and the second input signal INN into the single-ended signal Vi and outputs the single-ended signal Vi to the clamping current comparison module 200, where the clamping current comparison module 200 is a simple current comparator, and after the clamping current comparison module 200 clamps the single-ended signal, the current of the single-ended signal Vi of the rail-to-rail input module 100 is not separated from a saturation region, so as to reduce the transmission delay of the single-ended signal Vi. The hysteresis buffer module 300 receives the clamped current signal Vl, and the hysteresis buffer module 300 provides a hysteresis function and enhances the driving capability of the clamped current signal Vl to drive a large parasitic capacitor introduced by a rear-stage metal connecting wire and the like.
In this embodiment, when the common mode level of the input signal received by the rail-to-rail input module 100 is higher, lower or moderate, the rail-to-rail input module 100 will normally operate, which solves the problem that the conventional rail-to-rail comparator cannot handle the LVDS with a wide common mode range. The input signals INP and INN have slight variations near the threshold, the generated driving signal Vc will generate corresponding fluctuation variations, the rail-to-rail hysteresis comparator circuit has two threshold voltages, if the input signals change in one direction, the output driving signal Vc jumps only once, and if the input signals are between the two threshold voltages, the driving signal Vc with the original waveform is kept output. When the state of the received ground input signal changes, the single-ended signal Vi output by the rail-to-rail input module 100 is separated from the saturation region, and when the state of the received ground input signal changes, the single-ended signal Vi needs to be restored to the saturation region from the non-saturation region, so that the restoration time is long, the highest working speed of the rail-to-rail hysteresis comparison circuit is limited, the clamping current comparison module 200 is connected behind the rail-to-rail input module 100, and the clamping current comparison module 200 clamps the single-ended signal Vi output by the rail-to-rail input module 100 to enable the single-ended signal Vi not to be separated from the saturation region any more, so that the time for the single-ended signal Vi to be restored to the saturation region is shortened, the time delay is reduced, and the working speed of the rail-to-rail hysteresis comparison circuit is improved.
In one embodiment, referring to fig. 1, the rail-to-rail hysteresis comparison circuit further includes a bias power module 400, and the bias power module 400 is connected to the rail-to-rail input module 100 and the clamp current comparison module 200, and is configured to provide a bias power signal Ve to the rail-to-rail input module 100 and the clamp current comparison module 200.
In the present embodiment, the bias power signal Ve provides the first bias power signal IREF and the second bias power signal VB1 for the rail-to-rail input module 100, and provides the switch control signals VB2 and VB3 for the clamp current comparing module 200.
In one embodiment, the bias power supply module 400 is a cascode current mirror.
In the embodiment, the voltages of the two branches of the cascode current mirror are equal, so that errors caused by the channel length modulation effect and the threshold deviation caused by the drain can be eliminated.
In one embodiment, the rail-to-rail input module includes a first PMOS transistor MP1, a second PMOS transistor MP2, a third PMOS transistor MP3, a fourth PMOS transistor MP4, a fifth PMOS transistor MP5, a sixth PMOS transistor MP6, a seventh PMOS transistor MP7, an eighth PMOS transistor MP8, a first NMOS transistor MN1, a second NMOS transistor MN2, a third NMOS transistor MN3, a fourth NMOS transistor MN4, a fifth NMOS transistor MN5, a sixth NMOS transistor MN6, a seventh NMOS transistor MN7, an eighth NMOS transistor MN8, and a reference signal receiving NMOS transistor MNR.
The control end of a first PMOS tube MP1 is connected with the first access end of an input signal, the second end of a first PMOS tube MP1 is connected with the first end of a third PMOS tube MP3, the first end of the first PMOS tube MP1 is connected with the first end of MN5 of a fifth NMOS tube, the first end of a second PMOS tube MP2 is connected with the first end of a sixth NMOS tube MN6, the second end of the second PMOS tube MP2 is connected with the first end of the third PMOS tube MP3, the control end of the second PMOS tube MP2 is connected with the second access end of the input signal, the first end of the first NMOS tube MN1 is connected with the second end of a seventh PMOS tube MN7, the second end of the first NMOS tube MN8 is connected with the first end of a third NMOS tube MN3, the control end of the first NMOS tube MN1 is connected with the first access end of the input signal, the first end of the second NMOS tube MN2 is connected with the second end of an eighth PMOS tube MP8, the second end of the second NMOS tube MN 84 is connected with the second end of the NMOS tube MN 4642, and the second end of the NMOS tube MN 4642 is connected with the second end of the second NMOS 3, the control end of the third NMOS transistor MN3 is connected to the control end of the fourth NMOS transistor MN4, the second end of the third PMOS transistor MP3 receives the power supply signal VDD, the control end of the third PMOS transistor MP3 is connected to the control end of the fourth PMOS transistor MP4, the first end of the fourth NMOS transistor MN4 is connected to the first end of the fourth PMOS transistor MP4, the second end of the fourth NMOS transistor MN4 is grounded to GND, and the second end of the fourth PMOS transistor MP4 receives the power supply signal VDD.
A second end of the fifth PMOS transistor MP5 receives a power signal VDD, a first end of the fifth PMOS transistor MP5 is connected to the seventh PMOS transistor MP7, a first end of the sixth PMOS transistor MP6 is connected to a second end of the eighth PMOS transistor MP8, a second end of the sixth PMOS transistor MP6 receives the power signal VDD, and a control end of the sixth PMOS transistor MP6 and a control end of the fifth PMOS transistor MP5 are connected to the first end of the seventh PMOS transistor MP7, a control end of the fifth NMOS transistor MN5 and a control end of the sixth NMOS transistor MN 6; the control end of the seventh PMOS transistor MP7 and the control end of the eighth PMOS transistor MP8 commonly receive a first bias power signal IREF, the second end of the seventh NMOS transistor MN7 is connected to the first end of the fifth NMOS transistor MN5, the second end of the eighth NMOS transistor MN8 is connected to the first end of the sixth NMOS transistor MN6, the second end of the fifth NMOS transistor MN5 is grounded GND, the second end of the sixth NMOS transistor MN6 is grounded GND, the first end of the eighth PMOS transistor MP8 and the second end of the eighth NMOS transistor MN8 are also commonly connected to the clamp current comparing module 200, the control end of the reference signal receiving NMOS transistor MNR is connected to the control ends of the seventh NMOS transistor MN7 and the eighth NMOS transistor MN8, the first end of the reference signal receiving NMOS transistor MNR is connected to the control ends of the eighth NMOS transistor MN8 and the seventh NMOS transistor MN7 and receives a second bias power signal VB1, and the second end of the reference signal receiving NMOS transistor MNR is grounded GND.
Specifically, in this embodiment, the first end of the first PMOS transistor MP1 to the eighth PMOS transistor MP8 may be the drain thereof, the second end of the first PMOS transistor MP1 to the eighth PMOS transistor MP8 may be the source thereof, and the control end of the first PMOS transistor MP1 to the eighth PMOS transistor MP8 may be the gate thereof. The first end of the first NMOS transistor MN1 to the eighth NMOS transistor MP8 may be a drain thereof, the second end of the first NMOS transistor MN1 to the eighth NMOS transistor MN8 may be a source thereof, and the control end of the first NMOS transistor MN1 to the eighth NMOS transistor MN8 may be a gate thereof.
When the common mode level of the input signals INN and INP is high, the first NMOS transistor MN1 and the second NMOS transistor MN2 are turned on, the rail-to-rail input module 100 normally operates, when the common mode level of the input signals INN and INP is low, the first PMOS transistor MP1 and the second PMOS transistor MP2 are turned on, the circuit normally operates, when the common mode level of the input signals INN and INP is moderate, the first NMOS transistor MN1, the second NMOS transistor MN2, the first PMOS transistor MP1, and the second PMOS transistor MP2 are all turned on, and at this time, the rail-to-rail input module 100 still normally operates, so the rail-to-rail input module 100 can process input signals in a wide common mode range.
When the rail-to-rail input module 100 operates, when a differential signal in the input signal is at a high level and has a sufficiently large amplitude, the input signal INP is at a high level, the input signal INN is at a low level, at this time, the first NMOS transistor MN1 and the second PMOS transistor MP2 are turned on, the second NMOS transistor MN2 and the first PMOS transistor MP1 are turned off, the current in the third PMOS transistor MP3 all flows into the sixth NMOS transistor MN6, and the current in the third NMOS transistor MN3 is completely provided by the NMOS transistor MN 4.
Since the first PMOS transistor MP1 is in an off state, the current of the seventh NMOS transistor MN7 is equal to the current of the fifth NMOS transistor. Since the current IN the third NMOS transistor MN3 is completely supplied by the fifth PMOS transistor MP5, the current flowing through the fifth PMOS transistor MP5 is IP5 ═ IN3+ IP7 ═ IN3+ IN5, where IN3 is the current flowing through the third NMOS transistor MN3, IP7 is the current flowing through the seventh PMOS transistor MP7, and IN5 is the current flowing through the fifth NMOS transistor MN 5. Since the second NMOS transistor MN2 is IN an off state, a current IP8 ═ IP6 ═ IP5 ═ IP3+ IN5 flows through the eighth PMOS transistor, where IP3 is a current flowing through the third PMOS transistor MP3, IP5 is a current flowing through the fifth PMOS transistor MP5, and IP6 is a current flowing through the sixth PMOS transistor MP 6. Since the IP3 entirely flows into the sixth NMOS transistor MN6, and the current IN the sixth NMOS transistor MN6 remains unchanged, the current flowing through the eighth NMOS transistor MN8 is IN8 — IN6-IP3, where IN6 is the current flowing through the sixth NMOS transistor MN6, and IP3 is the current flowing through the third PMOS transistor.
The current value Iout of the single-ended signal Vi output by the rail-to-rail output module 100 is:
Iout＝IP8-IN8＝IN3+IN5-(IN6-IP3)＝IN3+IN5-IN6+IP3
IN this embodiment, IN the process of increasing the point of the single-ended signal Vi output by the rail-to-rail input module 100, the drain voltages of the sixth PMOS transistor MP6 and the eighth PMOS transistor gradually increase and leave the saturation region, while the current component flowing through the eighth PMOS transistor MP8 decreases, and when IP8 is IN8, IN6, IN5, the single-ended signal Vi reaches the highest point, so that the conversion of the input signals INN and INP to the single-ended signal Vi is achieved.
In one embodiment, as shown in connection with fig. 3, the clamp current comparison module 200 includes an inverting unit 210 and a feedback unit 220. The inverting unit 210 is connected to the rail-to-rail input module 100, and configured to perform inverting processing on the single-ended signal Vi to generate a clamping current signal Vl. The feedback unit 220 is connected to the inverting unit 210, and configured to feed back the clamping current signal Vi at the output of the inverting unit 210 to the input of the inverting unit 210, so as to clamp the voltage of the single-ended signal Vi.
In this embodiment, the inverting unit 210 and the feedback unit 220 clamp the single-ended signal Vi output by the rail-to-rail input module 100, so that the single-ended signal Vi is no longer separated from the saturation region, the time for the single-ended signal Vi to recover to the saturation region is reduced, the transmission delay of the single-ended signal Vi is greatly reduced, and the operating speed of the rail-to-rail hysteresis comparison circuit is increased.
In one embodiment, as shown in connection with fig. 3, the clamp current comparison module 200 further includes a switching unit 230. The switching unit 230 is connected to the inverting unit 210 and the feedback unit 220, respectively, for controlling a connection state between the inverting unit 210 and the power supply and a connection state between the feedback unit 220 and the power supply according to the switching control signals VB2 and VB 3.
Specifically, referring to fig. 3, the switch unit 230 includes a ninth PMOS transistor MP9 and a ninth NMOS transistor MN 9. A first end of the ninth PMOS transistor MP9 is connected to the second end of the tenth PMOS transistor MP10 and the second end of the eleventh PMOS transistor MP11, a second end of the ninth PMOS transistor MP9 is connected to a power supply and receives the power signal VDD, and a control end of the ninth PMOS transistor receives the first switch control signal VB 2. The first end of the ninth NMOS transistor MN9 is connected to the second end of the tenth NMOS transistor MN10 and the second end of the eleventh NMOS transistor MN11, the second end of the ninth NMOS transistor MN9 is grounded GND, and the control end of the ninth PMOS transistor receives the second switch control signal VB 3.
In this embodiment, the first ends of the ninth PMOS transistor MP9 and the ninth NMOS transistor MN9 may be the drains thereof, the second ends of the ninth PMOS transistor MP9 and the ninth NMOS transistor MN9 may be the sources thereof, and the control ends of the ninth PMOS transistor MP9 and the ninth NMOS transistor MN9 may be the gates thereof.
The ninth NMOS transistor MN9 and the ninth PMOS transistor MN9 are control switches, and when the rail-to-rail hysteresis comparator does not need the clamp current comparator 200 to operate, the ninth NMOS transistor MN9 and the ninth PMOS transistor MP9 are turned off, thereby reducing the power consumption of the clamp current comparator 200.
In one embodiment, the inverter unit 210 includes a tenth NMOS transistor MN10 and a tenth PMOS transistor MP 10. The first end of the tenth NMOS transistor MN10 and the first end of the tenth PMOS transistor MP10 are commonly connected to the rail-to-rail input module 100, the second end of the tenth PMOS transistor MP10 receives the power signal VDD, the second end of the tenth NMOS transistor MN10 is grounded GND, and the control end of the tenth PMOS transistor MP10 and the control end of the tenth NMOS transistor MN10 are connected to the hysteresis buffer module 300 and the feedback unit 220.
In this embodiment, the first ends of the tenth PMOS transistor MP10 and the tenth NMOS transistor MN10 may be the drains thereof, the second ends of the tenth PMOS transistor MP10 and the tenth NMOS transistor MN10 may be the sources thereof, and the control ends of the tenth PMOS transistor MP10 and the tenth NMOS transistor MN10 may be the gates thereof.
When the single-ended signal Vi is near the balance point of the circuit, the single-ended signal Vi and the clamp current signal Vl satisfy:
Vi-VN10<Vl<Vi+VP10
VN10 is the threshold voltage of a tenth NMOS transistor MN10, NP10 is the threshold voltage of a tenth PMOS transistor, at this time, both the tenth NMOS transistor MN10 and the tenth PMOS transistor MP10 are in an off state, the clamp current comparison module 200 is equivalent to a common inverter, and when Vi deviates from a balance point, the tenth NMOS transistor MN10 or the tenth PMOS transistor MP10 will be turned on, and the current flowing through the tenth NMOS transistor MN10 or the tenth PMOS transistor MP10 is output to the input end of the inverting unit 210, so as to balance the current of the single-ended signal Vi, and the voltage of the single-ended signal Vi stops continuously changing, thereby implementing the clamp function.
In one embodiment, referring to fig. 3, the feedback unit 220 includes an eleventh PMOS transistor NP11 and an eleventh NMOS transistor MP 12. The first end of the eleventh PMOS transistor MP11 and the first end of the eleventh NMOS transistor MN11 are commonly connected to the inverting unit 210, the second end of the eleventh PMOS transistor MP11 receives the power signal VDD, the second end of the eleventh NMOS transistor MN11 is grounded GND, and the control end of the eleventh PMOS transistor MP11 and the control end of the eleventh NMOS transistor MN11 are connected to the rail-to-rail input module 100.
In this embodiment, the first ends of the eleventh PMOS transistor MP11 and the eleventh NMOS transistor MN10 may be the drains thereof, the second ends of the eleventh PMOS transistor MP11 and the eleventh NMOS transistor MN11 may be the sources thereof, and the control ends of the eleventh PMOS transistor MP11 and the eleventh NMOS transistor MN11 may be the gates thereof.
The eleventh NMOS transistor MN11 and the eleventh PMOS transistor MP11 provide a channel from the output terminal of the clamp current comparing module 200 to the input terminal of the clamp current comparing module 200, so that the clamp current signal Vl controls the tenth PMOS transistor MP10 and the tenth NMOS transistor MN 10.
In one embodiment, referring to fig. 4, the hysteresis buffer module 300 includes a twelfth PMOS transistor MP12, a twelfth NMOS transistor MN13, a thirteenth PMOS transistor MP13, a thirteenth NMOS transistor MN13, a fourteenth PMOS transistor MP14, a fourteenth NMOS transistor MN14, a first inverter G1, and a second inverter G2.
A first end of a twelfth PMOS tube MP11 is connected to a second end of a thirteenth PMOS tube MP13, a second end of the twelfth PMOS tube MP12 receives a power supply signal VDD, a control end of the twelfth PMOS tube MP12 is connected to the clamp current comparison module 200, a first end of a thirteenth PMOS tube MP13 is connected to a first end of a thirteenth NMOS tube MN13, a control end of a thirteenth PMOS tube MP13 is connected to the clamp current comparison module 200, a second end of the thirteenth NMOS tube MN13 is connected to a first end of a twelfth NMOS tube MN12, a control end of a thirteenth NMOS tube MN13 is connected to the clamp current comparison module 200, a second end of a twelfth NMOS tube MN12 is grounded, a control end of a twelfth NMOS tube MN12 is connected to the clamp current comparison module 200, a first end of the twelfth PMOS tube MP12 and a second end of the thirteenth PMOS tube MP13 are connected to a second end of a fourteenth PMOS tube MP14, a second end of the thirteenth NMOS tube MN13 and a second end of the twelfth NMOS tube MN12 are connected to a second end of the fourteenth NMOS 14, the first end of the fourteenth NMOS tube is grounded, the control end of the fourteenth PMOS tube is connected with the first end of the thirteenth PMOS tube MP13, the control end of the fourteenth NMOS tube is connected with the first end of the thirteenth PMOS tube MP13, the first end of the fourteenth NMOS tube MN14 is grounded GND, the input end of the first phase inverter G1 is connected with the first end of the thirteenth PMOS tube MP13, the output end of the first phase inverter G1 is connected with the input end of the second phase inverter G2, and the output end of the second phase inverter G2 outputs a driving signal Vc.
In this embodiment, with continued reference to fig. 4, the first ends of the twelfth PMOS transistor MP12 to the fourteenth PMOS transistor MP14 and the twelfth NMOS transistor MN12 to the fourteenth NMOS transistor MN14 may be the drains thereof, the second ends of the twelfth PMOS transistor MP12 to the fourteenth PMOS transistor MP14 and the twelfth NMOS transistor MN12 to the fourteenth NMOS transistor MN14 may be the sources thereof, and the control ends of the twelfth PMOS transistor MP12 to the fourteenth PMOS transistor MP14 and the twelfth NMOS transistor MN12 to the fourteenth NMOS transistor MN14 may be the gates thereof.
The twelfth PMOS transistor MP12, the twelfth NMOS transistor MN13, the thirteenth PMOS transistor MP13, the thirteenth NMOS transistor MN13, the fourteenth PMOS transistor MP14 and the fourteenth NMOS transistor MN14 form a schmitt trigger, which provides a hysteresis function for the rail-to-rail hysteresis comparator, and the first inverter G1 and the second inverter G2 provide a buffer function for the driving signal Vc to be output, so as to enhance the driving capability of LVDS.
The present application provides, in another aspect, an electronic device including the rail-to-rail hysteresis comparison circuit described in any of the above embodiments.
The rail-to-rail hysteresis comparison circuit comprises a rail-to-rail input module, a clamping current comparison module and a hysteresis buffer module. The rail-to-rail input module is used for receiving an input signal and a bias power supply signal and generating a single-ended signal according to the input signal and the bias power supply signal, and the clamping current comparison module is connected with the rail-to-rail input module and used for receiving the single-ended signal and the bias power supply signal and clamping the voltage of the single-ended signal to generate a clamping current signal. The hysteresis buffer module is connected with the clamping current comparison module and used for receiving the clamping current signal and performing hysteresis buffer processing on the clamping current signal to generate a driving signal. The rail-to-rail input module can work normally when the common mode range of input signals is wide, and meanwhile the clamping current comparison module improves the working speed of the rail-to-rail hysteresis comparison circuit.
In the above embodiments, the description of each embodiment has its own emphasis, and reference may be made to the related description of other embodiments for parts that are not described or recited in any embodiment.
The above-mentioned embodiments are only used for illustrating the technical solutions of the present application, and not for limiting the same; although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications and substitutions do not substantially depart from the spirit and scope of the embodiments of the present application and are intended to be included within the scope of the present application.

Claims (10)

1. A rail-to-rail hysteresis comparison circuit, the rail-to-rail hysteresis comparison circuit comprising:
the rail-to-rail input module is used for receiving an input signal and a bias power supply signal and generating a single-ended signal according to the input signal and the bias power supply signal;
the clamping current comparison module is connected with the rail-to-rail input module and used for receiving the single-ended signal and the bias power supply signal and clamping the voltage of the single-ended signal to generate a clamping current signal;
and the hysteresis buffer module is connected with the clamping current comparison module and used for receiving the clamping current signal and performing hysteresis buffer processing on the clamping current signal to generate a driving signal.
2. The rail-to-rail hysteresis comparison circuit of claim 1, further comprising:
and the bias power supply module is connected with the rail-to-rail input module and the clamping current comparison module and is used for providing bias power supply signals for the rail-to-rail input module and the clamping current comparison module.
3. The rail-to-rail hysteresis comparison circuit of claim 2, wherein the bias supply module is a cascode current mirror.
4. The rail-to-rail hysteresis comparison circuit of claim 1, wherein the rail-to-rail input module comprises: the NMOS transistor comprises a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a fifth PMOS transistor, a sixth PMOS transistor, a seventh PMOS transistor, an eighth PMOS transistor, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, a seventh NMOS transistor, an eighth NMOS transistor and a reference signal receiving NMOS transistor; wherein,
the control end of the first PMOS tube is connected with the first access end of the input signal, the second end of the first PMOS tube is connected with the first end of the third PMOS tube, the first end of the first PMOS tube is connected with the first end of the fifth NMOS tube, the first end of the second PMOS tube is connected with the first end of the sixth NMOS tube, the second end of the second PMOS tube is connected with the first end of the third PMOS tube, the control end of the second PMOS tube is connected with the second access end of the input signal, the first end of the first NMOS tube is connected with the second end of the seventh PMOS tube, the second end of the first NMOS tube is connected with the first end of the third NMOS tube, the control end of the first NMOS tube is connected with the first access end of the input signal, the first end of the second NMOS tube is connected with the second end of the eighth PMOS tube, and the second end of the second NMOS tube is connected with the first end of the third NMOS tube, the control end of the second NMOS tube is connected with the second access end of the input signal, the second end of the third NMOS tube is grounded, the control end of the third NMOS tube is connected with the control end of the fourth NMOS tube, the second end of the third PMOS tube receives a power supply signal, the control end of the third PMOS tube is connected with the control end of the fourth PMOS tube, the first end of the fourth NMOS tube is connected with the first end of the fourth PMOS tube, the second end of the fourth NMOS tube is grounded, and the second end of the fourth PMOS tube receives the power supply signal;
the second end of the fifth PMOS tube receives the power supply signal, the first end of the fifth PMOS tube is connected with the seventh PMOS tube, the first end of the sixth PMOS tube is connected with the second end of the eighth PMOS tube, the second end of the sixth PMOS tube receives the power supply signal, and the control end of the sixth PMOS tube and the control end of the fifth PMOS tube are jointly connected with the first end of the seventh PMOS tube, the control end of the fifth NMOS tube and the control end of the sixth NMOS tube; the control end of the seventh PMOS tube and the control end of the eighth PMOS tube commonly receive a first bias power supply signal, the second end of the seventh NMOS tube is connected with the first end of the fifth NMOS tube, the second end of the eighth NMOS tube is connected with the first end of the sixth NMOS tube, the second end of the fifth NMOS tube is grounded, the second end of the sixth NMOS tube is grounded, the first end of the eighth PMOS tube and the second end of the eighth NMOS tube are also commonly connected with the clamping current comparison module, the control end of the reference signal receiving NMOS tube is connected with the control end of the seventh NMOS tube and the control end of the eighth NMOS tube, the first end of the reference signal receiving NMOS tube is connected with the control end of the eighth NMOS tube and the control end of the seventh NMOS tube and receives a second bias power supply signal, and the second end of the reference signal receiving NMOS tube is grounded.
5. The rail-to-rail hysteresis comparison circuit of claim 2, wherein the clamping current comparison module comprises:
the inverting unit is connected with the rail-to-rail input module and used for inverting the single-ended signal to generate the clamping current signal;
and the feedback unit is connected with the inverting unit and used for feeding back the clamping current signal at the output end of the inverting unit to the input end of the inverting unit so as to clamp the voltage of the single-ended signal.
6. The rail-to-rail hysteresis comparison circuit of claim 5, wherein the clamping current comparison module further comprises:
and the switch unit is respectively connected with the phase inversion unit and the feedback unit and is used for controlling the connection state between the phase inversion unit and the power supply and the connection state between the feedback unit and the power supply according to a switch control signal.
7. The rail-to-rail hysteresis comparison circuit of claim 5, wherein the inverting unit comprises: a tenth NMOS transistor and a tenth PMOS transistor; wherein,
the first end of the tenth NMOS tube and the first end of the tenth PMOS tube are connected with the rail-to-rail input module together, the second end of the tenth PMOS tube receives the bias power supply signal, the second end of the tenth NMOS tube is grounded, and the control end of the tenth PMOS tube and the control end of the tenth NMOS tube are connected with the hysteresis buffer module and the feedback unit.
8. The rail-to-rail hysteresis comparison circuit of claim 5, the feedback unit comprising: an eleventh PMOS tube and an eleventh NMOS tube; wherein,
the first end of the eleventh PMOS tube and the first end of the eleventh NMOS tube are connected with the phase inversion unit together, the second end of the eleventh PMOS tube receives a power supply signal, the second end of the eleventh NMOS tube is grounded, and the control end of the eleventh PMOS tube and the control end of the eleventh NMOS tube are connected with the rail-to-rail input module.
9. The rail-to-rail hysteresis comparison circuit of claim 1, wherein the hysteresis buffer module comprises a twelfth PMOS tube, a twelfth NMOS tube, a thirteenth PMOS tube, a thirteenth NMOS tube, a fourteenth PMOS tube, a fourteenth NMOS tube, a first inverter and a second inverter; wherein,
a first end of the twelfth PMOS transistor is connected to a second end of the thirteenth PMOS transistor, a second end of the twelfth PMOS transistor receives a power signal, a control end of the twelfth PMOS transistor is connected to the clamp current comparison module, a first end of the thirteenth PMOS transistor is connected to a first end of the thirteenth NMOS transistor, a control end of the thirteenth PMOS transistor is connected to the clamp current comparison module, a second end of the thirteenth NMOS transistor is connected to the first end of the twelfth NMOS transistor, a control end of the thirteenth NMOS transistor is connected to the clamp current comparison module, a second end of the twelfth NMOS transistor is grounded, a control end of the twelfth NMOS transistor is connected to the clamp current comparison module, a first end of the twelfth PMOS transistor and a second end of the thirteenth PMOS transistor are connected to a second end of the fourteenth PMOS transistor, a second end of the thirteenth NMOS transistor and a first end of the twelfth NMOS transistor are connected to a second end of the fourteenth NMOS transistor, the first end of the fourteenth NMOS tube is grounded, the control end of the fourteenth PMOS tube is connected with the first end of the thirteenth PMOS tube MP13, the control end of the fourteenth NMOS tube is connected with the first end of the thirteenth PMOS tube MP13, the first end of the fourteenth NMOS tube is grounded, the input end of the first phase inverter is connected with the first end of the thirteenth PMOS tube, the output end of the first phase inverter is connected with the input end of the second phase inverter, and the output end of the second phase inverter outputs the driving signal.
10. An electronic device, characterized in that the electronic device comprises a rail-to-rail hysteresis comparison circuit as claimed in any one of claims 1 to 8.
CN202210519640.8A 2022-05-13 2022-05-13 Rail-to-rail hysteresis comparison circuit and electronic equipment Pending CN115001462A (en)

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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115225067A (en) * 2022-09-09 2022-10-21 深圳市汇顶科技股份有限公司 Hysteresis comparator and chip based on operational amplifier
CN116470890A (en) * 2023-05-06 2023-07-21 湖南毂梁微电子有限公司 Hysteresis comparison circuit and electronic equipment
CN116827276A (en) * 2023-08-30 2023-09-29 江苏润石科技有限公司 Operational amplifier input stage circuit and common mode state detection method
CN117478108A (en) * 2023-12-11 2024-01-30 深圳市微源半导体股份有限公司 Comparison circuit and comparator

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115225067A (en) * 2022-09-09 2022-10-21 深圳市汇顶科技股份有限公司 Hysteresis comparator and chip based on operational amplifier
CN115225067B (en) * 2022-09-09 2023-03-10 深圳市汇顶科技股份有限公司 Hysteresis comparator and chip based on operational amplifier
CN116470890A (en) * 2023-05-06 2023-07-21 湖南毂梁微电子有限公司 Hysteresis comparison circuit and electronic equipment
CN116470890B (en) * 2023-05-06 2024-01-26 湖南毂梁微电子有限公司 Hysteresis comparison circuit and electronic equipment
CN116827276A (en) * 2023-08-30 2023-09-29 江苏润石科技有限公司 Operational amplifier input stage circuit and common mode state detection method
CN116827276B (en) * 2023-08-30 2023-11-14 江苏润石科技有限公司 Operational amplifier input stage circuit and common mode state detection method
CN117478108A (en) * 2023-12-11 2024-01-30 深圳市微源半导体股份有限公司 Comparison circuit and comparator
CN117478108B (en) * 2023-12-11 2024-03-12 深圳市微源半导体股份有限公司 Comparison circuit and comparator

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