TWI780942B - Digital circuit capable of generating differential signal and microcontroller using the same - Google Patents

Abstract

A digital circuit capable of generating differential signal and a microcontroller using the same are provided. The digital circuit includes a signal generating circuit, a first, a second, a third, and a fourth input/output pads (I/O pads). The signal generating circuit is configured to generate a first signal and a second signal, both of which form a differential signal, based on an input signal, wherein the second signal is inverted to the second signal. The first and the second I/O pads are coupled to the signal generating circuit and determine whether to enable according to a first enable signal. The third and the fourth I/O pads are configured to determine whether to enable according to a second enable signal which is inverted to the first enable signal. When the first and the second I/O pads are enabled, the first and the second I/O pads are configured to transmit the differential signal.

Description

Digital circuits capable of generating differential signals and microcontrollers using them

The present invention relates to a digital circuit and a microcontroller, and in particular to a digital circuit capable of generating differential signals and a microcontroller using it.

In some systems with relatively high-speed signal transmission, differential signal (Differential Signal) type transmission signal is used, because the type of differential signal transmission signal can resist noise. A differential signal consists of two signals that are 180 degrees out of phase with each other, as shown in Figure 1. Figure 1 shows an ideal differential signal with equal amplitudes and a phase difference of 180 degrees between the two signals. If the positive-phase signal Sp and the negative-phase signal Sn are overlapped, the overlapping position of the two signals will be exactly in the middle of the amplitude of the two signals, which means that the quality of the differential signal DFS is very good. However, in practical applications, due to circuit delay, one of the signals usually lags behind or leads the other signal. If the signal cannot maintain a phase difference close to 180 degrees, as shown in Figure 2, the anti-phase signal Sn has a delay DLY compared with the normal-phase signal Sp, which will cause the overlapping point of the two signals to no longer be in the middle of the amplitude. It may cause the receiving end to misjudge the transition time of the differential signal DFS'. Traditionally, differential signals need to be implemented through analog circuits to have low error characteristics, so it is usually necessary to additionally design analog circuits to generate differential signals.

In the prior art, it has also been proposed to use digital circuit design to solve the problem of complicated analog circuit design required for differential signal generation. However, it is still difficult for existing digital circuits to generate high-precision/low-error differential signals, so it is also difficult to apply to high-speed transmission applications. As shown in Figure 3, Fig. 3 is a schematic diagram of a conventional differential signal generating circuit. The function control circuit FCC can control whether the positive phase signal Sp and the negative phase signal Sn are output. Another main function is to select whether the input and output signals of other components or functional modules can be input and output through the input and output connection pads PAD0 and PAD1. . In other words, in the digital circuit, the user can change the mode or output value of the input and output connection pads PAD0 and PAD1 by changing the setting values PAD0_SEL and PAD1_SEL of the function control circuit FCC, so that the input and output connection pads PAD0 and PAD1 can be freely Set to multiple functions. Here, since the output of the positive-phase signal Sp and the negative-phase signal Sn is emphasized, the relationship between the functional control circuit FCC and other components or functional modules is not shown.

In the general scheme of using digital circuits to generate differential signals, the inverter INV can be used to generate the inverted signal Sn, wherein the positive-phase signal Sp and the inverted signal Sn will be respectively provided to the corresponding input and output through the function control circuit FCC Connect pads PAD0 and PAD1. Generally speaking, the positive-phase signal Sp and the negative-phase signal Sn will pass through combination circuits CC1 and CC2 composed of many digital circuits (eg, multiplexers and logic gates) when they reach the I/O connection pads PAD0 and PAD1 . Since the combination circuits CC1 and CC2 passed by the anti-phase signal Sn and the normal-phase signal Sp are not necessarily the same, the positions and signal transmission paths of these combination circuits CC1 and CC2 in the actual layout will also be different, so it will make There is a problem of delay between the inverted signal Sn and the normal-phase signal Sp, so that the final waveform will be as shown in Figure 2, and the phase difference between the signals cannot reach 180 degrees. If the differential clock is very high-speed, it may cause the transmission failure of the circuit using this clock synchronization. The only way to correct the path of the positive-phase signal Sp and the negative-phase signal Sn to the input and output connection pads PAD0 and PAD1 is to continuously correct the path through the back-end engineering. Make the two signals close to 180 degrees, but this process is very cumbersome and difficult to adjust. In addition, it may be because the combination circuit CC1 and CC2 have passed too much logic, resulting in a difference of 180 degrees under a certain function setting, but a different one The phase of the function settings and the two have shifted again.

An embodiment of the present invention provides a digital circuit capable of generating differential signals. The digital circuit includes a signal generating circuit, first and second input and output connection pads, and third and fourth input and output connection pads. The signal generating circuit is used for generating a first signal and a second signal constituting a differential signal based on the input signal, wherein the first signal and the second signal are opposite to each other. The first and second input-output connection pads are coupled to the signal generating circuit, and whether to enable is determined according to the first enabling signal. The third and fourth input-output connection pads are used to determine whether to enable according to a second enable signal that is opposite to the first enable signal. When the first and the second input-output connection pads are enabled, the first and the second input-output connection pads are respectively used to transmit a first signal and a second signal constituting the differential signal, And when the third and the fourth input-output connection pads are enabled, the third and the fourth input-output connection pads are used to transmit a plurality of functional signals. The first and the third input-output connection pads are commonly coupled to one of a plurality of package pins, and the second and the fourth input-output connection pads are commonly coupled to the plurality of package pins another of them.

An embodiment of the present invention provides a microcontroller, which includes a plurality of package pins, a function control circuit, a signal generating circuit, first and second input and output connection pads, and third and fourth input and output connection pads. The function control circuit is used for generating multiple function signals. The signal generating circuit is used for generating a first signal and a second signal constituting a differential signal based on the clock signal, wherein the first signal and the second signal are opposite to each other. The first and second input-output connection pads are coupled to the signal generation circuit for respectively receiving the first signal and the second signal constituting the differential signal. The third and fourth input-output connection pads are coupled to the function control circuit to respectively receive the plurality of function signals. The first and the third input-output connection pads are commonly coupled to one of the plurality of package pins, and the second and the fourth input-output connection pads are commonly coupled to the plurality of package pins. The other of the package pins.

In summary, compared with the prior art, the digital circuit capable of generating differential signals and the microcontroller using it in the embodiment of the present invention can greatly shorten the circuit because no additional analog circuit is designed to generate differential signals. design schedule. Furthermore, compared to the traditional digital circuit to generate the difference For the mechanism of dynamic signals, the embodiments of the present invention can effectively improve the phase shift problem of differential signals of digital circuits in different application scenarios, and also reduce the complexity of circuit adjustment. In addition, since the packaging pins of the circuit do not need to use extra pins under the design of this embodiment, the microcontroller can also optionally have the ability to output accurate differential clock signals, so it can be used without increasing the cost. Under the premise of reducing or circuit complexity, the microcontroller can be more widely used in high-speed transmission scenarios.

In order to further understand the techniques, means and effects of the present invention, reference can be made to the following detailed description and accompanying drawings, so that the purpose, features and concepts of the present invention can be thoroughly and specifically understood. However, the following detailed description and drawings are only for reference and illustration of the implementation of the present invention, and are not intended to limit the present invention.

50: microcontroller

52, 52_clk, 52_clkb: package pins

100, 200: digital circuit

110: Signal generating circuit

112, INV, 132_1, 132_2: inverter

114: delay circuit

120_1~120_4, PAD0, PAD1: input and output connection pads

130. FCC: Function Control Circuit

CLK, CLK', CLK_b: clock signal

DFS, DFS’: differential signal

Dout: data output terminal

DLY: delayed

EN: enable terminal

PAD0_SEL, PAD1_SEL: set value of function control circuit

S1: input signal

S1’, S1_b: signal

Sen, Sen_b: enable signal

SEL1, SEL2: function signal

Sp: positive phase signal

Sn: anti-phase signal

The accompanying drawings are provided to enable those skilled in the art to which the present invention pertains to further understand the present invention, and are incorporated in and constitute a part of the specification of the present invention. The drawings illustrate exemplary embodiments of the invention and together with the description serve to explain principles of the invention.

FIG. 1 is a schematic diagram of a waveform of a differential signal.

FIG. 2 is a schematic diagram of another differential signal waveform.

FIG. 3 is a schematic diagram of a conventional differential signal generating circuit.

FIG. 4 is a schematic diagram of a digital circuit capable of generating differential signals according to an embodiment of the present invention.

FIG. 5 is a schematic diagram of a microcontroller according to an embodiment of the present invention.

Reference will now be made in detail to the exemplary embodiments of the invention, which are illustrated in the accompanying drawings. Where possible, the same reference numerals are used in the drawings and description to refer to same or similar parts. In addition, the practice of the exemplary embodiment is only one of the implementations of the design concept of the present invention, and the following demonstrations are not intended to limit the present invention.

The terms "first", "second", ... etc. used herein do not refer to the meaning of order or sequence, nor are they used to limit the present invention, but are only used to distinguish elements described with the same technical terms. or operation only.

In addition, the "coupling" or "connection" used in this article can refer to two or more elements in direct physical or electrical contact with each other, or indirect physical or electrical contact with each other, and can also refer to two or more components. Multiple elements operate or act on each other.

The embodiment of the present invention proposes a differential signal generation mechanism implemented by a digital circuit. Since no additional design of an analog circuit is required to generate the differential signal, the circuit design time can be greatly shortened. Furthermore, compared with the traditional mechanism of using digital circuits to generate differential signals, the embodiments of the present invention can effectively improve the phase shift problem of differential signals in different application scenarios of digital circuits, and at the same time reduce the The complexity of circuit adjustment is reduced, and the microcontroller can be more widely used in high-speed transmission situations. Below, several embodiments are used to further illustrate the digital circuit and the microcontroller using it.

FIG. 4 is a schematic diagram of a digital circuit capable of generating differential signals according to an embodiment of the present invention. Please refer to FIG. 4 first. The digital circuit 100 of this embodiment can be configured to generate a differential signal DFS in a specific working mode, which includes a signal generating circuit 110 and a plurality of input/output connection pads (I/O pads). The signal generating circuit 110 generates the differential signal DFS based on the single-ended input signal S1, wherein the input signal S1 can be, for example, a clock signal, but the present invention is not limited thereto.

The plurality of input and output connection pads are used as an interface for the digital circuit 100 to output signals to the outside, or to receive signals from the outside and transmit them to the internal control circuit. Each input and output connection pad may include a connection pad and an input and output unit, wherein the input and output unit may include, for example, an electrostatic protection circuit, a buffer circuit, a power supply circuit, and the like. In this embodiment, the multiple input and output connections In this embodiment, four of the pads are shown as an example for illustration, such as the input and output connection pads 120_1 - 120_4 , but the present invention is not limited thereto.

Each of the input and output connection pads 120_1˜120_4 has an enable terminal EN and a data output terminal Dout. Each of the input and output connection pads 120_1˜120_4 will determine whether to be enabled according to the signal on the enable terminal EN, and will transmit the signal on the data transmission terminal Dout to the connection pads when enabled. The input and output connection pads 120_1 and 120_2 are respectively coupled to the signal generating circuit 110 through the data output terminal Dout to receive the differential signal DFS composed of the signals S1_b and S1', and determine whether to enable or not according to the enable signal Sen received from the enable terminal EN, The signals S1_b and S1' are substantially in antiphase with each other, and the phase difference is 180 degrees. The I/O pads 120_3 and 120_4 respectively receive the function signals SEL1 and SEL2 through the data output terminal Dout, and receive the enable signal Sen_b through the enable terminal EN. The enabling signals Sen and Sen_b are mutually inverse signals, that is, when the I/O pads 120_1 and 120_2 are enabled, the I/O pads 120_3 and 120_4 will be disabled; conversely, when the I/O pads 120_3 and 120_4 are enabled When enabled, the input and output connection pads 120_1 and 120_2 are disabled.

The enable signals Sen and Sen_b and the function signals SEL1 and SEL2 may be generated, for example, by a function control circuit (not shown). The function control circuit can provide different function signals SEL1 and SEL2 and enable signals Sen and Sen_b to each input and output connection pad 120_1~120_4 according to the user's selection, so as to set the working mode of each input and output connection pad 120_1~120_4 and output value. The function control circuit realizes the function that the user can set the working mode and the output value through the combination of multiple selectable logic circuits, but the present invention is not limited thereto.

Specifically, the digital circuit 100 can be selectively set to output the differential signal DFS or output the function signals SEL1 and SEL2 . When the digital circuit 100 is set to output the differential signal DFS, the function control circuit can generate corresponding enabling signals Sen and Sen_b (for example, 1 and 0), so that the input and output connection pads 120_1 and 120_2 are enabled, and the input and output connection pads 120_3 and 120_4 are disabled. At this time, the I/O pads 120_1 and 120_2 are used to transmit the differential signal DFS. On the other hand, when When the digital circuit 100 is set to output the function signals SEL1 and SEL2, the function control circuit can generate corresponding enable signals Sen and Sen_b (such as 0 and 1), so that the input and output connection pads 120_1 and 120_2 are enabled, and the input and output connection pads 120_3 and 120_4 are disabled.

More specifically, compared with the differential signal generation circuit shown in FIG. 3 , the configuration of this embodiment is to add two input-output connection pads 120_1 and 120_2 in the digital circuit 100, and the two input-output pads 120_2 The connection pads 120_1 and 120_2 are directly connected to the output of the signal generating circuit 110 to receive the signals S1 ′ and S1_b constituting the differential signal DFS, so that the input and output connection pads 120_1 and 120_2 are exclusively used for outputting the differential signal DFS. Since the differential signal DFS is not generated by the functional control circuit, even if the user sets the mode or output value of other input and output pads, it will not cause different phase delays of the differential signal DFS due to the change of the circuit combination path . In other words, the digital circuit 100 of this embodiment can output the differential signal DFS stably maintaining a phase difference of approximately 180 degrees, which is more suitable for applications in high-speed transmission environments.

On the other hand, since the additional I/O pads 120_1 and 120_2 have the same configuration as the other I/O pads 120_3 and 120_4 for outputting the functional signals SEL1 and SEL2 (i.e., adopt the same/similar I/O units), therefore There is no need to design another analog circuit to solve the problem of static electricity protection and driving force of the output signal. In addition, there is no need to adjust the delay of each logic circuit combination in the functional control circuit to match the phase of the differential signal DFS, so the time schedule of circuit design can be greatly reduced.

Moreover, since the I/O pads 120_1 and 120_2 are configured to be enabled/disabled complementary to the two corresponding functional I/O pads 120_3 and 120_4, as long as the I/O pads 120_1 and I/O pads 120_3 Connect to the same pin, and connect the input and output connection pad 120_2 and the input and output connection pad 120_4 to another pin, so that the optional differential signal DFS output function can be realized without increasing the package pins , and will not cause signal conflicts. This part will be further described in the subsequent embodiments.

In some embodiments, the enable control of the input and output connection pads 120_1~120_4 may be, for example, that the function control circuit sets the input and output connection pads 120_1~120_4 to the output mode, and the control of disabling the input and output connection pads 120_1~120_4 may be, for example, It is the function control circuit that sets the input and output connection pads 120_1 - 120_4 as the input mode, but the present invention is not limited thereto. In short, the enable terminals EN of the input/output connection pads 120_1~120_4 may receive other different enable signals to achieve the purpose of input or output, and the input/output connection pads 120_1~120_4 are not only used for output.

In some embodiments, the signal generating circuit 110 may include an inverter 112 and a delay circuit 114 . The inverter 112 has an input terminal and an output terminal, wherein the input terminal of the inverter 112 receives the input signal S1, and the output terminal of the inverter 112 is coupled to the data output terminal Dout of the input-output connection pad 120_1 to transmit the input signal S1. Inverted signal S1_b. The input end of the delay circuit 114 receives the input signal S1 , and the output end of the delay circuit 114 is coupled to the data output end Dout of the I/O connection pad 120_2 . The delay circuit 114 is used to adjust the phase of the input signal S1 to compensate the phase difference between the input signal S1 and the inverted signal S1_b, that is, to reduce the delay DLY shown in FIG. 2 and generate the adjusted signal S1', The adjusted signal S1 ′ and the signal S1_b which is inverse to the signal S1 ′ constitute the differential signal DFS.

Next, an implementation example of a microcontroller using the above-mentioned digital circuit will be described. Please refer to FIG. 5 , which is a schematic diagram of a microcontroller according to an embodiment of the present invention. In this embodiment, the microcontroller 50 includes a plurality of package pins 52 and a digital circuit 200 , wherein the digital circuit 200 includes a signal generating circuit 110 , input and output connection pads 120_1 - 120_4 and a function control circuit 130 .

The signal generating circuit 110 is used to generate a differential signal DFS based on the clock signal CLK, wherein the differential signal DFS includes the clock signal CLK' after phase adjustment by the delay circuit 114 and the clock signal inverse to the clock signal CLK' CLK_b.

The data output terminal Dout of the I/O pad 120_1 is coupled to the output terminal of the inverter 112 of the signal generating circuit 110 to receive the inverted clock signal CLK_b. The data output terminal Dout of the input-output connection pad 120_2 is coupled to the output terminal of the delay circuit 114 of the signal generating circuit 110 to receive the clock signal No. CLK'. The data output terminals Dout of the I/O pads 120_3 and 120_4 are coupled to the function control circuit 130 to receive function signals SEL1 and SEL2 respectively.

The function control circuit 130 is coupled to the enabling terminals EN of the input and output connection pads 120_1 - 120_4 . In addition to generating the function signals SEL1 and SEL2 , the function control circuit 130 also generates enabling signals Sen and Sen_b to control enabling/disabling of each input/output connection pad 120_1 ˜ 120_4 . In this embodiment, the I/O pads 120_1 and 120_2 receive the enable signal Sen from the function control circuit 130 , and the I/O pads 120_3 and 120_4 receive the enable signal Sen_b from the function control circuit 130 , which is inverse to the enable signal Sen. In addition, for the configuration and operation among the signal generating circuit 110 , the input/output connection pads 120_1 ˜ 120_4 , and the function control circuit 130 , please refer to the description of the embodiment in FIG. 4 above, and details will not be repeated here.

In some embodiments, the function control circuit 130 further includes inverters 132_1 and 132_2 for generating the enable signal Sen_b. The input terminal of the inverter 132_1 receives the enable signal Sen, and the output terminal of the inverter 132_1 generates an inverted enable signal Sen' and transmits it to the enable terminal EN of the I/O pad 120_3. The input terminal of the inverter 132_2 receives the enable signal Sen, and the output terminal of the inverter 132_2 generates an inverted enable signal Sen' and transmits it to the enable terminal EN of the I/O pad 120_4. Although the above-mentioned embodiment and FIG. 5 show that two inverters 132_1 and 132_2 are used to generate the enable signal Sen_b required by the input and output pads 120_3 and 120_4 as an example, the present invention is not limited thereto. In other embodiments, the function control circuit 130 can also be implemented by using a single inverter, and the output terminal of the single inverter is simultaneously connected to the enable terminals EN of the input-output connection pads 120_3 and 120_4 .

In this embodiment, the input and output connection pads 120_1 and 120_3 are configured to be commonly coupled to the packaged pin 52_clkb through wire bonding, and the input and output connection pads 120_2 and 120_4 are configured to be commonly coupled to the packaged pin 52_clk through wire bonding . Through the above configuration, when the digital circuit 200 is set to output the differential signal DFS, the input and output pads 120_1 and 120_2 will be enabled in response to the enable signal Sen, and transmit the clock signals CLK_b and CLK to the package pins 52_clkb and 52_clkb respectively. 52_clk, so that the microcontroller 50 can output the differential clock signal DFS to the outside through the package pins 52_clkb and 52_clk circuit. On the other hand, when the digital circuit 200 is configured to output the functional signals SEL1 and SEL2, the I/O pads 120_3 and 120_4 are enabled in response to the enable signal Sen_b, and transmit the functional signals SEL1 and SEL2 to the package pins 52_clkb and 52_clkb respectively. 52_clk, so that the microcontroller 50 can output the function signals SEL1 and SEL2 to the external circuit through the package pins 52_clkb and 52_clk.

In other words, in this embodiment, the input and output connection pads 120_1-120_4 share two package pins 52_clkb and 52_clk to realize the output of two different signal functions, including the input/output function and differential Clock signal output function.

From the perspective of circuit layout, the input and output connection pads 120_1 - 120_4 may be arranged and arranged on a side close to the package pin 52 . In some embodiments, the input and output connection pads 120_1 and 120_2 for outputting the differential signal DFS are located adjacent to each other and configured symmetrically in a mapping manner. That is, some or all of the circuit elements in the I/O pads 120_1 and 120_2 can be symmetrically arranged on both sides of a reference line, and the data output terminals Dout of the I/O pads 120_1 and 120_2 are located on adjacent sides. Such configuration can reduce the phase difference between the clock signals CLK' and CLK_b as much as possible, so that the differential signal DFS has better characteristics.

In some embodiments, the inverter 112 of the signal generating circuit 110 can be arranged in the middle of the input and output connection pads 120_1 and 120_2, and as close as possible to the input and output connection pads 120_1 and 120_2 under the premise of complying with the layout and routing rules. . The inverter 112 is arranged in the middle of the input and output connection pads 120_1 and 120_2, which means that the distance between the position of the layout of the inverter 112 and the data output terminal Dout of the input and output connection pad 120_1 is substantially equal to the distance between the input and output connection pads 120_1. The distance between the data output terminals Dout of the pads 120_2.

In addition, in the embodiment of the present invention, the digital circuit 200 may have more than four input and output connection pads. As shown in Fig. 5, an input and output connection pad can be provided on the upper side of the input and output connection pad 120_3, and an input and output connection pad can be provided on the lower side of the input and output connection pad 120_4, that is, the digital circuit 200 has 6 input and output pads in total. connection pad, the upper side of the input and output connection pad 120_3 is connected with the input and output The two input and output connection pads on the lower side of the pad 120_4 can be used to respectively receive the forward signal and the reverse signal of another set of output differential signals, and can also be used to respectively receive several other functional signals. The function control circuit 130 can provide another enabling signal to control the enabling of the above two input and output connection pads, and at this time the enabling signal Sen_b is not the inversion signal of the enabling signal Sen, but the three enabling signals at three different times Dots represent enabled voltage levels. The above two input and output connection pads can be coupled to the package pins 52_clk and 52_clkb respectively, so that the package pins 52_clk and 52_clkb can output two sets of different output differential signals and a set of multiple function signals according to different enabling signals One of the groups, or output two groups of functional signals and one group of output differential signals.

In summary, compared with the prior art, the digital circuit capable of generating differential signals and the microcontroller using it in the embodiment of the present invention can greatly shorten the circuit because no additional design of analog circuits is required to generate differential signals. design schedule. Furthermore, compared with the traditional mechanism of using digital circuits to generate differential signals, the embodiments of the present invention can effectively improve the phase shift of digital circuits in different application scenarios, and also reduce the The complexity of circuit tuning. In addition, since the packaging pins of the circuit do not need to use extra pins under the design of this embodiment, the microcontroller can also optionally have the ability to output accurate differential clock signals, so it can be used without increasing the cost. Under the premise of reducing or circuit complexity, the microcontroller can be more widely used in high-speed transmission scenarios.

It should be understood that the examples and embodiments described herein are for illustrative purposes only, and that various modifications or changes in view thereof will be suggested to those skilled in the art, and will be included within the spirit and scope of the application and the scope of the appended claims. within range.

100: digital circuit

110: Signal generation circuit

112: Inverter

114: delay circuit

120_1~120_4: input and output connection pads

DFS: Differential Signaling

Dout: data output terminal

EN: enable end

S1: input signal

S1’, S1_b: signal

Sen, Sen_b: enable signal

SEL1, SEL2: function signal

Claims (10)

A digital circuit capable of generating a differential signal, comprising: a signal generating circuit for generating a first signal and a second signal constituting a differential signal based on an input signal, wherein the first signal and the second signal are opposite to each other ; The first and second input-output connection pads are coupled to the signal generating circuit, and determine whether to enable according to the first enable signal; and the third and fourth input-output connection pads are used to determine whether to enable according to the second enable signal ; wherein when the first and the second input and output connection pads are enabled, the first and the second input and output connection pads are respectively used to transmit the first signal and the The second signal, and when the third and the fourth input-output connection pads are enabled, the third and the fourth input-output connection pads are used to transmit a plurality of functional signals; wherein the first one and the third input-output connection pads are commonly coupled to one of the plurality of package pins, and the second and the fourth input-output connection pads are commonly coupled to the other of the plurality of package pins 1. wherein the input signal is a clock signal, and the signal generating circuit includes: an inverter having an input terminal and an output terminal, the input terminal of which receives the clock signal, and the output terminal of which is coupled to the first a data output terminal of an input-output pad for transmitting the first signal, and the first signal is an inverted clock signal; and a delay circuit, used to adjust the phase of the clock signal to generate the second signal, the second signal is the phase-adjusted clock signal, and the phase-adjusted clock signal is the same as the The phases of the anti-phase clock signals are matched with each other, and the delay circuit transmits the adjusted clock signal to the data output end of the second input-output connection pad. The digital circuit capable of generating differential signals as described in Claim 1, further comprising: a function control circuit coupled to the first to the fourth input-output connection pads for generating the first enable signal, the The second activation signal and the plurality of function signals. The digital circuit capable of generating differential signals as described in claim 2 further includes: fifth and sixth input and output connection pads, used to determine whether to enable according to the third enabling signal; wherein the function control circuit further provides the described A third enable signal, and the first, the third and the fifth input and output connection pads are commonly coupled to the package pin, and the second, the fourth and the sixth input and output The connection pads are commonly coupled to the other package pin. The digital circuit capable of generating differential signals as described in Claim 2, wherein the function control circuit includes: at least one inverter having an input terminal and an output terminal, the input terminal of which receives the first enabling signal, and its The output terminal is coupled to the third and the fourth input-output connection pads to output the second enabling signal. The digital circuit capable of generating differential signals as described in Claim 1, wherein the first input-output connection pad and the second input-output connection pad are adjacent and symmetrically arranged in a mapping manner, and the first input The output connection pad and the data output terminal of the second input-output connection pad are located on adjacent sides. The digital circuit capable of generating differential signals as described in Claim 5, wherein the inverter is arranged with a first distance from the data output end of the first input-output connection pad and connected to the second input-output The data output ends of the pads have positions at a second pitch, wherein the first pitch and the second pitch are substantially equal. A microcontroller, comprising: a plurality of packaging pins; a function control circuit for generating a plurality of function signals; a signal generation circuit for generating a first signal and a second signal constituting a differential signal based on a clock signal; the second one and second input-output connection pads, coupled to the signal generating circuit, to respectively receive the first signal and the second signal constituting the differential signal; and third and fourth input-output connection pads, coupled to the function control circuit to respectively receive the plurality of function signals, wherein the first and the third input-output connection pads are commonly coupled to one of the plurality of package pins, and the The second and the fourth input-output connection pads are commonly coupled to another one of the plurality of package pins; Wherein the signal generating circuit includes: an inverter having an input terminal and an output terminal, the input terminal of which receives the clock signal, and the output terminal of which is coupled to the data output terminal of the first input-output connection pad to transmit the The first signal, and the first signal is an inverted clock signal; and a delay circuit, used to adjust the phase of the clock signal to generate the second signal, the second signal is the adjusted phase The phase of the adjusted clock signal matches the phase of the inverted clock signal, wherein the delay circuit transmits the adjusted clock signal to the second input-output connection Pad data output. The microcontroller as described in claim item 7, wherein the function control circuit is further used to generate a first enable signal and a second enable signal that is opposite to the first enable signal, the first and the second An IO pad receives the first enable signal, and the third and fourth IO pads receive the second enable signal. The microcontroller according to claim 8, wherein when said first and said second I/O connection pads are enabled in response to said first enable signal, said first and said second I/O connection pads Pad transmits said first signal and said second signal of said differential signal to said one of them and said other one of said package pins respectively; and when said third and said fourth input When an output pad is enabled in response to the second enable signal, the third and the fourth input-output pads transmit the multiple A functional signal is respectively sent to one of the above-mentioned ones and the other package pin of the above-mentioned ones. The microcontroller according to claim 7, wherein the first to the fourth input and output connection pads are arranged on one side close to the one of them and the other package pin of the said one of them, said The first input and output connection pads are adjacent to the second input and output connection pads and arranged symmetrically in a mapping manner, and the first input and output connection pads and the third input and output connection pads are respectively wired to one of the package pins, and the second input-output connection pad and the fourth input-output connection pad are connected to the other package pin by wire bonding respectively.

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