CN114461463A - Once-open type power-on detection circuit - Google Patents
Once-open type power-on detection circuit Download PDFInfo
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- CN114461463A CN114461463A CN202111666691.5A CN202111666691A CN114461463A CN 114461463 A CN114461463 A CN 114461463A CN 202111666691 A CN202111666691 A CN 202111666691A CN 114461463 A CN114461463 A CN 114461463A
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- 238000001514 detection method Methods 0.000 title claims abstract description 80
- 230000003111 delayed effect Effects 0.000 claims description 4
- 230000003068 static effect Effects 0.000 abstract description 4
- 230000002159 abnormal effect Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000001934 delay Effects 0.000 description 1
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- 230000004048 modification Effects 0.000 description 1
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/2284—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing by power-on test, e.g. power-on self test [POST]
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/12005—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details comprising voltage or current generators
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
- G11C5/147—Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
- G11C5/148—Details of power up or power down circuits, standby circuits or recovery circuits
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/20—Memory cell initialisation circuits, e.g. when powering up or down, memory clear, latent image memory
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Abstract
The invention belongs to the technical field of integrated circuits, and particularly relates to a power-on detection circuit. A once-open type power-on detection circuit comprises a voltage detection circuit, a power supply circuit and a power-on reset signal circuit, wherein the voltage detection circuit is provided with a power supply power end and a power-on reset signal end; the voltage detection circuit further includes: the comparator is characterized in that the in-phase input end is connected with a power supply end through a first resistor, the reverse input end is connected with a detection point voltage end, the output end is a power-on reset signal end, and the control end is connected with a power-on initialization signal end; and the grid electrode of the first MOSFET is connected with the power-on initialization signal end, the drain electrode of the first MOSFET is connected with the first resistor through the second resistor, and the source electrode of the first MOSFET is grounded. The invention can make the voltage detection circuit enter the low power consumption mode after the chip initialization work is finished, thereby avoiding the static power consumption of the voltage detection circuit.
Description
Technical Field
The invention belongs to the technical field of integrated circuits, and particularly relates to a power-on detection circuit.
Background
In both ASIC and MCU circuit designs, the device that has just been powered up has an initialization action. In the initialization action, the data in the nonvolatile register is transferred to various state registers, for example, the configuration of Band Gap is stored in a BGR state register for configuring a reference voltage value after power-on; storing the configuration of the OSC in an OSC status register for configuring the frequency of the OSC; the configuration of the LDO is stored in an LDO register and is used for configuring the VDD power supply voltage of the digital power supply and the like.
However, the initialization action may cause the error of the transferred data due to the following reasons:
1. when the application environment such as the power supply environment is abnormal, the power supply is shaken too much when the action is carried out;
2. in low power consumption designs, power supply detection is not performed, resulting in the action being performed at a lower power supply voltage;
3. some designs in non-volatile registers have too harsh read conditions resulting in data read errors for the non-volatile registers.
Errors such as these can occur:
1. after power-on, abnormal simulation parameters, such as Vref, VDD or OSC and other device parameters, cause that the working voltage of the chip is too high, the chip is burnt or the power consumption is too large;
2. digital part status register exceptions cause digital logic function errors and the like.
In order to prevent the above problems, a power-on/power-off protection circuit with voltage detection is generally added to the ASIC and MCU circuit design, so that the chip operates at a suitable voltage during initialization. Although the voltage detection circuit adopted in the prior art can avoid the problems, the voltage detection circuit brings static power consumption.
Disclosure of Invention
The invention aims to solve the technical problem that static power consumption is brought to the existing voltage detection circuit although the fault of initialization action can be avoided, and aims to provide a one-time open type power-on detection circuit.
A once-open type power-on detection circuit comprises a voltage detection circuit, a power supply circuit and a power-on reset signal circuit, wherein the voltage detection circuit is provided with a power supply power end and a power-on reset signal end;
the voltage detection circuit further includes:
the comparator is characterized in that the in-phase input end of the comparator is connected with the power supply end through a first resistor, the reverse input end of the comparator is connected with the voltage end of the detection point, the output end of the comparator is the power-on reset signal end, and the control end of the comparator is connected with the power-on initialization signal end;
and the grid electrode of the first MOSFET is connected with the power-on initialization signal end, the drain electrode of the first MOSFET is connected with the first resistor through the second resistor, and the source electrode of the first MOSFET is grounded.
After the chip is powered on, the power-on initialization signal input by the power-on initialization signal end is at a high level, the voltage detection circuit enters a working mode, and when:
VDD>Vref*(R2+R1)/R2
when the power-on reset signal end is turned over, the chip starts initialization work;
wherein VDD denotes the power supply terminal voltage, Vref denotes the detection point voltage input from the detection point voltage terminal, R1 denotes the first resistor, and R2 denotes the second resistor;
and when the chip initialization work is finished, the power-on initialization signal input by the power-on initialization signal end is at a low level, and the voltage detection circuit enters a low power consumption mode.
The first MOSFET is an N-channel MOSFET.
The power-on initialization signal input by the power-on initialization signal terminal is provided by an external digital circuit, and the following circuit structure can be adopted:
the voltage detection circuit further includes:
the input end of the delayer is connected with the output end of the comparator;
and the clock input end of the trigger is connected with the output end of the time delay unit, the signal input end of the trigger is grounded, and the signal output end of the trigger is the power-on initialization signal end.
When the chip is powered on, a high level is input into a setting end of the trigger, a power-on initialization signal input into a power-on initialization signal end is the high level, the voltage detection circuit enters a working mode, after the time delay is delayed for a preset time, a voltage signal at an output end of the time delay is turned over, the trigger acts, a signal output end of the trigger outputs the low level, namely the power-on initialization signal input into the power-on initialization signal end is the low level, and the voltage detection circuit enters a low power consumption mode.
The delay time of the delayer is not less than the initialization working time of the chip.
A once-open type power-on detection circuit comprises a voltage detection circuit, a power supply circuit and a power-on reset signal circuit, wherein the voltage detection circuit is provided with a power supply power end and a power-on reset signal end;
the voltage detection circuit further includes:
the grid electrode of the second MOSFET is connected with the power-on initialization signal end, the drain electrode of the second MOSFET is connected with the power supply end, the source electrode of the second MOSFET is connected with one end of a third resistor, and the other end of the third resistor is grounded through a fourth resistor;
the grid electrode of the third MOSFET is connected with the other end of the third resistor, the drain electrode of the third MOSFET is connected with the power supply end through a fifth resistor, and the source electrode of the third MOSFET is grounded;
and the input end of the phase inverter is connected with the drain electrode of the third MOSFET, and the output end of the phase inverter is the power-on reset signal end.
After the chip is powered on, the power-on initialization signal input by the power-on initialization signal end is at a low level, the voltage detection circuit enters a working mode, and when:
VDD>Vth*(R3+R4)/R4
when the power-on reset signal end is turned over, the chip starts initialization work;
wherein VDD represents the voltage at the power supply terminal, Vth represents the threshold voltage of the third MOSFET transistor, R3 represents the third resistor, and R4 represents the fourth resistor;
and when the chip initialization work is finished, the power-on initialization signal input by the power-on initialization signal end is at a high level, and the voltage detection circuit enters a low power consumption mode.
And the second MOSFET and the third MOSFET are both N-channel MOSFET tubes.
The power-on initialization signal input by the power-on initialization signal end is provided by an external digital circuit.
The positive progress effects of the invention are as follows: the invention adopts the once-open type power-on detection circuit, and can enable the voltage detection circuit to enter a low power consumption mode after the initialization work of the chip is completed, thereby avoiding the static power consumption of the voltage detection circuit.
Drawings
FIG. 1 is a schematic circuit diagram of the present invention;
FIG. 2 is a schematic diagram of the optimized circuit connection of FIG. 1;
FIG. 3 is another circuit schematic of the present invention;
FIG. 4 is a flow chart of voltage detection according to the present invention;
FIG. 5 is another exemplary voltage detection flow chart according to the present invention.
Detailed Description
In order to make the technical means, the creation characteristics, the achievement purposes and the effects of the invention easy to understand, the invention is further described in the following combined with the specific drawings.
Referring to fig. 1, a one-time-on power-on detection circuit includes a voltage detection circuit, which includes a power supply terminal VDD, a power-on reset signal terminal por, a comparator U1, a first resistor R1, a detection point voltage terminal, a power-on initialization signal terminal init, a first MOSFET Q1, and a second resistor R2.
The non-inverting input end of the comparator U1 is connected with a power supply end VDD through a first resistor R1, the inverting input end of the comparator U1 is connected with a detection point voltage end, the output end of the comparator U1 is a power-on reset signal end por, and the control end of the comparator U1 is connected with a power-on initialization signal end init. The power-on reset signal end por is used for being connected with an external mathematical circuit, and if the signal of the power-on reset signal end por is turned over, the chip can be initialized under the condition that the chip is in proper voltage. The power-on initialization signal terminal init provides a power-on initialization signal, which is high level 1 when the chip is initialized and is low level 0 after the chip is initialized.
The grid electrode of the first MOSFET Q1 is connected with a power-on initialization signal terminal init, the drain electrode of the first MOSFET Q1 is connected with a power supply end VDD through a second resistor R2 and a first resistor R1 which are connected in series, and the source electrode of the first MOSFET Q1 is grounded. The first MOSFET Q1 is an N-channel first MOSFET.
Referring to fig. 4, after the chip is powered on, the power-on initialization signal input by the power-on initialization signal terminal init is at a high level 1, and the voltage detection circuit enters a working mode when: when VDD is larger than Vref (R2+ R1)/R2, the power-on reset signal end por is turned over, and the chip is considered to be in a proper voltage environment at the moment, so that the chip starts initialization work; after the initialization work of the chip is completed, the power-on initialization signal input by the power-on initialization signal terminal init is at low level 0, at this time, the comparator U1 stops working, and the voltage detection circuit enters a low power consumption mode.
The power-on initialization signal input by the power-on initialization signal terminal init is provided by an external digital circuit, and the following circuit structure can be adopted:
referring to fig. 2, the voltage detection circuit further includes a Delay and a flip-flop Dff. The input end of the delayer is connected with the output end of the comparator U1, and the delayer outputs the signal output by the comparator U1 in a delayed mode. The Delay time of the Delay is not less than the initialization working time of the chip.
A clock input end (clk pin) of the flip-flop Dff is connected to an output end of the Delay, a signal input end (D pin) of the flip-flop Dff is grounded, and a signal output end (Q pin) of the flip-flop Dff is a power-on initialization signal terminal init. The SET terminal (SET pin) of the flip-flop Dff is configured to be high 1.
Referring to fig. 5, after the chip is powered on, the set terminal of the flip-flop Dff inputs a high level 1, and at this time, the signal output terminal of the flip-flop Dff is a high level 1, that is, the power-on initialization signal input by the power-on initialization signal terminal init is a high level 1, and the voltage detection circuit enters a working mode when: when VDD is larger than Vref (R2+ R1)/R2, the power-on reset signal end por is turned over, and the chip is considered to be in a proper voltage environment at the moment, so that the chip starts initialization work; the initialization work of the chip is completed within the Delay time of the delayer, after the delayer delays for a preset time, the voltage signal at the output end A of the delayer is delayed and inverted, the trigger Dff acts, the signal output end of the trigger Dff outputs a low level 0, namely, the power-on initialization signal input by the power-on initialization signal end init is a low level 0, and the voltage detection circuit enters a low power consumption mode.
Referring to fig. 3, the present invention further provides another one-time-on power-on detection circuit, which includes a voltage detection circuit, wherein the voltage detection circuit includes a power supply terminal VDD, a power-on reset signal terminal por, a second MOSFET Q2, a power-on initialization signal terminal initN, a third resistor R3, a fourth resistor R4, a third MOSFET Q3, a fifth resistor R5, and an inverter G1.
The gate of the second MOSFET Q2 is connected to the power-on initialization signal terminal initN, the drain of the second MOSFET Q2 is connected to the power supply terminal VDD, the source of the second MOSFET Q2 is connected to one end of the third resistor R3, and the other end of the third resistor R3 is grounded via the fourth resistor R4. The second MOSFET Q2 is an N-channel MOSFET.
The gate of the third MOSFET Q3 is connected to the other end of the third resistor R3, the drain of the third MOSFET Q3 is connected to the power supply terminal VDD via the fifth resistor R5, and the source of the third MOSFET Q3 is grounded. The third MOSFET Q3 is an N-channel MOSFET. The threshold voltage of the third MOSFET transistor Q2 is the threshold voltage Vth.
The input end of the inverter G1 is connected to the drain of the third MOSFET transistor Q3, and the output end of the inverter G1 is a power-on reset signal end por.
Referring to fig. 4, after the chip is powered on, the power-on initialization signal input by the power-on initialization signal terminal initN is at low level 0, and the voltage detection circuit enters a working mode when: when VDD is greater than Vth (R3+ R4)/R4, the power-on reset signal end por is turned over, and the chip is considered to be in a proper voltage environment at the moment, so that the chip starts initialization work; after the initialization of the chip is completed, the power-on initialization signal input by the power-on initialization signal terminal initN is at a high level 1, and the voltage detection circuit enters a low power consumption mode. The power-on initialization signal input by the power-on initialization signal terminal initN is provided by an external digital circuit.
The foregoing shows and describes the general principles, essential features, and advantages of the invention. It will be understood by those skilled in the art that the present invention is not limited to the embodiments described above, which are described in the specification and illustrated only to illustrate the principle of the present invention, but that various changes and modifications may be made therein without departing from the spirit and scope of the present invention, which fall within the scope of the invention as claimed. The scope of the invention is defined by the appended claims and equivalents thereof.
Claims (10)
1. A once-open type power-on detection circuit comprises a voltage detection circuit, a power supply circuit and a power-on reset signal circuit, wherein the voltage detection circuit is provided with a power supply power end and a power-on reset signal end;
characterized in that, the voltage detection circuit further comprises:
the comparator is characterized in that the in-phase input end of the comparator is connected with the power supply end through a first resistor, the reverse input end of the comparator is connected with the voltage end of the detection point, the output end of the comparator is the power-on reset signal end, and the control end of the comparator is connected with the power-on initialization signal end;
and the grid electrode of the first MOSFET is connected with the power-on initialization signal end, the drain electrode of the first MOSFET is connected with the first resistor through the second resistor, and the source electrode of the first MOSFET is grounded.
2. The one-time-on power-on detection circuit of claim 1, wherein after the chip is powered on, the power-on initialization signal input by the power-on initialization signal terminal is at a high level, and the voltage detection circuit enters an operating mode when:
VDD>Vref*(R2+R1)/R2
when the power-on reset signal end is turned over, the chip starts initialization work;
wherein VDD denotes the power supply terminal voltage, Vref denotes the detection point voltage input from the detection point voltage terminal, R1 denotes the first resistor, and R2 denotes the second resistor;
and when the chip initialization work is finished, the power-on initialization signal input by the power-on initialization signal end is at a low level, and the voltage detection circuit enters a low power consumption mode.
3. The one-time turn-on power-on detection circuit of claim 1, wherein the first MOSFET transistor is an N-channel MOSFET transistor.
4. The one-time-on power-on detection circuit of claim 1, wherein the power-on initialization signal input by the power-on initialization signal terminal is provided by an external digital circuit.
5. The one-time-on power-up detection circuit of any one of claims 1 to 3, wherein the voltage detection circuit further comprises:
the input end of the delayer is connected with the output end of the comparator;
and the clock input end of the trigger is connected with the output end of the time delay unit, the signal input end of the trigger is grounded, and the signal output end of the trigger is the power-on initialization signal end.
6. The one-off power-on detection circuit as claimed in claim 5, wherein after the chip is powered on, the set terminal of the flip-flop inputs a high level, the power-on initialization signal input by the power-on initialization signal terminal is a high level, the voltage detection circuit enters an operating mode, after the delay time is delayed for a preset time, the voltage signal at the output terminal of the delay time is inverted, the flip-flop operates, the signal output terminal of the flip-flop outputs a low level, that is, the power-on initialization signal input by the power-on initialization signal terminal is a low level, and the voltage detection circuit enters a low power consumption mode.
7. The one-time-on power-on detection circuit of claim 5, wherein the delay time of the delay is not less than the initialization operating time of the chip.
8. A once-open type power-on detection circuit comprises a voltage detection circuit, a power supply circuit and a power-on reset signal circuit, wherein the voltage detection circuit is provided with a power supply power end and a power-on reset signal end;
characterized in that, the voltage detection circuit further comprises:
the grid electrode of the second MOSFET is connected with the power-on initialization signal end, the drain electrode of the second MOSFET is connected with the power supply end, the source electrode of the second MOSFET is connected with one end of a third resistor, and the other end of the third resistor is grounded through a fourth resistor;
the grid electrode of the third MOSFET is connected with the other end of the third resistor, the drain electrode of the third MOSFET is connected with the power supply end through a fifth resistor, and the source electrode of the third MOSFET is grounded;
and the input end of the phase inverter is connected with the drain electrode of the third MOSFET, and the output end of the phase inverter is the power-on reset signal end.
9. The one-time-on power-on detection circuit of claim 8, wherein after the chip is powered on, the power-on initialization signal input by the power-on initialization signal terminal is at a low level, and the voltage detection circuit enters an operating mode when:
VDD>Vth*(R3+R4)/R4
when the power-on reset signal end is turned over, the chip starts initialization work;
wherein VDD represents the voltage of the power supply terminal, Vth represents the threshold voltage of the third MOSFET transistor, R3 represents the third resistor, and R4 represents the fourth resistor;
and when the chip initialization work is finished, the power-on initialization signal input by the power-on initialization signal end is at a high level, and the voltage detection circuit enters a low power consumption mode.
10. The one-time-on power-on detection circuit of claim 8, wherein the second MOSFET and the third MOSFET are both N-channel MOSFET transistors;
the power-on initialization signal input by the power-on initialization signal end is provided by an external digital circuit.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202111666691.5A CN114461463A (en) | 2021-12-31 | 2021-12-31 | Once-open type power-on detection circuit |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202111666691.5A CN114461463A (en) | 2021-12-31 | 2021-12-31 | Once-open type power-on detection circuit |
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| CN114461463A true CN114461463A (en) | 2022-05-10 |
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| CN202111666691.5A Pending CN114461463A (en) | 2021-12-31 | 2021-12-31 | Once-open type power-on detection circuit |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116647216A (en) * | 2023-05-31 | 2023-08-25 | 成都电科星拓科技有限公司 | Method, circuit, phase-locked loop and chip for solving POR and LDO power-on sequence |
| CN117406699A (en) * | 2023-12-12 | 2024-01-16 | 苏州萨沙迈半导体有限公司 | MCU power-on self-checking circuit, chip and electronic equipment |
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