CN110971218A - Power-on reset circuit - Google Patents

Power-on reset circuit Download PDF

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CN110971218A
CN110971218A CN201911311910.0A CN201911311910A CN110971218A CN 110971218 A CN110971218 A CN 110971218A CN 201911311910 A CN201911311910 A CN 201911311910A CN 110971218 A CN110971218 A CN 110971218A
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transistor
circuit
resistor
voltage
voltage detection
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CN110971218B (en
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刘勇江
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Chengdu Haiguang Microelectronics Technology Co Ltd
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Chengdu Haiguang Microelectronics Technology Co Ltd
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/22—Modifications for ensuring a predetermined initial state when the supply voltage has been applied
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/16—Modifications for eliminating interference voltages or currents
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/16—Modifications for eliminating interference voltages or currents
    • H03K17/161—Modifications for eliminating interference voltages or currents in field-effect transistor switches
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/22—Modifications for ensuring a predetermined initial state when the supply voltage has been applied
    • H03K17/223—Modifications for ensuring a predetermined initial state when the supply voltage has been applied in field-effect transistor switches
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/22—Modifications for ensuring a predetermined initial state when the supply voltage has been applied
    • H03K2017/226—Modifications for ensuring a predetermined initial state when the supply voltage has been applied in bipolar transistor switches

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Abstract

The utility model provides a power-on reset circuit of high accuracy low-power consumption, including voltage detection circuit and comparator. The voltage detection circuit is used for detecting power supply voltage and comprises a first output end, a second output end, a first branch circuit and a second branch circuit, wherein the first branch circuit and the second branch circuit are connected between the ground and the power supply voltage in parallel; the non-inverting input end of the comparator is connected to the first output end of the voltage detection circuit, and the inverting input end of the comparator is connected to the second output end of the voltage detection circuit and used for outputting a power-on reset signal. The power-on reset circuit disclosed by the invention does not need reference voltage and can generate a power-on reset signal with low trigger voltage.

Description

Power-on reset circuit
Technical Field
The disclosure relates to the technical field of circuits, in particular to a power-on reset circuit.
Background
A Power On Reset (POR) circuit is a very important component of a System On Chip (SOC), and is mainly used for resetting or resetting the current state of each module when the System is started. With the advanced process, the power supply voltage in the SOC system is lower, and the general POR circuit requires that the POR trigger voltage must be greater than 1.25V, which is poor in precision and large in power consumption, and cannot adapt to the SOC system. Therefore, a power-on reset circuit capable of realizing high accuracy and low power consumption of a low POR trigger voltage is required.
Disclosure of Invention
In view of this, the present disclosure provides a voltage detection circuit and a power-on reset circuit including the same, which can effectively solve the problems of high voltage, large power consumption and low reliability of a POR trigger point of a conventional power-on reset circuit.
The following presents a simplified summary of the disclosure in order to provide a basic understanding of some aspects of the disclosure. It should be understood that this summary is not an exhaustive overview of the disclosure. It is not intended to identify key or critical elements of the disclosure or to delineate the scope of the disclosure. Its sole purpose is to present some concepts in a simplified form as a prelude to the more detailed description that is discussed later.
According to a first aspect of the present disclosure, there is provided a power-on-reset circuit including a voltage detection circuit and a comparator. The voltage detection circuit is used for detecting the power supply voltage and comprises a first output end, a second output end, a first branch circuit and a second branch circuit, wherein the first branch circuit and the second branch circuit are connected between the ground and the power supply voltage in parallel. Specifically, the first branch comprises a first voltage dividing resistor and a first adjustable resistor which are connected in series, the second branch comprises a second voltage dividing resistor and a second adjustable resistor which are connected in series, the first voltage dividing resistor and the second voltage dividing resistor have the same resistance value, and the first adjustable resistor and the second adjustable resistor have the same resistance value; a first voltage dividing resistor of the first branch circuit is connected with a first transistor and a third resistor which are connected in series with each other in parallel to form a first parallel circuit, one end of the first parallel circuit is grounded, and the other end of the first parallel circuit is connected to a first output end of the voltage detection circuit; and a second voltage-dividing resistor of the second branch is connected with a second transistor in parallel to form a second parallel circuit, one end of the second parallel circuit is grounded, and the other end of the second parallel circuit is connected to the second output end of the voltage detection circuit. The non-inverting input end of the comparator is connected to the first output end of the voltage detection circuit, and the inverting input end of the comparator is connected to the second output end of the voltage detection circuit and used for outputting a power-on reset signal.
In some embodiments, the area of the first transistor may be n times that of the second transistor, n being an integer equal to or greater than 2.
In some embodiments, the trigger voltage of the power-on-reset circuit may be adapted to:
Figure BDA0002324758580000021
wherein, V1Is the threshold voltage of the first transistor, V2Is the threshold voltage, R, of the second transistor3、R1、RadThe resistance values of the third resistor, the first divider resistor and the first adjustable resistor are respectively.
In some embodiments, the power-on-reset circuit may further include a schmitt trigger and a buffer circuit, which may include one or more buffers. The output end of the comparator can be connected to the input end of the Schmitt trigger, the output end of the Schmitt trigger can be connected to the buffer circuit, and the buffer circuit is used for outputting a power-on reset signal.
In some embodiments, the first adjustable resistor may include a plurality of series resistors, the second adjustable resistor may include a plurality of series resistors, a switch is connected in parallel to both ends of one of the series resistors of the first adjustable resistor and both ends of one of the series resistors of the second adjustable resistor, and the buffer circuit may be further configured to output a power-on reset signal to the switch to control the series resistor access circuit or the short circuit.
In some embodiments, the power-on reset circuit may further include a pulse generating circuit connected to the output terminal of the buffer circuit, for generating a pulse signal of a certain width as the power-on reset signal.
According to a second aspect of the present disclosure, there is provided a voltage detection circuit for detecting a supply voltage, comprising first and second output terminals, first and second branches connected in parallel between ground and the supply voltage. The first branch circuit comprises a first voltage-dividing resistor and a first adjustable resistor which are connected in series, the second branch circuit comprises a second voltage-dividing resistor and a second adjustable resistor which are connected in series, the first voltage-dividing resistor and the second voltage-dividing resistor have the same resistance value, and the first adjustable resistor and the second adjustable resistor have the same resistance value; the first voltage dividing resistor of the first branch circuit is connected with a first transistor and a third resistor which are connected in series with each other in parallel to form a first parallel circuit, one end of the first parallel circuit is grounded, and the other end of the first parallel circuit is connected to the first output end of the voltage detection circuit; and a second voltage-dividing resistor of the second branch is connected with a second transistor in parallel to form a second parallel circuit, one end of the second parallel circuit is grounded, and the other end of the second parallel circuit is connected to the second output end of the voltage detection circuit.
In some embodiments, the area of the first transistor may be n times that of the second transistor, n being an integer equal to or greater than 2.
In some embodiments, the first transistor may be a first PMOS transistor, a drain of the first PMOS transistor is connected to one end of a third resistor, a source and a gate of the first PMOS transistor are grounded, and the other end of the third resistor is connected to the first output terminal of the voltage detection circuit; the second transistor is a second PMOS tube, the drain electrode of the second PMOS tube is connected to the second output end of the voltage detection circuit, and the source electrode and the grid electrode of the second PMOS tube are grounded.
In some embodiments, the first transistor may be a first NMOS transistor, a source and a gate of the first NMOS transistor are connected to one end of a third resistor, a drain of the first NMOS transistor is grounded, and the other end of the third resistor is connected to the first output terminal of the voltage detection circuit; the second transistor may be a second NMOS transistor, a source and a gate of the second NMOS transistor are connected to the second output terminal of the voltage detection circuit, and a drain of the second NMOS transistor is grounded.
In some embodiments, the first transistor may be a first PNP transistor, an emitter of the first PNP transistor is connected to one end of the third resistor, a collector and a base of the first PNP transistor are grounded, and the other end of the third resistor is connected to the first output terminal of the voltage detection circuit; the second transistor may be a second PNP transistor, an emitter of the second PNP transistor is connected to the second output terminal of the voltage detection circuit, and a collector and a base are grounded.
In some embodiments, the first transistor may be a first NPN transistor, a collector and a base of the first NPN transistor are connected to one end of a third resistor, an emitter of the third resistor is grounded, and the other end of the third resistor is connected to the first output terminal of the voltage detection circuit; the second transistor may be a second NPN transistor, a collector and a base of which are connected to the second output terminal of the voltage detection circuit, and an emitter of which is grounded.
According to a third aspect of the present disclosure, there is provided a system-on-chip comprising the power-on-reset circuit provided according to the first aspect of the present disclosure.
According to the power-on reset circuit, the voltage detection circuit and the comparator which do not need reference voltage are adopted to generate the power-on reset signal, the area of the power-on reset circuit is effectively saved, the power consumption is reduced, and the trigger voltage of the power-on reset circuit can be effectively reduced and the reset precision is improved by adjusting the access resistance value of the voltage detection circuit.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings needed to be used in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings without creative efforts. The foregoing and other objects, features and advantages of the application will be apparent from the accompanying drawings. Like reference numerals refer to like parts throughout the drawings. The drawings are not intended to be to scale as practical, emphasis instead being placed upon illustrating the subject matter of the present application.
Fig. 1 is a circuit schematic diagram of a power-on reset circuit of the related art.
Fig. 2 is a circuit schematic diagram of another power-on reset circuit of the related art.
Fig. 3 is a schematic structural diagram of a voltage detection circuit according to an embodiment of the present disclosure.
Fig. 4 is a circuit schematic diagram of a voltage detection circuit provided according to an embodiment of the present disclosure.
Fig. 5 is a circuit schematic diagram of another voltage detection circuit provided in accordance with an embodiment of the present disclosure.
Fig. 6 is a circuit schematic diagram of still another voltage detection circuit provided according to an embodiment of the present disclosure.
Fig. 7 is a circuit schematic diagram of still another voltage detection circuit provided in accordance with an embodiment of the present disclosure.
Fig. 8 is a graph of the output voltage of the voltage detection circuit as a function of the supply voltage according to an embodiment of the disclosure.
Fig. 9 is a circuit schematic of a power-on-reset circuit according to an embodiment of the disclosure.
Fig. 10 is a timing diagram of the voltage at each node of the power-on-reset circuit according to an embodiment of the disclosure.
Detailed Description
The technical solutions in the embodiments of the present application will be described below with reference to the drawings in the embodiments of the present application.
It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined and explained in subsequent figures. Meanwhile, relational terms such as "first," "second," and the like may be used solely in the description herein to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
Further, the term "and/or" in the present application is only one kind of association relationship describing the associated object, and means that three kinds of relationships may exist, for example, a and/or B may mean: a exists alone, A and B exist simultaneously, and B exists alone.
Exemplary embodiments of the present disclosure will be described below with reference to the accompanying drawings. In the interest of clarity and conciseness, not all features of an actual embodiment are described in the specification. It will of course be appreciated that in the development of any such actual embodiment, numerous implementation-specific decisions may be made to achieve the developers' specific goals, such as compliance with system-related and business-related constraints, which will vary from one implementation to another.
Here, it should be further noted that, in order to avoid obscuring the present disclosure with unnecessary details, only the device structure closely related to the scheme according to the present disclosure is shown in the drawings, and other details not so related to the present disclosure are omitted.
It is to be understood that the disclosure is not limited to the described embodiments, as described below with reference to the drawings. In this context, embodiments may be combined with each other, features may be replaced or borrowed between different embodiments, one or more features may be omitted in one embodiment, where feasible.
Fig. 1 shows a power-on reset circuit commonly used in the related art, which mainly includes a resistor and a capacitor, and charges the capacitor through the resistor and generates a power-on reset signal when the voltage of the capacitor reaches the on-state voltage of the buffer. Another common power-on reset circuit used in the prior art is a circuit structure that employs a complex reference voltage in combination with a comparator, and the comparator compares a power supply voltage with the reference voltage to generate a power-on reset signal. The former has the defects of poor reset precision and low reliability, and the latter has the defects of complex structure and large power consumption.
On the other hand, as shown in fig. 2, the POR trigger voltage of the power-on reset circuit in the prior art is larger than 1.25V, however, as the process advances and the power supply voltage of the system on chip decreases, the POR trigger voltage needs to be small enough to meet the system requirement.
In order to solve the above problem, embodiments of the present disclosure provide a voltage detection circuit and a power-on reset circuit including the voltage detection circuit. First, a voltage detection circuit provided in an embodiment of the present disclosure is described below.
Fig. 3 shows a schematic structural diagram of a voltage detection circuit 300 provided according to an embodiment of the present disclosure, where the voltage detection circuit 300 is used for detecting a power supply voltage. The voltage detection circuit 300 is connected to the power supply voltage301 and ground 302, there are two outputs: a first output 310 and a second output 311. The first output terminal 310 and the second output terminal 311 may respectively output respective detection voltages V in response to a circuit power-up procedure, i.e., a power supply voltage rising from 0Vout1And Vout2And is used for generating a power-on reset signal. For example, as described in detail below, the voltage V at the first output terminal 310out1And the voltage V of the second output terminal 311out2Is input to the comparator, generates a power-on reset signal by the comparator, and does not require a reference voltage.
As shown in fig. 3, the voltage detection circuit 300 includes a first branch L connected in parallel between a power supply voltage 301 and a ground 3021And a second branch L2Wherein the first branch L1Comprises a first voltage dividing resistor 303 and a first adjustable resistor 304 connected in series, and a second branch L2Comprising a second voltage dividing resistor 305 and a second adjustable resistor 306 in series.
First branch L1The first voltage dividing resistor 303 is connected in parallel with a first transistor 307 and a third resistor 308 connected in series to form a first parallel circuit P1First parallel circuit P1One terminal is connected to ground 302 and the other terminal is connected to a first output terminal 310 of the voltage detection circuit. Second branch L2Is connected in parallel with a second transistor 309 to form a second parallel circuit P2Second parallel circuit P2One end is connected to ground and the other end is connected to the second output terminal 311 of the voltage detection circuit.
In the embodiment of the present disclosure, the first voltage-dividing resistor 303 and the second voltage-dividing resistor 305 have the same resistance value, and the first adjustable resistor 304 and the second adjustable resistor 306 have the same resistance value. Hereinafter, by adjusting the resistance values of first adjustable resistor 304 and second adjustable resistor 306, the power voltage value when the voltages of first output terminal 310 and second output terminal 311 are equal, that is, the trigger voltage V of the power-on reset circuit can be adjustedTrig。
The purpose of this is to equalize the currents through the first and second voltage-dividing resistors 303 and 305 and also equalize the currents through the first and second tunable resistors 304 and 306 when the output voltages of the first and second output terminals 310 and 311 of the voltage detection circuit 300 are equal, because the current through the first transistor 307 is the difference between the current through the first tunable resistor 304 and the current through the first voltage-dividing resistor 303 and the current through the second transistor 309 is the difference between the current through the second tunable resistor 306 and the current through the second voltage-dividing resistor 305. Therefore, the current through the first transistor 307 can be made equal to the current through the second transistor 309.
In some possible embodiments, the area of the first transistor 307 may be larger than the second transistor, for example, n times the area of the second transistor 309, where n is an integer equal to or larger than 2. In some possible embodiments, the first transistor 307 and the second transistor 309 may be a P-type metal-oxide semiconductor field effect transistor (PMOS transistor) or an N-type metal-oxide semiconductor field effect transistor (NMOS transistor), and may also be a PNP-type transistor or an NPN-type transistor. Fig. 4-7 illustrate four different voltage detection circuits provided according to embodiments of the present disclosure, respectively, depending on the type of transistors employed.
As shown in fig. 4, the present disclosure provides a voltage detection circuit 400, which includes a first branch L connected in parallel between a power supply voltage and ground1And a second branch L2Wherein the first branch L1Comprising a first series-connected voltage-dividing resistor R1And a first adjustable resistance Rad1Second branch L2Comprising a second voltage-dividing resistor R connected in series2And a second adjustable resistance Rad2. First voltage dividing resistor R1And a second voltage dividing resistor R2Has the same resistance value, and the first adjustable resistor Rad1And a second adjustable resistance Rad2The resistance values of (a) and (b) are the same.
As shown, the first divider resistor R1Are connected in parallel with first transistors MP connected in series1And a third resistor R3First transistor MP1Is a PMOS transistor, a first transistor MP1Is connected to a third resistor R3A source and a gate are grounded, and a third resistor R3The other end of which is connected to the second end of the voltage detection circuitAn output terminal Out1. Second voltage dividing resistor R2Both ends of the first transistor MP are connected in parallel with a second transistor MP2Second transistor MP2Is a PMOS transistor, a second transistor MP2Is connected to a second output terminal Out of the voltage detection circuit2And the source and gate are grounded.
As shown in fig. 5, the present disclosure provides another voltage detection circuit 500, which includes a first branch L connected in parallel between a power supply voltage and ground1And a second branch L2Wherein the first branch L1Comprising a first series-connected voltage-dividing resistor R1And a first adjustable resistance Rad1Second branch L2Comprising a second voltage-dividing resistor R connected in series2And a second adjustable resistance Rad2. First voltage dividing resistor R1And a second voltage dividing resistor R2Has the same resistance value, and the first adjustable resistor Rad1And a second adjustable resistance Rad2The resistance values of (a) and (b) are the same.
As shown, the first divider resistor R1Are connected in parallel with first transistors MP connected in series1And a third resistor R3First transistor MP1Is an NMOS transistor, a first transistor MP1Is connected to a third resistor R3Has a drain grounded, and a third resistor R3Is connected to a first output terminal Out of the voltage detection circuit1(ii) a Second voltage dividing resistor R2Both ends of the first transistor MP are connected in parallel with a second transistor MP2Second transistor MP2Is an NMOS transistor, a second transistor MP2Is connected to the second output terminal Out of the voltage detection circuit2And the drain is grounded.
As shown in fig. 6, the present disclosure provides another voltage detection circuit 600, which includes a first branch L connected in parallel between a power supply voltage and ground1And a second branch L2Wherein the first branch L1Comprising a first series-connected voltage-dividing resistor R1And a first adjustable resistance Rad1Second branch L2Comprising a second voltage-dividing resistor R connected in series2And a second adjustable resistance Rad2. First voltage dividing resistor R1And a firstTwo divider resistor R2Has the same resistance value, and the first adjustable resistor Rad1And a second adjustable resistance Rad2The resistance values of (a) and (b) are the same.
First voltage dividing resistor R1Are connected in parallel with first transistors Q connected in series with each other1And a third resistor R3A first transistor Q1Is a PNP triode, a first transistor Q1Is connected to a third resistor R3A collector and a base are grounded, and a third resistor R3Is connected to a first output terminal Out of the voltage detection circuit1(ii) a Second voltage dividing resistor R2Are connected in parallel with a second transistor Q2A second transistor Q2Is a PNP triode, a second transistor Q2Is connected to a second output terminal Out of the voltage detection circuit2And the collector and the base are grounded.
As shown in fig. 7, the present disclosure provides still another voltage detection circuit 700, which includes a first branch L connected in parallel between a power voltage and ground1And a second branch L2Wherein the first branch L1Comprising a first series-connected voltage-dividing resistor R1And a first adjustable resistance Rad1Second branch L2Comprising a second voltage-dividing resistor R connected in series2And a second adjustable resistance Rad2. First voltage dividing resistor R1And a second voltage dividing resistor R2Has the same resistance value, and the first adjustable resistor Rad1And a second adjustable resistance Rad2The resistance values of (a) and (b) are the same.
As shown, the first divider resistor R1Are connected in parallel with first transistors Q connected in series with each other1And a third resistor R3A first transistor Q1Is an NPN triode, a first transistor Q1Is connected to a third resistor R3One end of (3), the emitter is grounded, and a third resistor R3Is connected to a first output terminal Out of the voltage detection circuit1(ii) a Second voltage dividing resistor R2Are connected in parallel with a second transistor Q2A second transistor Q2Is an NPN triode, and a second transistor Q2Is connected to the collector and the baseSecond output terminal Out of voltage detection circuit2And the emitter is grounded.
FIG. 8 shows an output voltage V of the voltage detection circuit provided by the embodiment of the disclosureout1And Vout2Graph with supply voltage. The operation of the voltage detection circuit provided in this embodiment will be specifically described below with reference to fig. 3 and 8.
First stage, V from originout1And Vout2The phase in which the curves of (a) substantially overlap: in a process (e.g., power-on) in which the power supply voltage gradually rises from 0V, when the power supply voltage is still small, the first transistor 307 and the second transistor 309 are not turned on, and the voltage V of the first output terminal 310 of the voltage detection circuitout1The voltage V of the second output terminal 311 of the voltage detection circuit is the voltage of the first voltage-dividing resistor 303out2The voltage of the second voltage-dividing resistor 305 is the voltage V at the first output terminal 310 of the stage voltage detection circuit, since the first voltage-dividing resistor 303 and the second voltage-dividing resistor 305 have the same resistance, and the first adjustable resistor 304 and the second adjustable resistor 306 have the same resistanceout1And the voltage V of the second output terminal 311out2Are equal.
A second stage in which V isout1And Vout2In the case of equality, since the first divider resistor 303 and the second divider resistor 305 have equal resistance values, and the first adjustable resistor 304 and the second adjustable resistor 306 have equal resistance values, the currents passing through the first transistor 307 and the second transistor 309 are equal. As the power supply voltage increases, the current through the first transistor 307 and the second transistor 309 becomes larger gradually, and the first transistor 307 and the second transistor 309 are turned on. The first transistor 307 and the second transistor 309 may have different areas in the embodiment of the present disclosure, for example, the area of the first transistor 307 is n times (n is an integer greater than or equal to 2) the area of the second transistor 309, so that the threshold voltage V of the first transistor 307th1Is less than the threshold voltage V of the second transistor 309th2. In addition, considering that the power voltage is still relatively small at this stage, the current flowing through the third resistor 308 is relatively small, the voltage drop across the third resistor 308 is negligible, and therefore the voltage detection is performedThe voltage V at the first output 310 of the circuitout1Is the threshold voltage V of the first transistor 307th1Voltage V at the second output terminal 311 of the voltage detection circuitout2Is the threshold voltage V of the second transistor 309th2At Vth1Less than Vth2In the case of (1), the voltage V of the first output terminal 310 of the voltage detection circuitout1Is less than the voltage V of the second output terminal 311out2。
And a third stage: the supply voltage continues to increase and the current through the third resistor 308 gradually increases, the voltage across the third resistor 308 being negligible at this stage. At this time, the voltage V of the first output terminal 310 of the voltage detection circuitout1Is the voltage of the third resistor 308 and the threshold voltage V of the first transistor 307th1Sum, voltage V of second output terminal 311 of the voltage detection circuitout2Is the threshold voltage V of the second transistor 309th2. When the current passing through the third resistor 308 is large to a certain degree, the voltage V at the first output terminal 310 of the voltage detection circuit can be enabledout1And the voltage V of the second output terminal 311out2Equal and then as the supply voltage increases, the voltage V at the first output 310 of the voltage detection circuitout1Will be greater than the voltage V of the second output terminal 311out2。
According to the above description, the voltage detection circuit according to the embodiment of the disclosure is applied to the power-on reset circuit, and the voltage V of the first output terminal 310 of the voltage detection circuit can be utilizedout1And the voltage V of the second output terminal 311out2A power-on reset signal is generated.
The power-on reset circuit provided by the embodiment of the present disclosure will be described below. As shown in fig. 9, the power-on reset circuit 900 provided in the embodiment of the present disclosure includes a voltage detection circuit 901, a comparator 902, a schmitt trigger 903 and a buffer circuit 904, where the voltage detection circuit 901 is used for detecting a power supply voltage and includes a first branch L connected in parallel between ground and the power supply voltage1And a second branch L2First branch L1Comprising a first series-connected voltage-dividing resistor R11And a first adjustable resistance Rad1Second branch L2Comprising a second voltage-dividing resistor connected in seriesR21And a second adjustable resistance Rad2First divider resistor R11And a second voltage dividing resistor R21Has the same resistance value, and the first adjustable resistor Rad1And a second adjustable resistance Rad2The resistance values of (a) and (b) are the same. In this embodiment, the first adjustable resistor Rad1Can be composed of three resistors R12、R13、R14Formed by connecting in series a second adjustable resistor Rad2Can be composed of three resistors R22、R23、R24Are connected in series, wherein the resistance R14And a resistance R24May be provided as an adjustable resistance.
First branch L1First voltage dividing resistor R11Connected in parallel with first transistors MP connected in series1And a third resistor R3To form a first parallel circuit P1The first parallel circuit P1One end of which is grounded and the other end of which is connected to a first output terminal Out of the voltage detection circuit 9011(ii) a Second branch L2Second voltage-dividing resistor R21Connected in parallel with a second transistor MP2To form a second parallel circuit P2The second parallel circuit P2One end of which is grounded and the other end of which is connected to a second output terminal Out of the voltage detection circuit 9012。
In the embodiment of the present disclosure, the first adjustable resistor Rad1Of (3) a series resistance R13And a second adjustable resistor Rad2Of (3) a series resistance R23Both ends of the switch are connected in parallel with a switch SW1Switch SW1Can control the resistance R13And R23Access to the circuit or short circuit.
In the embodiment of the present disclosure, the first transistor MP1May be the second transistor MP28 times of the first transistor MP, and the first transistor MP1And a second transistor MP2May be a PMOS transistor.
It should be noted that, as described in the foregoing description of the voltage detection circuit in the embodiment of the present disclosure, a person skilled in the art should know that, on the premise of ensuring that the area of the first transistor is larger than that of the second transistor, the area of the first transistor may also be other integer multiples of that of the second transistor, which is determined according to the structure and function of the power-on reset circuit. In addition, the arrangement of the first transistor and the second transistor is not limited to a PMOS transistor, and may also be an NMOS transistor, a PNP triode, an NPN triode, or the like.
In the embodiment of the present disclosure, the non-inverting input of the comparator 902 is connected to the first output terminal Out of the voltage detection circuit 9011The inverting input terminal is connected to the second output terminal Out of the voltage detection circuit 9012The output end is connected with the input end of the Schmitt trigger 903; the output end of the Schmitt trigger 903 is connected with the input end of the buffer circuit 904; the buffer circuit 904, which includes one or more buffers, outputs a power-on reset signal. The buffer circuit 904 may also output a power-on reset signal to the voltage detection circuit 901 by controlling the switch SW1To control the resistance R13Access to the circuit or short circuit.
In the embodiment of the disclosure, the buffer circuit 904 may include two buffers, and the buffer 1 outputs the first buffer signal VBuf1To the voltage detection circuit 901 to detect the voltage by controlling the switch SW1To control the resistance R13And R23The buffer 2 outputs a second buffer signal V when the circuit is switched on or short-circuitedBuf2As a power-on reset signal.
It is noted that, alternatively, the first adjustable resistor R may also bead1Of (3) a series resistance R13Both ends are connected in parallel with a switch SW1Switch SW1Can control the resistance R13Access to a circuit or short circuit; second adjustable resistor Rad2Of (3) a series resistance R23Both ends are connected in parallel with a switch SW2Switch SW2Can control the resistance R23Access to the circuit or short circuit. The buffer circuit 904 may also output the power-on reset signals to the switches SW of the voltage detection circuit 901, respectively1And SW2By controlling the switch SW1And SW2To control the resistance R13And R23Access to the circuit or short circuit.
In the embodiment of the present disclosure, the power-on reset circuit may further include a pulse generating circuit 905, configured to further process the signal output by the buffer circuit 904, so as to generate a pulse signal with a certain pulse width, so as to provide the pulse signal for different systems. In the embodiment of the disclosure, the pulse generating circuit 905 further processes the second buffered signal output from the buffer 2 to generate a pulse signal with a certain width.
Fig. 10 shows a voltage timing diagram of each node of the power-on-reset circuit of the embodiment of the present disclosure. The operation principle of the power-on reset circuit provided by the embodiment of the present disclosure will be described in detail with reference to fig. 8, 9 and 10.
In the process of the power supply voltage rising from 0V to the normal voltage, the voltage detection circuit 901 detects the power supply voltage and generates a first output voltage VOut1And a second output terminal voltage VOut2. Voltage V at first output terminalOut1As an input signal to the non-inverting input of the comparator 902, a voltage V at the second outputOut2As an input signal to the inverting input of the comparator 902, at a first output terminal voltage VOut1Less than the second output voltage VOut2In the case of (2), the comparator 902 outputs a low level, and no power-on reset signal is generated. As the power supply voltage rises, the voltage V at the first output terminal of the voltage detection circuit 901Out1Will gradually equal to or greater than the voltage V at the second output endOut2When the voltage V of the first output terminal is higher than the voltage V of the second output terminalOut1Equal to the voltage V of the second output terminalOut2The comparator 902 is triggered and then at a first output voltage VOut1Greater than the second output voltage VOut2In the case of (2), the output of the comparator 902 is kept at a high level. Voltage V at first output terminal of voltage detection circuit 901Out1Equal to the voltage V of the second output terminalOut2When the power-on reset circuit is triggered, the value of the power supply voltage is referred to as the trigger voltage of the power-on reset circuit, i.e., V shown in fig. 8Trig。
The power-on reset circuit trigger voltage V will be described in detail belowTrigThe method of (3). It will be appreciated that, via this calculation method, it is possible to adjust the adjustable resistance Rad1And Rad2To configure the trigger voltage V of the power-on reset circuitTrig。
Voltage V at first output terminal of voltage detection circuit 901Out1Equal to the voltage V of the second output terminalOut2While flowing through the first adjustable resistor Rad1The current of (a) is:
Figure BDA0002324758580000131
from this, the first adjustable resistance R can be calculatedad1The upper and supply voltages are respectively:
Figure BDA0002324758580000141
VAVDD＝V2+Vad1(3)
then, combining the above formula, the trigger voltage VTrig of the power-on reset circuit can be calculated as:
Figure BDA0002324758580000142
wherein, V1Is a first transistor MP1Threshold voltage of, V2Is a second transistor MP2Threshold voltage of R3、R1、RadAre respectively a third resistor R3A first voltage dividing resistor R11A first adjustable resistor Rad1The resistance value of (2).
From the formula (4), the trigger voltage V of the power-on reset circuit is shownTrigFrom the second transistor MP2Threshold voltage V of2Second transistor MP2Threshold voltage of and the first transistor MP1Difference V of threshold voltages of2-V1And a first adjustable resistance Rad1And a first divider resistor R11Ratio of resistance values, first adjustable resistance Rad1And a third resistor R3The ratio of the resistance values is determined.
The second transistor MP is known from the characteristics of the transistor itself in the embodiment of the disclosure2Threshold voltage V of2Is inversely related to temperature; in addition, the present disclosure providesIn the embodiment, the second transistor MP2Threshold voltage of and the first transistor MP1Difference V of threshold voltages of2-V1The calculation method is as follows:
Figure BDA0002324758580000143
wherein, CdIs the surface depletion layer capacitance of a transistor, CoxIs a capacitor of an oxide layer of a transistor,
Figure BDA0002324758580000144
is a positive temperature coefficient, where k is the Boltzmann constant and k is about 1.38X 10-23J/K, T is thermodynamic temperature, unit is K (Kelvin), corresponding absolute temperature is about 300K at normal temperature, q is electronic charge, and q is 1.6 multiplied by 10-19C, A is the first transistor MP1And the second transistor MP2Width to length ratio of (a).
From equation (5), the second transistor MP2Threshold voltage of and the first transistor MP1Difference V of threshold voltages of2-V1Is positively correlated with the temperature, so that the first adjustable resistor R can be adjustedad1And a first divider resistor R11And a first adjustable resistor Rad1And a third resistor R3The proportional relation of the resistance values enables the trigger voltage of the power-on reset circuit to be designed to be irrelevant to the temperature, so that temperature compensation can be achieved, the reset voltage can not deviate along with the temperature under the condition that the power-on reset circuit does not have reference voltage, and high reset precision can be achieved.
In addition, since the second transistor MP is formed in the advanced process2The threshold voltage of the second transistor MP can be as low as about 0.25V, and in the embodiment of the disclosure, the second transistor MP can be used2Is set to 0.25V, in which case by adjusting the first adjustable resistance Rad1Are respectively connected with the first divider resistor R11A third resistor R3The trigger voltage of the power-on reset circuit shown in the embodiment of the present disclosure can be controlled to be about 0.5V according to the proportional relationship of the resistance valuesAnd right, thereby effectively reducing the trigger voltage.
As shown in fig. 10, in the embodiment of the disclosure, after the power-on reset circuit is triggered, the comparator 902 outputs a high-level signal VCompTo the Schmitt trigger 903, the Schmitt trigger 903 responds to the high level signal VCompDe-noising is carried out, and the output waveform change lags behind the high level signal VCompSignal V ofSmt. Due to the output signal V of the Schmitt trigger 903SmtThe variation is slow, and in the embodiment of the disclosure, the buffer circuit 904 is further configured to shape the signal and output a shaped signal V with strong driving capabilityBufAs a power-on reset signal. In the disclosed embodiment, the buffer circuit 904 may include a two-stage buffer, wherein the buffer 1 outputs the first buffered signal VBuf1To the voltage detection circuit 901 to control the switch SW1Opening and closing of (1); the buffer 2 outputs a second buffered signal VBuf2As a power-on reset signal.
In the embodiment of the disclosure, the buffer 1 can output the first buffering signal VBuf1To the voltage detection circuit 901 to control the switch SW1Is closed, thereby the first adjustable resistor R is connectedad1Of (3) a series resistance R13And a second adjustable resistor Rad2Of (3) a series resistance R23And (4) short-circuiting. Due to the series resistance R13And R23Is short-circuited to make the first adjustable resistor Rad1And a second adjustable resistor Rad2When the power supply voltage changes from high to low, the first branch L of the voltage detection circuit 901 is connected1And a first branch L2When the voltage of the first output terminal of the voltage detection circuit 901 is reduced to a voltage VOut1And a second output terminal voltage VOut2When the voltage drops to be equal again, the trigger voltage of the power-on reset circuit is smaller than that of the power-on reset circuit in the voltage rising process, so a window is generated in the rising and falling processes of the power voltage, and hysteresis is formed. By the hysteresis effect, the power supply voltage can be prevented from shaking to generate misoperation, so that the anti-interference capability of the power-on reset circuit is improved.
In addition, it should be noted that, in some embodiments,in the formula (4), when the first transistor and the second transistor are both PMOS transistors or NMOS transistors, V is1And V2Threshold voltages V of the first transistor and the second transistor, respectivelyth(ii) a When the first transistor and the second transistor are both PNP triode or NPN triode, V is1And V2V of the first transistor and the second transistor respectivelybeA voltage.
The power-on reset circuit provided by this embodiment may also be used as an under-voltage protection circuit in other systems, and when being used as an under-voltage protection circuit, the circuit structure and the operation principle are the same as those described in this embodiment.
The power-on reset circuit provided by the embodiment can be used for a system-on-chip as a power-on reset circuit or an undervoltage protection circuit of the system-on-chip.
The above-mentioned embodiments are merely specific embodiments of the present disclosure, which are used for illustrating the technical solutions of the present disclosure and not for limiting the same, and the scope of the present disclosure is not limited thereto, although the present disclosure is described in detail with reference to the foregoing embodiments, those skilled in the art should understand that: any person skilled in the art can modify or easily conceive of the technical solutions described in the foregoing embodiments or equivalent technical features thereof within the technical scope of the present disclosure; such modifications, changes or substitutions do not depart from the spirit and scope of the exemplary embodiments of the present disclosure, and should be construed as being included therein.

Claims (17)

1. A power-on-reset circuit, comprising:
a voltage detection circuit for detecting the power supply voltage, including a first output terminal, a second output terminal, a first branch circuit and a second branch circuit connected in parallel between ground and the power supply voltage, wherein
The first branch circuit comprises a first divider resistor and a first adjustable resistor which are connected in series, the second branch circuit comprises a second divider resistor and a second adjustable resistor which are connected in series, the first divider resistor and the second divider resistor have the same resistance value, the first adjustable resistor and the second adjustable resistor have the same resistance value,
the first voltage dividing resistor of the first branch is connected with a first transistor and a third resistor which are connected in series with each other in parallel to form a first parallel circuit, one end of the first parallel circuit is grounded, and the other end of the first parallel circuit is connected to the first output end of the voltage detection circuit,
a second voltage-dividing resistor of the second branch is connected with a second transistor in parallel to form a second parallel circuit, one end of the second parallel circuit is grounded, and the other end of the second parallel circuit is connected to a second output end of the voltage detection circuit;
and the non-inverting input end of the comparator is connected to the first output end of the voltage detection circuit, and the inverting input end of the comparator is connected to the second output end of the voltage detection circuit and used for outputting a power-on reset signal.
2. The power-on-reset circuit as claimed in claim 1, wherein the area of the first transistor is n times larger than that of the second transistor, and n is an integer of 2 or more.
3. The power-on reset circuit as claimed in claim 2, wherein the first transistor is a first PMOS transistor, the drain of the first PMOS transistor is connected to one end of a third resistor, the source and the gate of the first PMOS transistor are grounded, and the other end of the third resistor is connected to the first output terminal of the voltage detection circuit; the second transistor is a second PMOS tube, the drain electrode of the second PMOS tube is connected to the second output end of the voltage detection circuit, and the source electrode and the grid electrode of the second PMOS tube are grounded.
4. The power-on reset circuit as claimed in claim 2, wherein the first transistor is a first NMOS transistor, a source and a gate of the first NMOS transistor are connected to one end of a third resistor, a drain of the first NMOS transistor is grounded, and the other end of the third resistor is connected to the first output terminal of the voltage detection circuit; the second transistor is a second NMOS transistor, a source electrode and a grid electrode of the second NMOS transistor are connected to a second output end of the voltage detection circuit, and a drain electrode is grounded.
5. The power-on reset circuit as claimed in claim 2, wherein the first transistor is a first PNP transistor, an emitter of the first PNP transistor is connected to one end of a third resistor, a collector and a base of the first PNP transistor are grounded, and the other end of the third resistor is connected to the first output terminal of the voltage detection circuit; the second transistor is a second PNP triode, an emitting electrode of the second PNP triode is connected to a second output end of the voltage detection circuit, and a collecting electrode and a base electrode of the second PNP triode are grounded.
6. The power-on reset circuit as claimed in claim 2, wherein the first transistor is a first NPN transistor, a collector and a base of the first NPN transistor are connected to one end of a third resistor, an emitter of the first NPN transistor is grounded, and the other end of the third resistor is connected to the first output terminal of the voltage detection circuit; the second transistor is a second NPN triode, a collector and a base of the second NPN triode are connected to the second output end of the voltage detection circuit, and an emitter of the second NPN triode is grounded.
7. The power-on-reset circuit of claim 2, the trigger voltage of the power-on-reset circuit adapted to:
Figure FDA0002324758570000021
wherein, V1Is the threshold voltage of the first transistor, V2Is the threshold voltage, R, of the second transistor3、R1、RadThe resistance values of the third resistor, the first divider resistor and the first adjustable resistor are respectively.
8. The power-on-reset circuit of claim 1, further comprising a schmitt trigger and a buffer circuit comprising one or more buffers, wherein
The output end of the comparator is connected to the input end of the Schmitt trigger, the output end of the Schmitt trigger is connected to the buffer circuit, and the buffer circuit is used for outputting a power-on reset signal.
9. The power-on reset circuit as claimed in claim 8, wherein the first adjustable resistor comprises a plurality of series resistors, the second adjustable resistor comprises a plurality of series resistors, a switch is connected in parallel between two ends of one of the series resistors of the first adjustable resistor and two ends of one of the series resistors of the second adjustable resistor, and the buffer circuit is further configured to output the power-on reset signal to the switch to control the series resistor access circuit or short circuit.
10. The power-on-reset circuit of claim 8, further comprising a pulse generating circuit coupled to the output of the buffer circuit for generating a pulse signal of a certain width as the power-on-reset signal.
11. A voltage detection circuit for detecting a supply voltage, comprising a first output terminal and a second output terminal, a first branch and a second branch connected in parallel between ground and the supply voltage, wherein
The first branch circuit comprises a first divider resistor and a first adjustable resistor which are connected in series, the second branch circuit comprises a second divider resistor and a second adjustable resistor which are connected in series, the first divider resistor and the second divider resistor have the same resistance value, the first adjustable resistor and the second adjustable resistor have the same resistance value,
the first voltage dividing resistor of the first branch is connected with a first transistor and a third resistor which are connected in series with each other in parallel to form a first parallel circuit, one end of the first parallel circuit is grounded, the other end of the first parallel circuit is connected to the first output end of the voltage detection circuit,
and a second voltage-dividing resistor of the second branch is connected with a second transistor in parallel to form a second parallel circuit, one end of the second parallel circuit is grounded, and the other end of the second parallel circuit is connected to the second output end of the voltage detection circuit.
12. The voltage detection circuit as claimed in claim 11, wherein an area of the first transistor is n times larger than that of the second transistor, and n is an integer of 2 or more.
13. The voltage detection circuit of claim 12, wherein the first transistor is a first PMOS transistor, a drain of the first PMOS transistor is connected to one end of a third resistor, a source and a gate of the first PMOS transistor are grounded, and the other end of the third resistor is connected to the first output terminal of the voltage detection circuit; the second transistor is a second PMOS tube, the drain electrode of the second PMOS tube is connected to the second output end of the voltage detection circuit, and the source electrode and the grid electrode of the second PMOS tube are grounded.
14. The voltage detection circuit as claimed in claim 12, wherein the first transistor is a first NMOS transistor, a source and a gate of the first NMOS transistor are connected to one end of a third resistor, a drain of the first NMOS transistor is grounded, and the other end of the third resistor is connected to the first output terminal of the voltage detection circuit; the second transistor is a second NMOS transistor, a source electrode and a grid electrode of the second NMOS transistor are connected to a second output end of the voltage detection circuit, and a drain electrode is grounded.
15. The voltage detection circuit of claim 12, wherein the first transistor is a first PNP transistor, an emitter of the first PNP transistor is connected to one end of a third resistor, a collector and a base of the first PNP transistor are grounded, and the other end of the third resistor is connected to the first output terminal of the voltage detection circuit; the second transistor is a second PNP triode, an emitting electrode of the second PNP triode is connected to a second output end of the voltage detection circuit, and a collecting electrode and a base electrode of the second PNP triode are grounded.
16. The voltage detection circuit as claimed in claim 12, wherein the first transistor is a first NPN transistor, a collector and a base of the first NPN transistor are connected to one end of a third resistor, an emitter of the first NPN transistor is grounded, and the other end of the third resistor is connected to the first output terminal of the voltage detection circuit; the second transistor is a second NPN triode, a collector and a base of the second NPN triode are connected to the second output end of the voltage detection circuit, and an emitter of the second NPN triode is grounded.
17. A system-in-chip comprising the power-on-reset circuit as claimed in any one of claims 1-10.
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