CN116647216A - Method, circuit, phase-locked loop and chip for solving POR and LDO power-on sequence - Google Patents
Method, circuit, phase-locked loop and chip for solving POR and LDO power-on sequence Download PDFInfo
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- CN116647216A CN116647216A CN202310630997.8A CN202310630997A CN116647216A CN 116647216 A CN116647216 A CN 116647216A CN 202310630997 A CN202310630997 A CN 202310630997A CN 116647216 A CN116647216 A CN 116647216A
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- 238000000034 method Methods 0.000 title claims abstract description 15
- 238000004364 calculation method Methods 0.000 claims description 5
- 230000001174 ascending effect Effects 0.000 claims description 3
- 230000003247 decreasing effect Effects 0.000 claims description 3
- 101710147185 Light-dependent protochlorophyllide reductase Proteins 0.000 claims 1
- 101710193909 Protochlorophyllide reductase, chloroplastic Proteins 0.000 claims 1
- 101710109491 Pyruvate synthase subunit PorA Proteins 0.000 claims 1
- 101710109487 Pyruvate synthase subunit PorB Proteins 0.000 claims 1
- 101710109489 Pyruvate synthase subunit PorC Proteins 0.000 claims 1
- 101710109484 Pyruvate synthase subunit PorD Proteins 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000003111 delayed effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/22—Modifications for ensuring a predetermined initial state when the supply voltage has been applied
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/22—Modifications for ensuring a predetermined initial state when the supply voltage has been applied
- H03K17/223—Modifications for ensuring a predetermined initial state when the supply voltage has been applied in field-effect transistor switches
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/296—Time-programme switches providing a choice of time-intervals for executing more than one switching action and automatically terminating their operation after the programme is completed
Abstract
The invention discloses a method, a circuit, a phase-locked loop and a chip for solving the power-on sequence of a POR and an LDO, wherein the circuit comprises a low dropout linear voltage regulator, a power-on reset circuit, an inverter, a first MOS tube, a second MOS tube, a first resistor, a second resistor and a third resistor, and a signal input end of the low dropout linear voltage regulator, a first end of the first resistor and a source electrode of the second MOS tube are connected with a working voltage VDD; the grid electrode of the first MOS tube is connected with the signal output end of the low-dropout linear voltage regulator, the drain electrode of the first MOS tube is connected with the second end of the first resistor and the grid electrode of the second MOS tube, and the source electrode of the first MOS tube is grounded. According to the invention, the first resistor is used as the pull-up resistor to enable the second MOS tube to be kept in an initial off state, and then the grid electrode of the first MOS tube is controlled by the output signal of the low dropout linear voltage regulator, so that the power-on reset circuit outputs after the output of the low dropout linear voltage regulator is stable, and the correct power-on time sequence is ensured.
Description
Technical Field
The present invention relates to the field of clock chip design technology, and in particular, to a method, a circuit, a phase-locked loop, and a chip for solving the power-on sequence of a POR and an LDO.
Background
In the design of a clock chip, the correct and reliable power-on time sequence determines whether the chip can work normally. This requires POR (Power On Reset) to perform a power-on RESET, where the power supply VDD generates a RESET signal (RESET signal) at the beginning of power-on to initialize the whole system chip, and when VDD is high enough, the POR follows the power supply voltage output to make each module work normally, and when VDD drops low enough, the POR outputs a low RESET signal to RESET the whole chip circuit.
When the digital module needs to use an LDO (low dropout linear regulator), it needs to ensure that the output POR is high after the digital LDO is stable. In this case, whether the POR is pulled first or the LDO is stabilized first cannot be determined, and the POR is pulled first can be delayed by counting by a counter, but the delay time is influenced by the VDD power-up time and PVT (Process Voltage Temperature ), and cannot give an accurate delay time.
Disclosure of Invention
In order to solve the above problems, the present invention provides a method, a circuit, a phase-locked loop and a chip for solving the power-on sequence of a POR and an LDO, wherein a first resistor is added as a pull-up resistor to keep a second MOS tube in an initial off state, and then the output signal of a low dropout linear voltage regulator is used to control the grid electrode of the first MOS tube, so that the power-on reset circuit outputs after the output of the low dropout linear voltage regulator is stable, thereby ensuring the correct power-on sequence.
The technical scheme adopted by the invention is as follows:
a circuit for solving POR and LDO power-on sequence comprises a low dropout linear voltage regulator, a power-on reset circuit, an inverter, a first MOS tube, a second MOS tube, a first resistor, a second resistor and a third resistor, wherein a signal input end of the low dropout linear voltage regulator, a first end of the first resistor and a source electrode of the second MOS tube are connected with a working voltage VDD; the grid electrode of the first MOS tube is connected with the signal output end of the low dropout linear voltage regulator, the drain electrode of the first MOS tube is connected with the second end of the first resistor and the grid electrode of the second MOS tube, and the source electrode of the first MOS tube is grounded; the drain electrode of the second MOS tube is connected with the first end of the second resistor, the second end of the second resistor is connected with the first end of the third resistor and the input end of the inverter, the output end of the inverter is connected with the power-on reset circuit, and the second end of the third resistor is grounded; and the first resistor is used as a pull-up resistor to enable the second MOS tube to be kept in an initial off state, and then the output signal of the low dropout linear voltage regulator is used for controlling the grid electrode of the first MOS tube, so that the power-on reset circuit outputs after the output of the low dropout linear voltage regulator is stable.
Further, the method comprises the steps of,the reference voltage V is realized by adjusting the first resistor and the size of the first MOS tube REF After the output is stable, the pull-down capability of the first MOS tube is larger than that of the first resistor, namely the on-resistance R of the first MOS tube on The second MOS tube is smaller than the first resistor, the second MOS tube starts to be conducted, the voltage of the connecting point of the inverter, the first resistor and the second resistor starts to rise, and when the voltage rises to the threshold voltage of the inverter, the power-on reset circuit starts to output.
Further, the on-resistance R of the first MOS tube on The calculation method of (1) comprises the following steps:
wherein L represents the gate length of the first MOS tube, W represents the gate width of the first MOS tube, mu n Representing mobility of the first MOS tube, C ox Representing the capacitance of the gate oxide layer per unit area, V gs Representing the gate-source voltage of the first MOS transistor, V t Representing the threshold voltage of the first MOS transistor.
A high performance phase locked loop includes the above-described circuitry to address POR and LDO power-up sequences.
A clock chip comprises the high-performance phase-locked loop.
A method of resolving power-on sequences of POR and LDO, comprising the steps of:
step S1, when the working voltage VDD starts to be electrified, a reference voltage V is arranged at the grid electrode of the first MOS tube REF Starting to rise; the first MOS tube is in an off state, the connection point of the drain electrode of the first MOS tube, the grid electrode of the second MOS tube and the second end of the first resistor is marked as an A point, the A point is pulled up by the first resistor to change along with the working voltage VDD, the grid source voltage of the second MOS tube is zero at the moment and is in the off state, and the output of the power-on reset circuit is 0;
s2, when the reference voltage V REF Rising to threshold voltage V of first MOS tube th After that, the first MOS tube is conducted, the point A starts to pull down, and the on-resistance R of the first MOS tube on With reference voltage V REF Ascending and decreasing;
s3, adjusting the sizes of the first resistor and the first MOS tube to enable the reference voltage V REF After the output is stable, when the pull-down capability of the first MOS tube is larger than the pull-up capability of the first resistor, the point A is pulled down to 0, the second MOS tube starts to be conducted, the voltage of the point B which is the connection point of the inverter, the first resistor and the second resistor starts to rise, and when the voltage rises to the threshold voltage of the inverter, the output of the power-on reset circuit is pulled up to the working voltage VDD.
Further, in step S3, when the pull-down capability of the first MOS transistor is greater than the pull-up capability of the first resistor, the on-resistance R of the first MOS transistor on Less than the first resistance.
Further, the on-resistance R of the first MOS tube on The calculation method of (1) comprises the following steps:
wherein L represents the gate length of the first MOS tube, W represents the gate width of the first MOS tube, mu n Representing mobility of the first MOS tube, C ox Representing the capacitance of the gate oxide layer per unit area, V gs Representing the gate-source voltage of the first MOS transistor, V t Representing the threshold voltage of the first MOS transistor.
A high performance phase locked loop is based on the method for solving POR and LDO power-on sequence.
A clock chip comprises the high-performance phase-locked loop.
The invention has the beneficial effects that:
according to the invention, the first resistor is added as the pull-up resistor to enable the second MOS tube to keep an initial off state, and then the grid electrode of the first MOS tube is controlled by the output signal of the low dropout linear voltage regulator, so that the power-on reset circuit outputs after the output of the low dropout linear voltage regulator is stable, and the correct power-on time sequence is ensured.
Drawings
FIG. 1 is a waveform diagram showing that a POR is pulled up before an LDO.
Fig. 2 is a schematic circuit diagram for solving the power-on sequence of POR and LDO in embodiment 1.
FIG. 3 is a schematic diagram of the POR and LDO output waveforms of embodiment 1.
Detailed Description
Specific embodiments of the present invention will now be described in order to provide a clearer understanding of the technical features, objects and effects of the present invention. It should be understood that the particular embodiments described herein are illustrative only and are not intended to limit the invention, i.e., the embodiments described are merely some, but not all, of the embodiments of the invention. All other embodiments, which can be made by a person skilled in the art without making any inventive effort, are intended to be within the scope of the present invention.
Example 1
As shown in fig. 1, when the power-on reset circuit POR is pulled up at point a, the low dropout linear regulator LDO is not yet stable, resulting in a digital enable error. Although the low dropout linear regulator LDO is ensured to be stable by delaying the pulling-up time of the power-on reset circuit POR through a counter, the margin is insufficient if the delay time is set to be too small, and the power-on time is strictly required; too much delay time is set, power-up time is wasted.
Based on this, the present embodiment provides a circuit for solving the power-on sequence of the POR and the LDO without a counter, as shown in fig. 1, the circuit includes a low dropout linear regulator LDO, a power-on reset circuit POR, an inverter, a first MOS transistor M1, a second MOS transistor M2, a first resistor R1, a second resistor R2 and a third resistor R3, wherein a signal input end of the low dropout linear regulator LDO, a first end of the first resistor R1, and a source electrode of the second MOS transistor M2 are connected to an operating voltage VDD; the grid electrode of the first MOS tube M1 is connected with the signal output end of the low dropout linear regulator LDO, the drain electrode is connected with the second end of the first resistor R1 and the grid electrode of the second MOS tube M2, and the source electrode is grounded; the drain electrode of the second MOS tube M2 is connected with the first end of the second resistor R2, the second end of the second resistor R2 is connected with the first end of the third resistor R3 and the input end of the inverter, the output end of the inverter is connected with the power-on reset circuit POR, and the second end of the third resistor R3 is grounded.
The circuit uses a first resistor R1 as a pull-up resistor to enable a second MOS tube M2 to keep an initial off state, and then controls a grid electrode of the first MOS tube M1 through an output signal of a low dropout linear regulator LDO, so that a power-on reset circuit POR outputs after the output of the low dropout linear regulator LDO is stable.
Meanwhile, the embodiment provides a method for solving the power-on sequence of the POR and the LDO, which comprises the following steps:
step S1, when the working voltage VDD starts to be powered on, the reference voltage V at the grid electrode of the first MOS transistor M1 REF Starting to rise; the first MOS tube M1 is in an off state, the connection point of the drain electrode of the first MOS tube M1, the grid electrode of the second MOS tube M2 and the second end of the first resistor R1 is recorded as an A point, the A point is pulled up by the first resistor R1 to change along with the working voltage VDD, at the moment, the grid source voltage of the second MOS tube M2 is zero and is in an off state, and the POR output is 0;
s2, when the reference voltage V REF Rising to threshold voltage V of first MOS transistor M1 th After that, the first MOS tube M1 is conducted, the point A starts to pull down, and the on-resistance R of the first MOS tube M1 on With reference voltage V REF Ascending and decreasing;
s3, adjusting the sizes of the first resistor R1 and the first MOS tube M1 to enable the reference voltage V REF After the output is stable, when the pull-down capability of the first MOS transistor M1 is greater than the pull-up capability of the first resistor R1, the point a is pulled down to 0, the second MOS transistor M2 starts to be turned on, the voltage at the point B, which is the connection point of the inverter, the first resistor R1 and the second resistor R2, starts to rise, and when the voltage rises to the threshold voltage of the inverter, the output of the power-on reset circuit POR is pulled up to the working voltage VDD.
Preferably, in step S3, when the pull-down capability of the first MOS transistor M1 is greater than the pull-up capability of the first resistor R1, the on-resistance R of the first MOS transistor M1 on Less than the first resistance R1.
More preferably, the on-resistance R of the first MOS transistor M1 on The calculation method of (2) is as follows:
wherein L represents the gate length, W of the first MOS transistor M1Represents the gate width, mu of the first MOS transistor M1 n Represents the mobility of the first MOS tube M1, C ox Representing the capacitance of the gate oxide layer per unit area, V gs Represents the gate-source voltage, V, of the first MOS transistor M1 t The threshold voltage of the first MOS transistor M1 is shown.
As shown in fig. 3, which shows the improved POR output waveform, it can be seen that the point a is pulled up by the first resistor R1 and follows the change of the working voltage VDD, when the first MOS transistor M1 is turned on and the pull-down resistor is smaller than the first resistor R1, the point a is pulled down to 0, the second MOS transistor M2 is turned on, and the power-on reset circuit POR starts to output.
Example 2
This example is based on example 1:
the present embodiment provides a high performance phase locked loop including the circuit of embodiment 1 that addresses the POR and LDO power-up sequences.
Example 3
This example is based on example 2:
the present embodiment provides a clock chip including the high performance phase locked loop of embodiment 2.
The foregoing is merely a preferred embodiment of the invention, and it is to be understood that the invention is not limited to the form disclosed herein but is not to be construed as excluding other embodiments, but is capable of numerous other combinations, modifications and environments and is capable of modifications within the scope of the inventive concept, either as taught or as a matter of routine skill or knowledge in the relevant art. And that modifications and variations which do not depart from the spirit and scope of the invention are intended to be within the scope of the appended claims.
Claims (10)
1. The circuit for solving the power-on sequence of the POR and the LDO is characterized by comprising a low dropout linear voltage regulator (LDO), a power-on reset circuit (POR), an inverter, a first MOS tube (M1), a second MOS tube (M2), a first resistor (R1), a second resistor (R2) and a third resistor (R3), wherein a signal input end of the low dropout linear voltage regulator (LDO), a first end of the first resistor (R1) and a source electrode of the second MOS tube (M2) are connected with a working voltage VDD; the grid electrode of the first MOS tube (M1) is connected with the signal output end of the low dropout linear regulator (LDO), the drain electrode of the first MOS tube is connected with the second end of the first resistor (R1) and the grid electrode of the second MOS tube (M2), and the source electrode of the first MOS tube is grounded; the drain electrode of the second MOS tube (M2) is connected with the first end of a second resistor (R2), the second end of the second resistor (R2) is connected with the first end of a third resistor (R3) and the input end of an inverter, the output end of the inverter is connected with a power-on reset circuit (POR), and the second end of the third resistor (R3) is grounded;
the first resistor (R1) is used as a pull-up resistor to enable the second MOS tube (M2) to keep an initial off state, and then the output signal of the low dropout linear voltage regulator (LDO) is used for controlling the grid electrode of the first MOS tube (M1) so that the power-on reset circuit (POR) outputs after the output of the low dropout linear voltage regulator (LDO) is stable.
2. The circuit for solving the power-on sequence of POR and LDO according to claim 1, wherein the reference voltage V is obtained by adjusting the dimensions of the first resistor (R1) and the first MOS transistor (M1) REF After the output is stable, the pull-down capability of the first MOS tube (M1) is larger than the pull-up capability of the first resistor (R1), namely the on-resistance R of the first MOS tube (M1) on The MOS transistor is smaller than the first resistor (R1), the second MOS transistor (M2) starts to be conducted, the voltage of the connecting point of the inverter, the first resistor (R1) and the second resistor (R2) starts to rise, and when the voltage rises to the threshold voltage of the inverter, the power-on reset circuit (POR) starts to output.
3. The circuit for solving the power-on sequence of POR and LDO according to claim 1, wherein the on-resistance R of the first MOS transistor (M1) on The calculation method of (1) comprises the following steps:
wherein L represents the gate length of the first MOS tube (M1), W represents the gate width of the first MOS tube (M1), μ n Represents the mobility of the first MOS tube (M1), C ox Representing the capacitance of the gate oxide layer per unit area, V gs Represents the gate-source voltage, V, of the first MOS transistor (M1) t The threshold voltage of the first MOS transistor (M1) is represented.
4. A high performance phase locked loop comprising a circuit according to any of claims 1-3 that addresses the power-on sequence of PORs and LDOs.
5. A clock chip comprising the high performance phase locked loop of claim 4.
6. A method for solving the power-on sequence of a POR and an LDO based on the circuit for solving the power-on sequence of a POR and an LDO according to claim 1, the method comprising the steps of:
s1, when the working voltage VDD starts to be electrified, a reference voltage V is arranged at the grid electrode of the first MOS tube (M1) REF Starting to rise; the first MOS tube (M1) is in an off state, a connection point of a drain electrode of the first MOS tube (M1), a grid electrode of the second MOS tube (M2) and a second end of the first resistor (R1) is recorded as an A point, the A point is pulled up by the first resistor (R1) to change along with the working voltage VDD, at the moment, the grid source voltage of the second MOS tube (M2) is zero and is in an off state, and a power-on reset circuit (POR) outputs 0;
s2, when the reference voltage V REF Rise to the threshold voltage V of the first MOS transistor (M1) th After that, the first MOS tube (M1) is conducted, the point A starts to pull down, and the on-resistance R of the first MOS tube (M1) on With reference voltage V REF Ascending and decreasing;
s3, adjusting the sizes of the first resistor (R1) and the first MOS tube (M1) to enable the reference voltage V REF After the output is stable, when the pull-down capability of the first MOS tube (M1) is larger than the pull-up capability of the first resistor (R1), the point A is pulled down to 0, the second MOS tube (M2) starts to be conducted, the voltage of the point B which is the connection point of the inverter, the first resistor (R1) and the second resistor (R2) starts to rise, and when the voltage rises to the threshold voltage of the inverter, the output of the power-on reset circuit (POR) is pulled up to the working voltage VDD.
7. The method for resolving POR and LDO power-up sequences according to claim 6, further comprising the step ofIn step S3, when the pull-down capability of the first MOS tube (M1) is greater than the pull-up capability of the first resistor (R1), the on-resistance R of the first MOS tube (M1) on Is smaller than the first resistance (R1).
8. The method for solving a power-on sequence of a POR and an LDO according to claim 6, wherein the on-resistance R of the first MOS transistor (M1) on The calculation method of (1) comprises the following steps:
wherein L represents the gate length of the first MOS tube (M1), W represents the gate width of the first MOS tube (M1), μ n Represents the mobility of the first MOS tube (M1), C ox Representing the capacitance of the gate oxide layer per unit area, V gs Represents the gate-source voltage, V, of the first MOS transistor (M1) t The threshold voltage of the first MOS transistor (M1) is represented.
9. A high performance phase locked loop, characterized by a method of solving the power-on sequence of POR and LDO according to any of claims 6-8.
10. A clock chip comprising the high performance phase locked loop of claim 9.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310630997.8A CN116647216A (en) | 2023-05-31 | 2023-05-31 | Method, circuit, phase-locked loop and chip for solving POR and LDO power-on sequence |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202310630997.8A CN116647216A (en) | 2023-05-31 | 2023-05-31 | Method, circuit, phase-locked loop and chip for solving POR and LDO power-on sequence |
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| CN116647216A true CN116647216A (en) | 2023-08-25 |
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Citations (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101026374A (en) * | 2007-03-23 | 2007-08-29 | 鼎芯通讯（上海）有限公司 | Circuit for controll chip digital module working |
| CN204190734U (en) * | 2014-11-05 | 2015-03-04 | 百利通科技（扬州）有限公司 | A kind of electrify restoration circuit |
| CN105634453A (en) * | 2014-11-03 | 2016-06-01 | 上海华虹宏力半导体制造有限公司 | Power-on reset circuit |
| CN105988495A (en) * | 2015-02-09 | 2016-10-05 | 钜泉光电科技(上海)股份有限公司 | LDO (Low Drop-out voltage regulator) overshooting protection circuit |
| CN106371334A (en) * | 2015-07-21 | 2017-02-01 | 深圳市奇辉电气有限公司 | Circuit for controlling power-on and power-off time sequences and power supply system |
| CN111638742A (en) * | 2020-06-30 | 2020-09-08 | 湘潭大学 | Fast and stable LDO (low dropout regulator) circuit with zero pole tracking frequency compensation |
| CN114461463A (en) * | 2021-12-31 | 2022-05-10 | 上海聚栋半导体有限公司 | Once-open type power-on detection circuit |
| CN114696808A (en) * | 2020-12-25 | 2022-07-01 | 上海贝岭股份有限公司 | Power-on reset circuit |
| CN217469914U (en) * | 2022-04-29 | 2022-09-20 | 上海料聚微电子有限公司 | Power-on reset circuit |
| US20220407503A1 (en) * | 2021-06-17 | 2022-12-22 | Nxp B.V. | Mode detector for dc-dc converters |
| CN116015267A (en) * | 2022-12-31 | 2023-04-25 | 成都电科星拓科技有限公司 | Power-on and power-off reset method and device for protecting chip low-voltage device |
-
2023
- 2023-05-31 CN CN202310630997.8A patent/CN116647216A/en active Pending
Patent Citations (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101026374A (en) * | 2007-03-23 | 2007-08-29 | 鼎芯通讯（上海）有限公司 | Circuit for controll chip digital module working |
| CN105634453A (en) * | 2014-11-03 | 2016-06-01 | 上海华虹宏力半导体制造有限公司 | Power-on reset circuit |
| CN204190734U (en) * | 2014-11-05 | 2015-03-04 | 百利通科技（扬州）有限公司 | A kind of electrify restoration circuit |
| CN105988495A (en) * | 2015-02-09 | 2016-10-05 | 钜泉光电科技(上海)股份有限公司 | LDO (Low Drop-out voltage regulator) overshooting protection circuit |
| CN106371334A (en) * | 2015-07-21 | 2017-02-01 | 深圳市奇辉电气有限公司 | Circuit for controlling power-on and power-off time sequences and power supply system |
| CN111638742A (en) * | 2020-06-30 | 2020-09-08 | 湘潭大学 | Fast and stable LDO (low dropout regulator) circuit with zero pole tracking frequency compensation |
| CN114696808A (en) * | 2020-12-25 | 2022-07-01 | 上海贝岭股份有限公司 | Power-on reset circuit |
| US20220407503A1 (en) * | 2021-06-17 | 2022-12-22 | Nxp B.V. | Mode detector for dc-dc converters |
| CN114461463A (en) * | 2021-12-31 | 2022-05-10 | 上海聚栋半导体有限公司 | Once-open type power-on detection circuit |
| CN217469914U (en) * | 2022-04-29 | 2022-09-20 | 上海料聚微电子有限公司 | Power-on reset circuit |
| CN116015267A (en) * | 2022-12-31 | 2023-04-25 | 成都电科星拓科技有限公司 | Power-on and power-off reset method and device for protecting chip low-voltage device |
Non-Patent Citations (2)
| Title |
|---|
| WANG DEMING;HU JIANGUO;WANG JIANHUI;DING YANYU;WU JING;: "VLSI Implementation of Area and Power Efficient Digital Control Circuit for HF RFID Tag Chip", CHINESE JOURNAL OF ELECTRONICS, no. 01, 15 January 2020 (2020-01-15), pages 195 - 201 * |
| 方佩敏;: "具有排序及跟踪功能的LDO", 今日电子, no. 06, 10 June 2006 (2006-06-10), pages 67 - 73 * |
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