JPH07162281A - Data input buffer - Google Patents

Abstract

PURPOSE: To make it possible to maintain a stable input trip margin even when power supply voltage is changed and to obtain a data input buffer to be stably and surely operated. CONSTITUTION: A sense clock CLK outputted from a power supply voltage sensing circuit 220 is outputted as a logic 'low' when power supply voltage VCC becomes lower than reference voltage VREF and outputted as logical 'high' when the VCC becomes higher than the VREF. A PMOS transistor(TR) 55 to be controlled by the clock CLK is connected in parallel with a PMOS TR 50 in a Schmitt trigger circuit SM constituting a data input buffer and art NMOS TR 65 controlled by the clock CLK is connected to an NMOS TR 60. Thereby when the VCC is changed, the TRs 55, 65 are suitably turned on/off, so that the channel size ratio Wp/Wn of the TR 50 to the TR 60 is changed and an input trip margin for an input signal VIN is stabilized.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data input buffer for shaping an input signal to obtain a desired output signal,
In particular, the present invention relates to a data input buffer in a semiconductor memory device, which enables more stable and reliable operation with respect to fluctuations in power supply voltage.

[0002]

2. Description of the Related Art In a semiconductor memory device, since a TTL (Transistor-Transistor Logic) level input signal input from the outside is converted into a CMOS level signal that can be used internally, a data input buffer is connected to the outside. It is provided for the pin. Therefore,
In order to accurately determine the address signal and various control signals applied from the outside of the semiconductor memory device (chip),
The point is the operational stability of the data input buffer that performs the buffering.

Generally, in the data input buffer, an input trip point level (also called a switching point level) for determining a predetermined logic state from a TTL level signal sent from the outside is set. This is determined according to the channel size of the CMOS transistor that constitutes the buffer. However, when the channel size of the transistor is used as described above, the reliability of the buffer is relatively likely to be lowered due to the influence of factors that make the input trip level unstable such as fluctuation of the power supply voltage.

Further, recently, the power supply voltage in a highly integrated semiconductor memory device tends to decrease further, but even if the operating voltage decreases, the input / output related circuits in the semiconductor memory device operate stably and at high speed. If you do not, you will not get satisfactory performance. In particular, it is important to stabilize and speed up the operation of the data input buffer for converting the TTL level to the CMOS level because it greatly affects the overall operation of the semiconductor memory device.

FIG. 4 shows a structure of a data input buffer of a conventional general semiconductor memory device. The data input buffer includes a sensing unit 200 for sensing the state of the TTL level input signal VIN and a driving unit 210 for driving the output signal of the sensing unit 200.

The sensing section 200 includes a resistor 5, a PMOS transistor 10 which is always in a conductive state, a PMOS transistor 15 which receives an input signal VIN at each gate, and an NMOS.
And transistors 20 and 25. Also, NM
The OS transistor 30 is provided to improve the switching speed of the data input buffer. In the configuration of the sensing unit 200, the transistors 15, 20, 25 connected in series are usually Schmitt triggers.
Trigger) circuit, these transistors 15, 2
Channel size ratio of 0, 25 (Wp / Wn or Ln / L
p) determines the trip point level of the data input buffer.

The driving unit 210 is composed of inverters 35 and 40, and drives the signal set at the level sensing node N1 to finally provide the output signal VOUT to the inside of the chip.

In this data input buffer, the input signal V
If the potential of IN is sufficiently high, the NMOS transistor 2
0 and 25 are completely conductive, and level sensing node N
A logic "low" potential is set to 1. The logic "low" signal set at the level sensing node N1 is driven by the driver 210 and provided to each circuit of the semiconductor memory device.

On the other hand, if the potential of the input signal VIN is sufficiently low, the PMOS transistor 15 becomes conductive, and the potential of the logic "high" is set to the level sensing node N1. This case will be described in detail.

When the voltage of the input signal VIN is 0.8V or less, the PMOS transistor 15 is turned on, and the output signal VOUT is output as a logic "high". In this case, while the data input buffer is operating, the PMO
Since the S-transistor 10 is always on,
The voltage VS1 set at the source terminal S1 of the S-transistor 15 begins with the resistor 5 and the PMOS transistor 10.
It is a value that is lowered by a predetermined value due to. And PMOS
When the transistor 15 becomes conductive and current flows, the PMOS
The voltage V set at the source terminal S1 of the transistor 15
S1 becomes even lower.

In this operation, when the power supply voltage VCC rises and the internal power supply voltage Vint obtained by converting (stepping down) the power supply voltage VCC for the internal circuit rises, the voltage VS1 set at the source terminal S1 of the PMOS transistor 15 also rises. To do. As a result, the gate of the PMOS transistor 15
As the source-to-source voltage | VIN-VS1 | increases, the voltage appearing at the level sensing node N1 (input trip margin) also increases as the power supply voltage VCC increases. That is, the gate-source voltage | VIN-VS of the PMOS transistor 15 due to the rise of the power supply voltage VCC.
Due to the increase of 1 |, the trip margin of the input level changes. As a result, in the data input buffer shown in FIG. 4, even if the level of the input signal VIN is higher than 0.8V, the output signal VOUT of logical "high" can be output. Even when the power supply voltage VCC becomes lower than the normal range, the input trip margin of the PMOS transistor 15 may be affected in the same manner as the increase of the power supply voltage VCC.

As described above, in the data input buffer which basically determines the input trip margin by the channel size ratio of the PMOS transistor 15 and the NMOS transistors 20 and 25, when the power supply voltage VCC fluctuates and falls, "low" input is performed. Trip margin VIL is insufficient,
When the power supply voltage VCC fluctuates and rises, the "high" input trip margin VIH becomes insufficient. That is, when the power supply voltage changes, the gate-source voltage and the drain-source voltage of the PMOS transistor and the NMOS transistor change, which causes a problem that the operation becomes unstable.

[0013]

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a data input buffer which can maintain a stable input trip margin even when the power supply voltage fluctuates and can operate stably and reliably.

[0014]

In order to achieve such an object, the present invention provides a power supply voltage sensing circuit for a data input buffer, which senses the level of a power supply voltage applied from the outside to generate a level sensing signal. And a first conductive path connected between the internal power supply voltage terminal and the level sensing node and capable of controlling the amount of current corresponding to the level sensing signal,
And a second conductive path connected between the level sensing node and the ground voltage terminal and capable of controlling the amount of current in response to the level sensing signal.

Further, in particular, the first conductive path of the data input buffer has at least two P-channel MOS transistors connected in series for receiving an input signal at the gate terminal, and a level sensing signal at the gate terminal, and the channel is the above-mentioned channel. A P-channel MOS transistor connected in parallel to any of the P-channel MOS transistors, and a second conductive path having at least two N-channel MOS transistors connected in series and having a gate terminal for receiving an input signal; And an N-channel MOS transistor whose channel receives a level detection signal and whose channel is connected in parallel to any of the N-channel MOS transistors.

[0016]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT A preferred embodiment of the present invention will now be described in detail with reference to the accompanying drawings.

FIG. 1 shows an example of the data input buffer according to the present invention. The same components as those in FIG. 4 are designated by the same reference numerals.

The data input buffer shown in FIG. 1 senses the level of a power source voltage VCC applied from the outside and generates a sensing clock CLK as a level sensing signal, and a power source voltage sensing circuit 220. Controlled by the sensing clock CLK output from
The driving unit 210 includes a sensing unit 225 that senses the voltage level of the TL level input signal VIN and inverters 35 and 40, and a driving unit 210 that drives and outputs the signal of the level sensing node N2 of the sensing unit 225. There is. Incidentally, V
SS indicates the ground voltage.

FIG. 2 shows a detailed circuit example of the power supply voltage sensing circuit 220. The power supply voltage sensing circuit 220 receives the reference voltage VREF and the power supply voltage VCC as inputs, and compares the level of the power supply voltage VCC with the voltage level of the reference voltage VREF to generate the sensing clock CLK. Therefore, a PMOS transistor 75 that receives the reference voltage VREF at its gate terminal, a PMOS transistor 105 that receives the reference voltage VREF at its gate terminal, and performs current control according to the voltage level of the reference voltage VREF, and a drain of the PMOS transistor 105. PM with gate terminal connected to terminal
An NMOS transistor 95 having a gate terminal connected to the OS transistor 85 and the drain terminal of the PMOS transistor 85 and connected in series to the PMOS transistor 75.
An NMOS transistor having a gate terminal connected to the drain terminal of the PMOS transistor 75, connected to the NMOS transistor 100 connected in series to the PMOS transistor 85, and the source terminals of the NMOS transistors 95 and 100, and receiving the enable signal φEN at its gate terminal. And a transistor 120. Further, the drain terminal of the PMOS transistor 105 is connected in series with an NMOS transistor 110 which receives a reference voltage VREF at its gate terminal.
An NMOS transistor 115 that receives the enable signal φEN is connected in series to the gate terminal.

The enable signal φEN input to the gate terminals of the NMOS transistors 115 and 120 is an enable control signal for controlling the driving of the power supply voltage sensing circuit 220. That is, the power supply voltage sensing circuit 220 is enabled when the enable signal φEN is logic “high”, and the power supply voltage sensing circuit 220 is disabled when the enable signal φEN is logic “low”.
Therefore, the power supply voltage sensing circuit 220 suppresses unnecessary power consumption, which is advantageous in terms of power saving.

FIG. 3 shows an example of a circuit for generating the enable signal φEN. As shown in the figure, an inverter chain composed of a large number of inverters 125, 130 and 135 and having a chip enable clock CECLK as an input, and an NAND gate 140 having an output of the inverter chain and the chip enable clock CECLK as an input.
And an inverter 145 that inverts the output of the NAND gate 140. That is, the enable signal φ based on the chip enable clock CECLK
It is designed to generate EN.

The data input buffer of this example will be described in detail with reference to FIGS. Sensing unit 22
Reference numeral 5 includes a resistor 5 and a PMOS transistor 10 that is always in a conductive state, and PMOS transistors 15 and 50 and NMOS transistors 60 and 70 that are connected in series from the PMOS transistor 10. Furthermore, PMOS
A current adjusting PMOS transistor 55 is connected in parallel to the transistor 50, and a current adjusting NMOS transistor 65 is connected in parallel to the NMOS transistor 60. In this configuration, the first conductive path is formed by the PMOS transistors 15, 50, 55 provided on the power supply side of the level sensing node N2, and the NMOS transistors 60, 65 provided on the ground side of the level sensing node N2.
A second conductive path is formed by 70. Also, N
MOS transistor 30 is provided to improve the switching speed of the data input buffer. Figure 1
As shown in, the PMOS transistors 15, 50, NM
The gate terminals of the OS transistors 60 and 70 are connected to receive the input signal VIN. The gate terminals of the PMOS transistor 55 and the NMOS transistor 65 are connected to receive the sensing clock CLK output from the power supply voltage sensing circuit 220.

In this circuit, a block S indicated by a dotted line
M is a Schmitt trigger stage, and the PMOS transistor and NM that constitute this Schmitt trigger stage SM
The input trip margin is determined by the channel size ratio with the OS transistor. This will be easily understood by those of ordinary skill in the art.

In the data input buffer of this example, P which is a current adjusting transistor according to the fluctuation of the power supply voltage VCC.
By turning on / off the MOS transistor 55 and the NMOS transistor 65, the Schmitt trigger stage S
The channel size ratio of the PMOS transistor and the NMOS transistor forming M is made variable to stabilize the input trip margin. The ON / OFF control of the transistors 55 and 65 at that time is performed by the sensing clock CLK which is a level sensing signal generated by comparing the power supply voltage VCC with the reference voltage VREF.
It is designed to be controlled using.

The level of the power supply voltage VCC is the reference voltage VRE.
When it becomes lower than the F level, the power supply voltage sensing circuit 22
A logic "low" sense clock CLK is generated from zero. The sensing clock CLK of logic "low" is sensed by the sensing unit 225.
Are input to the respective gate terminals of the PMOS transistor 55 and the NMOS transistor 65, and thereby the PMOS transistor 55 and the NMOS transistor 65 are turned on and off, respectively. This operation relatively increases the channel size ratio (Wp / Wn) of the Schmitt trigger stage SM, and improves the "low" input trip margin VIL. That is, when the sensing clock CLK is input at a logic "low", the Schmitt trigger stage SM
Three PMOS transistors 1
5, 50 and 55 act, and two transistors 60 and 70 act as NMOS transistors to perform a buffer operation.

On the other hand, when the level of the power supply voltage VCC becomes higher than the level of the reference voltage VREF, the power supply voltage sensing circuit 220 generates a logic "high" sensing clock CLK. The logic "high" sensing clock CLK is input to the gate terminals of the PMOS transistor 55 and the NMOS transistor 65 of the sensing unit 225, so that P
MOS transistor 55 and NMOS transistor 65
Are turned off and on respectively. By this operation, the channel size ratio of the Schmitt trigger stage SM (Wp / W
n) is relatively reduced and the "high" input trip margin VIH is improved. That is, when the sensing clock CLK is input as a logic "high", the two transistors 15 and 50 act as PMOS transistors of the Schmitt trigger stage SM, and the three transistors 60, 65 and 70 act as NMOS transistors. A buffer operation is performed.

Table 1 below shows the results of comparing the input trip margins of the input signals between the data input buffer of this embodiment and the conventional data input buffer shown in FIG. The power supply voltage VCC at this time is assumed to fluctuate between a minimum of 4V and a maximum of 8V. The level of internal power supply voltage Vint when the lowest level power supply voltage VCC is applied is 3V, and the level of internal power supply voltage Vint when the highest level power supply voltage VCC is applied is 5V.

[0028]

[Table 1]

In each of the configurations of the above embodiments, the level of the reference voltage VREF used in the power supply voltage sensing circuit 220 can be adjusted to a desired level according to the required operation characteristics of the data input buffer. Also, regarding various changes such as that the sensing accuracy of the power supply voltage sensing circuit 220 may be lowered to some extent in order to reduce the standby current, a person having ordinary knowledge in the art, in particular, It will be easy to understand without explaining.

[0030]

As described above, according to the present invention, in the data input buffer, the current amount (resistance value) by the PMOS and NMOS transistors of the Schmitt trigger stage can be adjusted according to the fluctuation of the power supply voltage.
The input trip level can be adjusted to an optimum value according to the power supply voltage (internal power supply voltage), the operational stability and reliability of the data input buffer are significantly improved, and a reliable operating state can be obtained.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an embodiment of a data input buffer according to the present invention.

2 is a circuit diagram showing a configuration example of a power supply voltage sensing circuit in the data input buffer of FIG.

3 is a circuit diagram showing a configuration example of a circuit for generating an enable signal provided to the power supply voltage sensing circuit of FIG.

FIG. 4 is a circuit diagram of a conventional data input buffer.

[Explanation of symbols]

210 driving unit 35, 40 inverter 220 power supply voltage sensing circuit 75, 85, 105 PMOS transistor 95, 100, 110, 115, 120 NMOS transistor 225 sensing unit 5 resistance 10, 15, 50, 55 PMOS transistor 60, 65, 70, 30 NMOS transistor 125, 130, 135, 145 Inverter 140 NAND gate VCC Power supply voltage Vint Internal power supply voltage VSS Ground voltage VIN Input signal VREF Reference voltage CLK Sensing clock φEN Enable signal CECLK Chip enable clock

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical indication location H03K 19/0175 8839-5J H03K 19/00 101 K

Claims (8)

[Claims] 1. A data input buffer of a semiconductor memory device, comprising: a power supply voltage sensing circuit for sensing a level of a power supply voltage applied from the outside to generate a level sensing signal; and an internal power supply voltage terminal and a level sensing node. Connected between the level sensing node and the ground voltage terminal, the first conductive path being capable of controlling the amount of current corresponding to the level sensing signal,
A second conductive path having a current amount controllable in response to a level detection signal. 2. The first conductive path includes at least two P-channel MOS transistors connected in series, the gate terminal of which receives an input signal, and the gate terminal of which receives a level sensing signal, and the channel of which is the P-channel MOS transistor. And a P-channel MOS transistor connected in parallel with each other, and the second conductive path has at least two N-channel MOS transistors connected in series, which receive an input signal at a gate terminal, and a level sensing signal at a gate terminal. 2. The data input buffer according to claim 1, further comprising: an N-channel MOS transistor having a channel connected in parallel to any of the N-channel MOS transistors. 3. The driving unit for driving a signal in the level sensing node, further comprising:
Described data input buffer. 4. A data input buffer of a semiconductor memory device, comprising: a power supply voltage sensing circuit for comparing a power supply voltage level applied from the outside with a reference voltage level to generate a level sensing signal indicating the power supply voltage level. A first transistor that receives the internal power supply voltage at one end of the channel and receives an input signal at the gate terminal, and a first transistor that is connected between the other end of the channel of the first transistor and the level sensing node and receives the input signal at the gate terminal. A second transistor, a third transistor connected between the other end of the channel of the first transistor and the level sensing node, and a third transistor receiving a level sensing signal at its gate terminal, and one end of the channel connected to the level sensing node and at its gate terminal The fourth transistor that receives the input signal and one end of the channel are connected to the level sensing node, and the gate terminal has the level. A fifth transistor that receives an intelligent signal; and a sixth transistor that is connected between the other end of each channel of the fourth and fifth transistors and the ground voltage terminal and that receives an input signal at its gate terminal. Data input buffer to be used. 5. The first, second and third transistors are P
The data input buffer according to claim 4, wherein the channel MOS transistor and the fourth, fifth and sixth transistors are N-channel MOS transistors. 6. A data input buffer using a Schmitt trigger circuit for converting an input signal to generate an output signal from a level sensing node, wherein the data input buffer is provided in parallel with a transistor on the power source side of the level sensing node, and the power supply voltage fluctuates. And a current amount adjusting transistor which is turned on / off in response to the current, and a current amount adjusting transistor which is provided in parallel with the transistor on the ground side of the level sensing node and is turned on / off in response to fluctuations in the power supply voltage. A data input buffer characterized in that 7. The data input buffer according to claim 6, wherein the current adjusting transistor is controlled by a power supply voltage sensing circuit for detecting a level of the power supply voltage with respect to the reference voltage and generating a level sensing signal. 8. The data input buffer according to claim 7, wherein the power supply voltage sensing circuit is operated by an enable signal generated based on a chip enable clock.