TW357351B - Semiconductor memory data input buffer - Google Patents

Semiconductor memory data input buffer

Info

Publication number
TW357351B
TW357351B TW083110315A TW83110315A TW357351B TW 357351 B TW357351 B TW 357351B TW 083110315 A TW083110315 A TW 083110315A TW 83110315 A TW83110315 A TW 83110315A TW 357351 B TW357351 B TW 357351B
Authority
TW
Taiwan
Prior art keywords
semiconductor memory
data input
input buffer
memory data
power supply
Prior art date
Application number
TW083110315A
Other languages
Chinese (zh)
Inventor
Kyung-W00 Kang
Original Assignee
Samsung Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Application granted granted Critical
Publication of TW357351B publication Critical patent/TW357351B/en

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G11C7/1084—Data input buffers, e.g. comprising level conversion circuits, circuits for adapting load
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • G11C5/143—Detection of memory cassette insertion or removal; Continuity checks of supply or ground lines; Detection of supply variations, interruptions or levels ; Switching between alternative supplies
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/003—Modifications for increasing the reliability for protection
    • H03K19/00369—Modifications for compensating variations of temperature, supply voltage or other physical parameters
    • H03K19/00384—Modifications for compensating variations of temperature, supply voltage or other physical parameters in field effect transistor circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
    • H03K19/018585—Coupling arrangements; Interface arrangements using field effect transistors only programmable

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Power Engineering (AREA)
  • Dram (AREA)
  • Logic Circuits (AREA)
  • Static Random-Access Memory (AREA)

Abstract

A semiconductor memory data input buffer, including: a power voltage sensing circuit, for sensing the voltage level fed from an external power supply and generating a power voltage sensing signal; the first conduction route, connected between an internal power voltage and a level sensing point, for controlling the current flow based on the power supply voltage sensing signal; and the second conduction route, connected between the level sensing point and a grounding, for controlling the current flow based on the power supply voltage sensing signal.
TW083110315A 1993-10-06 1994-11-08 Semiconductor memory data input buffer TW357351B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019930020596A KR0126254B1 (en) 1993-10-06 1993-10-06 Data input buffer for semiconductor memory device

Publications (1)

Publication Number Publication Date
TW357351B true TW357351B (en) 1999-05-01

Family

ID=19365299

Family Applications (1)

Application Number Title Priority Date Filing Date
TW083110315A TW357351B (en) 1993-10-06 1994-11-08 Semiconductor memory data input buffer

Country Status (4)

Country Link
JP (1) JPH07162281A (en)
KR (1) KR0126254B1 (en)
DE (1) DE4435649B4 (en)
TW (1) TW357351B (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI762317B (en) * 2021-05-17 2022-04-21 力晶積成電子製造股份有限公司 Sensing circuit and testing device

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100670683B1 (en) * 2005-03-31 2007-01-17 주식회사 하이닉스반도체 Data input buffer in semiconductor device
KR102294149B1 (en) 2015-02-13 2021-08-26 삼성전자주식회사 Schmitt trigger circuit and non-volatile memory device including the same
CN109036322B (en) * 2018-09-26 2023-11-03 北京集创北方科技股份有限公司 Input buffer, control method, driving device and display device
CN109036323B (en) * 2018-09-26 2023-11-03 北京集创北方科技股份有限公司 Output stage circuit, control method, driving device and display device

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4472647A (en) * 1982-08-20 1984-09-18 Motorola, Inc. Circuit for interfacing with both TTL and CMOS voltage levels
US4783607A (en) * 1986-11-05 1988-11-08 Xilinx, Inc. TTL/CMOS compatible input buffer with Schmitt trigger

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI762317B (en) * 2021-05-17 2022-04-21 力晶積成電子製造股份有限公司 Sensing circuit and testing device
US11450402B1 (en) 2021-05-17 2022-09-20 Powerchip Semiconductor Manufacturing Corporation Sensing circuit and test device

Also Published As

Publication number Publication date
DE4435649B4 (en) 2005-08-25
JPH07162281A (en) 1995-06-23
KR0126254B1 (en) 1998-04-10
KR950012703A (en) 1995-05-16
DE4435649A1 (en) 1995-04-13

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Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees