CN109036323B - Output stage circuit, control method, driving device and display device - Google Patents
Output stage circuit, control method, driving device and display device Download PDFInfo
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- CN109036323B CN109036323B CN201811124401.2A CN201811124401A CN109036323B CN 109036323 B CN109036323 B CN 109036323B CN 201811124401 A CN201811124401 A CN 201811124401A CN 109036323 B CN109036323 B CN 109036323B
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- 238000000034 method Methods 0.000 title claims abstract description 37
- 239000003990 capacitor Substances 0.000 claims abstract description 76
- 238000007599 discharging Methods 0.000 claims abstract description 16
- 238000001514 detection method Methods 0.000 claims description 33
- 101000869896 Homo sapiens Death-inducer obliterator 1 Proteins 0.000 description 17
- 101001053773 Homo sapiens Type I iodothyronine deiodinase Proteins 0.000 description 17
- 102100024063 Type I iodothyronine deiodinase Human genes 0.000 description 17
- 238000010586 diagram Methods 0.000 description 17
- 230000008569 process Effects 0.000 description 14
- 239000000872 buffer Substances 0.000 description 13
- 239000010409 thin film Substances 0.000 description 9
- 239000004973 liquid crystal related substance Substances 0.000 description 8
- 230000000630 rising effect Effects 0.000 description 4
- 230000001360 synchronised effect Effects 0.000 description 4
- 230000009471 action Effects 0.000 description 3
- 229910044991 metal oxide Inorganic materials 0.000 description 3
- 150000004706 metal oxides Chemical class 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
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- 239000000463 material Substances 0.000 description 1
- 230000011664 signaling Effects 0.000 description 1
- 238000002834 transmittance Methods 0.000 description 1
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3674—Details of drivers for scan electrodes
- G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3685—Details of drivers for data electrodes
- G09G3/3688—Details of drivers for data electrodes suitable for active matrices only
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- Theoretical Computer Science (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
- Liquid Crystal Display Device Control (AREA)
Abstract
The embodiment of the application discloses an output stage circuit, which is characterized by comprising: the first input module is used for providing a first charge-discharge path of the load capacitor according to the input signal, the second input module is used for providing a second charge-discharge path of the load capacitor according to the control signal, and the first input module and the second input module are used for charging and discharging the load capacitor to obtain an output signal. The size of the transistors in the input block is reduced while the drive capability of the circuit is improved. The embodiment of the application also discloses a control method, a driving device and a display device of the output stage circuit.
Description
Technical Field
The present application relates to the field of electronic circuits, and more particularly, to an output stage circuit, a control method, a driving device, and a display device.
Background
Output buffers (output buffers) are commonly used in various electronic devices to isolate signal inputs from signal outputs, so as to prevent the signal inputs from being affected by loads and enhance the ability of the signals to drive the loads. As shown in fig. 1, a conventional liquid crystal display device includes a plurality of source driver chips connected in cascade. The source driver chips are synchronized with each other by the synchronizing signal DIO, for example, after the source driver chip 120-1 receives data, the synchronizing signal DIO1 is provided to the source driver chip 120-2, the source driver chip 120-2 starts receiving data according to the synchronizing signal DIO1, and so on. After all the source driving chips receive the data, each source driving chip sequentially provides the corresponding gray scale voltage to the display panel 11.
Fig. 2 shows a schematic block diagram of data synchronization between prior art source driver chips, and fig. 2 shows a source driver chip 120-1 and a source driver chip 120-2, and after the source driver chip 120-1 receives data, a synchronization signal DIO1 is supplied to the source driver chip 120-2. Specifically, the output buffer 121 of the source driver chip 120-1 couples the load capacitor C according to the input signal Vin L The charging is performed to obtain the synchronization signal DIO1, the synchronization signal DIO1 finally obtains the synchronization signal dio1_in through the input buffer 122 of the source driving chip 120-2, and the source driving signal 120-2 starts to receive the data signal according to the synchronization signal dio1_in.
Fig. 3 shows an output stage circuit of a prior art output buffer, which comprises an input stage circuit and an output stage circuit. As shown in fig. 3, the conventional output stage 1212 includes a transistor M1 and a transistor M2, wherein the transistor M1 is a PMOS transistor (positive channel Metal Oxide Semiconductor, P-type Metal Oxide Semiconductor) and the transistor M2 is an NMOS transistor (N-type Metal Oxide Semiconductor). The input signal Vin is used to turn on the transistor M1, thereby forming a voltage from the power supply voltage VDD to the load capacitor C via the turned-on transistor M1 L To the load capacitor C L Charging is performed to obtain the synchronization signal DIO.
The output stage circuit of the prior art output buffer has the following problems: the output stage circuit in the prior art adopts a single transistor to charge the load capacitor to obtain the synchronous signal, and the application condition of the chip is unknown, so that the size and the working frequency of the load capacitor are unknown, and thus, over-design exists in circuit design. For example, in order to improve the driving capability of a circuit, the area of a transistor needs to be increased, so that peak current generated instantaneously when the transistor works is increased, the voltage drop of a power supply is increased when the circuit works, and the working voltage of a source electrode driving chip is insufficient due to the overlarge voltage drop of the power supply, so that the working performance of the source electrode driving chip is affected.
Disclosure of Invention
In view of the foregoing, it is an object of the present application to provide an output stage circuit, a control method, a driving device, and a display device, which can improve the driving capability of the circuit and reduce the size of transistors in an input module.
According to an aspect of the present application, there is provided an output stage circuit comprising: the first input module is used for providing a first charge-discharge path of the load capacitor according to the input signal, the second input module is used for providing a second charge-discharge path of the load capacitor according to the control signal, and the first input module and the second input module are used for charging and discharging the load capacitor to obtain an output signal. And the second input module is used for charging and discharging the load capacitor to obtain the output signal.
Preferably, the first input module includes a first transistor and a second transistor connected in series between the supply voltage and ground, control terminals of the first transistor and the second transistor being configured to receive the input signal, the first transistor being configured to provide a first charging path for the supply voltage to the load capacitor, and the second transistor being configured to provide a first discharging path for the load capacitor.
Preferably, the second input module includes a third transistor and a fourth transistor connected in series between the power supply voltage and ground, a control terminal of the third transistor being configured to receive a first control signal, the third transistor being configured to provide the power supply voltage to a second charging path of the load capacitor, a control terminal of the fourth transistor being configured to receive a second control signal, and the fourth transistor being configured to provide a second discharging path of the load capacitor.
Preferably, the first control signal and the second control signal are mutually inverted signals.
Preferably, the output stage circuit further comprises: the first control module is connected with the control end of the third transistor to provide the first control signal; and the second control module is connected with the control end of the fourth transistor to provide the second control signal.
Preferably, the output stage circuit further includes a first time detection module, configured to detect a precharge time of the first input module, where when the precharge time is a first preset time, the first time detection module provides a first trigger signal to the first control module, and the first control module provides the first control signal according to the first trigger signal.
Preferably, the output stage circuit further includes a second time detection module, configured to detect a pre-discharge time of the first input module, where the second time detection module provides a second trigger signal to the second control module when the pre-discharge time is a second preset time, and the second control module provides the second control signal according to the second trigger signal.
Preferably, the output stage circuit further includes a first voltage detection module, configured to detect a voltage value of the load capacitor, where when the voltage value is a first preset voltage, the first voltage detection module provides a third trigger signal to the first control module, and the second control module provides the first control signal according to the third trigger signal.
Preferably, the output stage circuit further includes a second voltage detection module, configured to detect a voltage value of the load capacitor, where when the voltage value is a second preset voltage, the second voltage detection module provides a fourth trigger signal to the second control module, and the second control module provides the second control signal according to the fourth trigger signal.
According to a second aspect of the present application, there is provided a control method of an output stage circuit including a first input module, a second input module, and a load capacitance, wherein the control method includes: providing an input signal; starting a first input module to precharge the load capacitor; and starting a second input module, wherein the first input module and the second input module charge the load capacitor at the same time to obtain an output signal.
Preferably, the step of opening the second input module includes: detecting the charging time of the first input module; when the charging time reaches a preset time, providing a first trigger signal; obtaining a first control signal according to the first trigger signal; and starting the second input module according to the first control signal.
Preferably, the step of opening the second input module includes: detecting a voltage value of the load capacitor; when the voltage of the load capacitor reaches a preset voltage, providing a second trigger signal; obtaining a second control signal according to the second trigger signal; and starting the second input module according to the second control signal.
According to a third aspect of the present application there is provided a driving apparatus comprising a plurality of driving circuits, wherein each of said driving circuits comprises an output stage circuit as described above.
Preferably, the driving circuit includes a gate driving chip or a source driving chip, and the driving device includes a gate driving device or a source driving device.
According to a fourth aspect of the present application, there is provided a display device comprising: gate driving means for providing a plurality of gate driving signals; a source driving device for providing a plurality of gray-scale data; and a display panel including a plurality of pixel units arranged in an array, and a plurality of gate lines and a plurality of data lines, the display panel receiving the plurality of gate driving signals via the plurality of gate lines to select the plurality of pixel units by rows, and receiving the plurality of gray scale data by columns via the plurality of data lines to be supplied to the selected pixel units to achieve image display, wherein the gate driving device and/or the source driving device includes the above-described output stage circuit.
The application provides an output stage circuit with adjustable driving capability, which comprises a first input module and a second input module, wherein the first input module can precharge a load capacitor according to an input signal, and the second input module can charge the load capacitor according to a control signal provided by a control module so as to obtain an output signal. The driving capability of the circuit is improved, and compared with the existing circuit, the size of the transistors in the first input module and the second input module can be relatively reduced, so that the driving capability is ensured, and meanwhile, the area consumed by the circuit can be reduced. Meanwhile, compared with the existing circuit, the output stage circuit has smaller voltage drop of the power supply voltage during operation, can not influence the operation of the later stage circuit, and has higher circuit stability.
The application also provides a control method, a driving device and a display device of the output stage circuit, which can improve the driving capability of the circuit and reduce the size of the transistor of the input module at the same time, thereby having higher stability of the circuit.
Drawings
The above and other objects, features and advantages of the present application will become more apparent from the following description of embodiments of the present application with reference to the accompanying drawings.
Fig. 1 shows a schematic structure of a liquid crystal display device according to the related art.
Fig. 2 shows a schematic block diagram for achieving data synchronization between source driver chips according to the prior art.
Fig. 3 shows a schematic diagram of the structure of an output stage circuit of an output buffer according to the prior art.
Fig. 4 shows an equivalent circuit diagram of a liquid crystal display device according to a first embodiment of the present application.
Fig. 5 illustrates a schematic structure of the source driving device of fig. 4.
Fig. 6 is a schematic diagram showing a structure of synchronizing data between source driving chips in fig. 5.
Fig. 7 shows a timing chart of the operation of synchronizing data between the source driving chips in fig. 6.
Fig. 8 shows a schematic diagram of the structure of an output stage circuit according to a second embodiment of the application.
Fig. 9 shows a schematic diagram of an output stage circuit according to a third embodiment of the application.
Fig. 10 shows a schematic diagram of a charging process of an output stage circuit according to a third embodiment of the present application.
Fig. 11 shows a schematic diagram of the structure of an output stage circuit according to a fourth embodiment of the present application.
Fig. 12 shows a schematic diagram of a charging process of an output stage circuit according to a fourth embodiment of the present application.
Fig. 13 shows a flow chart of a control method of the output stage circuit according to the fifth embodiment of the present application.
Fig. 14 shows a flow chart of a control method of an output stage circuit according to a sixth embodiment of the present application.
Detailed Description
The application will be described in more detail below with reference to the accompanying drawings. Like elements are denoted by like reference numerals throughout the various figures. For clarity, the various features of the drawings are not drawn to scale. Furthermore, some well-known portions may not be shown.
Numerous specific details of the application, such as device structures, materials, dimensions, processing techniques and technologies, are set forth in the following description in order to provide a thorough understanding of the application. However, as will be understood by those skilled in the art, the present application may be practiced without these specific details.
The application may be embodied in various forms, some examples of which are described below.
Fig. 4 shows an equivalent circuit diagram of a liquid crystal display device according to a first embodiment of the present application.
The liquid crystal display device 200 includes a display panel 210, a gate driving device 220, a source driving device 230, and a timing control device 240. The display panel 210 is, for example, a liquid crystal display panel, and includes a plurality of thin film transistors T and a plurality of pixel capacitors C formed between the pixel electrode and the common electrode LC . The plurality of thin film transistors T constitute an array. The timing control device 240 receives display data from the front end via the data interface, generates a timing signal and a gray scale driving signal according to the display data, and the timing control device 240 is connected to the gate driving device 220 and the source driving device 230, thereby providing various timing signals to the gate driving device 220 and the source driving device 230. The gate driving device 220 is respectively connected to gates of the thin film transistors T of the corresponding rows via a plurality of gate scan lines for supplying gate voltages G1 to Gm in a scanning manner so that the thin film transistors of different rows are turned on in one image frame period. The source driving device 230 is connected to the sources of the thin film transistors T of the corresponding columns via a plurality of source data lines, respectively, for providing gray scale voltages S1 to Sn corresponding to gray scales to the thin film transistors T of the columns, respectively, when the thin film transistors T of the respective rows are turned on. Where m and n are natural numbers. By a means ofThe drains of the thin film transistors T are respectively connected to a corresponding pixel capacitor C LC 。
In the gate state, the source driving device 230 applies gray voltages to the pixel capacitor C via the source data line and the thin film transistor T LC And (3) upper part. Pixel capacitance C LC The voltage is applied to the liquid crystal molecules to change the orientation of the liquid crystal molecules, thereby achieving light transmittance corresponding to gray scale. In order to maintain the voltage between the refresh periods of the pixel, the pixel capacitance C LC The storage capacitor Cs may be connected in parallel for a longer holding time.
The source driving device 230 may be implemented by a plurality of source driving chips, and as shown in fig. 5, the source driving device 230 includes source driving chips 231-23n. The source driver chips 231-23n perform data synchronization via the synchronization signal DIO, for example, after the source driver chip 231 receives data, the synchronization signal DIO1 is provided to the source driver chip 232, the source driver chip 232 starts receiving data according to the synchronization signal DIO1, and so on.
Fig. 6 is a schematic diagram showing a structure of synchronizing data between source driving chips in fig. 5. As shown in fig. 6, the source driving chips each include an input buffer and an output buffer. The output buffer 240 of the source driving chip 231 is coupled to the load capacitor C according to the input signal Vin provided inside the chip L Charging and discharging are performed to obtain a synchronization signal DIO1. The input buffer 250 of the source driver chip 232 receives the synchronization signal DIO1, and obtains the synchronization signal dio1_in according to the synchronization signal DIO1, where the synchronization signal dio1_in is used for controlling the source driver chip 232 to receive the data signal after clock synchronization.
Fig. 7 shows a timing chart of the operation of synchronizing data between the source driving chips in fig. 6. As shown in fig. 7, one period of the clock signal CLK is 3T, where T is a predetermined clock period, for example, a minimum clock period of the system clock signal. The input buffer 250 is generally composed of schmitt trigger and inverter, so that the synchronization signal dio1_in is considered as logic high after the synchronization signal DIO1 rises to 0.5VDD, the time for the synchronization signal DIO1 to rise from 0 to 0.5VDD is defined as Tsr, the gate delay of the synchronization signal DIO1 to the synchronization signal dio1_in is defined as Tgd, and the synchronization signal dio1 and the synchronization signal dio1_in of the embodiment of the present application must satisfy tsr+tgd < = 3T because the synchronization signal dio1_in must be established before the next rising edge of the clock signal CLK arrives.
Fig. 8 shows a schematic diagram of the structure of an output stage circuit according to a second embodiment of the application. FIG. 8 shows an output stage circuit of the output buffer 240 of FIG. 6. As shown in FIG. 8, the output stage circuit 241 is coupled to the load capacitor C according to the input signal Vin L Charging and discharging are performed to obtain a synchronization signal DIO1. The output stage circuit 241 includes a first input module 244, a second input module 242, and a control module 243. The first input module 244 is used for providing an input signal Vin to the load capacitor C L Providing a first charge-discharge path for a load capacitor C L Charging and discharging are performed. The second input module 242 is used for providing a control signal to the load capacitor C according to the control module 243 L Providing a second charge-discharge path for the load capacitor C L And performing secondary charge and discharge to obtain a synchronous signal DIO1.
In the present embodiment, the first input module 244 includes a first inverter circuit including a transistor M3 and a transistor M4. The control terminals of the transistors M3 and M4 are connected to each other to receive the input signal Vin, the first path terminal of the transistor M3 is for receiving the power supply voltage VDD, the first path terminal of the transistor M4 is grounded, the second path terminals of the transistors M3 and M4 are connected to each other, the intermediate node of the transistors M3 and M4 is connected to the load capacitor C L Is connected to the first end of the housing. The transistor M3 is, for example, a PMOS transistor, and the transistor M4 is, for example, an NMOS transistor. The transistor M3 is turned on under the control of the input signal Vin to provide the power voltage VDD to the load capacitor C L Is provided. The transistor M4 is turned on under the control of the input signal Vin to provide a load capacitance C L A first discharge path to ground.
The second input module 242 includes transistors M5 and M6. The first path of the transistor M5 is for receiving the power voltage VDD, and the first path of the transistor M6 is for grounding. The second path terminals of the transistor M5 and the transistor M6 are connected with the first input module 241 and the load capacitor C L Is connected to the intermediate node of (c). The transistor M5 is for example a PMOS transistor,the transistor M6 is, for example, an NMOS transistor. The control terminal of the transistor M5 is for receiving the first control signal V1, and is turned on under the control of the first control signal V1 to provide the power voltage VDD to the load capacitor C L Is provided. The control terminal of the transistor M6 is used for receiving the second control signal V2 and is used for being conducted under the control of the second control signal V2 to provide the load capacitor C L A second discharge path to ground.
The control module 243 includes a first control module 2431 and a second control module 2432, the first control module 2431 is configured to provide a first control signal V1 to the transistor M5, and the second control module 2432 is configured to provide a second control signal V2 to the transistor M6. Wherein the first control signal V1 and the second control signal V2 are mutually inverted signals.
Fig. 9 shows a schematic diagram of an output stage circuit according to a third embodiment of the application. As shown in fig. 9, the output stage circuit 340 includes a first input module 341, a second input module 342, a control module 343, and a time detection module 344. The structures and connection relationships of the first input module 341, the second input module 342, and the control module 343 are the same as those of the first input module 244, the second input module 242, and the control module 243 in the output stage circuit of the second embodiment shown in fig. 8, and are not described herein.
The time detection module 344 includes a first time detection module 3441 and a second time detection module 3442, where the first time detection module 3441 is configured to detect a precharge time of the first input module 341, and when the precharge time reaches a first preset time, provide a first trigger signal to the first control module 3431, and the first control module 3431 obtains a first control signal V1 according to the first trigger signal. The second time detection module 3442 is configured to detect the pre-discharge time of the first input module, and when the pre-discharge time reaches a second preset time, provide a second trigger signal to the second control module 3432, and the second control module 3432 obtains a second control signal V2 according to the second trigger signal.
Fig. 10 shows a schematic diagram of a charging process of an output stage circuit according to a third embodiment of the present application. As shown in FIG. 10, the horizontal axis represents time in T, where T is the predetermined clockThe period, e.g., the minimum clock period of the system clock signal. The vertical axis represents the voltage value of the load capacitance in VDD, where VDD is the supply voltage at which the system operates. Curves a, b, c represent the case of charging different load capacitances or at different operating frequencies, respectively. Curve a shows that the capacitance value of the load capacitance is small or the operating frequency is low, curve b shows that the capacitance value of the load capacitance is medium or the operating frequency is medium, and curve c shows that the capacitance value of the load capacitance is large or the operating frequency is high. The working principle of the present embodiment is described in detail below with reference to fig. 9 and 10. As shown in fig. 9, first, the transistor M3 is turned on according to the input signal Vin, and the load capacitor C is connected to the power supply voltage VDD L The precharge is performed, followed by a detection of the charge time by the first time detection module 3441, when the charge time reaches 1.5T, where T is a predetermined clock period, such as the minimum clock period of the system clock signal. The first time detection module 3441 provides a first trigger signal to the first control module 3431, the first control module 3431 provides a first control signal V1 according to the first trigger signal, turns on the transistor M5, and the transistor M5 provides the power supply voltage VDD to the load capacitor C L The transistor M3 and the transistor M5 together charge the load capacitor to obtain the synchronization signal DIO1. As shown in fig. 10, in the precharge process, the voltage rising rates of different load capacitances are different, and the voltage of the load capacitance rises faster because the capacitance value of the load capacitance of the curve a is smaller, and reaches 0.5VDD before 1.5T; since the capacitance value of the load capacitor of the curve c is large, the voltage of the load capacitor rises slowly. When the time is 1.5T, the transistor M5 is turned on, and for curve a, because the voltage value of the load capacitor is larger at this time, the voltage difference between the source and the drain of the transistor M5 is small, so the transistor M5 provides a smaller driving current, and the voltage value of the load capacitor is slightly increased compared with the previous voltage value. For curve c, since the voltage value of the load capacitor at this time is small, the voltage difference between the source and drain of the transistor M5 is large, and thus the transistor M5 provides a large driving current, the rising rate of the voltage of the load capacitor increases significantly. The times at which curves a, b, c rise to 0.5VDD are t1, t2, and t3, respectively, which times are required to meet the minimum time Tsr specified by the circuit.
It should be noted that, the preset time of the present application is not limited to the embodiment, and one skilled in the art may select the preset time according to the specific situation.
In this embodiment, the discharging process and the charging process of the output stage circuit are similar, and thus will not be described again.
Fig. 11 shows a schematic diagram of the structure of an output stage circuit according to a fourth embodiment of the present application. As shown in fig. 11, the output stage circuit 440 includes a first input module 441, a second input module 442, a control module 443, and a voltage detection module 444. The structures and connection relationships of the first input module 441, the second input module 442, and the control module 443 are the same as those of the first input module 244, the second input module 242, and the control module 243 in the output stage circuit of the second embodiment shown in fig. 8, and are not described herein again.
The voltage detection module 444 includes a first voltage detection module 4441 and a second voltage detection module 4442, the first voltage detection module 4441 being configured to detect the load capacitance C L When the voltage value of the load capacitor reaches the first preset voltage, a third trigger signal is provided to the first control module 4431, and the first control module 4431 obtains a first control signal V1 according to the third trigger signal. The second voltage detection module 4442 is used for detecting the load capacitance C L When the voltage value of the load capacitor reaches the second preset voltage, a fourth trigger signal is provided to the second control module 4432, and the second control module 4432 obtains a second control signal V2 according to the fourth trigger signal.
Fig. 12 shows a schematic diagram of a charging process of an output stage circuit according to a fifth embodiment of the present application. As shown in fig. 12, the horizontal axis represents time in T, where T is a predetermined clock period, such as the minimum clock period of the system clock signal. The vertical axis represents the voltage value of the load capacitance in VDD, where VDD is the supply voltage at which the system operates. Curves a, b, c represent the case of charging different load capacitances or at different operating frequencies, respectively. Curve a shows that the capacitance value of the load capacitance is small or the operating frequency is low, curve b shows that the capacitance value of the load capacitance is medium or the operating frequency is medium, curvec represents that the capacitance value of the load capacitance is large or the operating frequency is high. The working principle of the present embodiment is described in detail below with reference to fig. 11 and 12. As shown in fig. 11, first, the transistor M3 is turned on according to the input signal Vin, and the load capacitor C is connected to the power supply voltage VDD L The precharge is performed, and then the voltage of the load capacitor is detected by the first voltage detection module 4441, when the voltage value reaches 0.3VDD, where VDD is the power supply voltage. The first voltage detection module 4441 provides a third trigger signal to the first control module 4431, the first control module 4431 provides the first control signal V1 according to the third trigger signal, turns on the transistor M5, and the transistor M5 provides the power supply voltage VDD to the load capacitor C L The transistor M3 and the transistor M5 together charge the load capacitor to obtain the synchronization signal DIO1. When the voltage of the load capacitor rises to 0.3VDD, the transistor M5 is turned on, and the voltage difference across the source and drain of the transistor M5 in the curves a, b, and c is the same, so that the rising rates of the voltages of the load capacitors in the curves a, b, and c are the same. The times at which curves a, b, c rise to 0.5VDD are t1, t2, and t3, respectively, and as such, the times are required to meet the minimum time Tsr specified by the circuit.
It should be noted that, the voltage value of the preset voltage in the present application is not limited to the embodiment, and one skilled in the art may select the voltage value of the preset voltage according to the specific situation.
In this embodiment, the discharging process and the charging process of the output stage circuit are similar, and thus will not be described again.
The output stage circuit is suitable for a time sequence control chip, a source electrode driving chip or a grid electrode driving chip adopting a mini-LVDS (Low Voltage Differential Signaling, low voltage differential signal) interface and an RSDS (Reduced Swing Differential Signal, low swing differential signal) interface. The mini-LVDS interface and the RSDS interface have very low electromagnetic interference (EMI) and can provide a very high bandwidth for display driving.
In the above embodiments, the output stage circuit of the present application is described by taking the source driving chip as an example, but the present application is not limited thereto, and the output stage circuit of the present application is also applicable to synchronous data between the gate driving chips or between the timing control chip and the gate driving chip or between the timing control chip and the source driving chip.
According to another aspect of the present application there is provided a driving device, for example a gate driving device or a source driving device, comprising a plurality of gate driving chips or source driving chips, respectively, each gate driving chip and/or source driving chip comprising an output stage circuit as described above.
Fig. 13 shows a flow chart of a control method of the output stage circuit according to the fifth embodiment of the present application. The output stage circuit comprises a first input module and a second input module. As shown in fig. 13, the control method includes:
step S110, providing an input signal;
step S120, a first input module is started according to an input signal, and a load capacitor is charged;
step S130, detecting the charging time of the first input module;
step S140, judging whether the charging time reaches the preset time, if so, executing step S150, starting the second input module, and charging the load capacitor by the first input module and the second input module. Specifically, when the charging time reaches the preset time, a first trigger signal is provided, then a first control signal is obtained according to the first trigger signal, and the second input module is started according to the first control signal. If the charging time does not reach the preset time, the process returns to step S130.
Fig. 14 shows a flow chart of a control method of an output stage circuit according to a sixth embodiment of the present application. The output stage circuit comprises a first input module and a second input module. As shown in fig. 14, the control method includes:
step S210, providing an input signal;
step S220, a first input module is started according to an input signal, and a load capacitor is charged;
step S230, detecting the voltage value of the load capacitor;
step S240, determining whether the voltage of the load capacitor reaches a preset voltage, if so, performing step S250, starting the second input module, and charging the load capacitor by the first input module and the second input module. Specifically, when the voltage of the load capacitor reaches a preset voltage, a second trigger signal is provided, then a second control signal is obtained according to the second trigger signal, and the second input module is started according to the second control signal. If the voltage of the load capacitor does not reach the preset voltage, the process returns to step S230.
In summary, the present application provides an output stage circuit with adjustable driving capability, which includes a first input module and a second input module, wherein the first input module can precharge a load capacitor according to an input signal, and the second input module charges the load capacitor according to a control signal provided by a control module to obtain an output signal. The driving capability of the circuit is improved, and compared with the existing circuit, the size of the transistors in the first input module and the second input module can be relatively reduced, so that the driving capability is ensured, the area consumed by the circuit can be reduced, and the peak current is reduced. Meanwhile, compared with the existing circuit, the output stage circuit has smaller voltage drop of the power supply voltage during operation, can not influence the operation of the later stage circuit, and has higher circuit stability.
The application also provides a control method of the output stage circuit, a driving device and a source driving device of the display device.
It should be noted that in this document relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.
Embodiments in accordance with the present application, as described above, are not intended to be exhaustive or to limit the application to the precise embodiments disclosed. Obviously, many modifications and variations are possible in light of the above teaching, including but not limited to, variations in the local construction of the circuit, and replacement of type or model of component. The embodiments were chosen and described in order to best explain the principles of the application and the practical application, to thereby enable others skilled in the art to best utilize the application and various modifications as are suited to the particular use contemplated. The application is limited only by the claims and the full scope and equivalents thereof.
Claims (7)
1. An output stage circuit, comprising: a first input module and a second input module connected in parallel between the supply voltage and ground,
the first input module comprises a first transistor and a second transistor connected in series between the supply voltage and ground, the control terminals of the first transistor and the second transistor being for receiving an input signal, the first transistor being for providing a first charging path for the supply voltage to a load capacitance, the second transistor being for providing a first discharging path for the load capacitance,
the second input module comprises a third transistor and a fourth transistor connected in series between the supply voltage and ground, the control terminal of the third transistor being arranged to receive a first control signal, the third transistor being arranged to provide the supply voltage to a second charging path of the load capacitance, the control terminal of the fourth transistor being arranged to receive a second control signal, the fourth transistor being arranged to provide a second discharging path of the load capacitance,
the first input module and the second input module are used for charging and discharging the load capacitor to obtain an output signal,
wherein the output stage circuit further comprises:
the first control module is connected with the control end of the third transistor to provide the first control signal;
the second control module is connected with the control end of the fourth transistor to provide the second control signal;
the first time detection module is used for detecting the precharge time of the first input module, and when the precharge time is a first preset time, the first time detection module provides a first trigger signal for the first control module, and the first control module provides the first control signal according to the first trigger signal; and
the second time detection module is used for detecting the pre-discharge time of the first input module, and when the pre-discharge time is a second preset time, the second time detection module provides a second trigger signal for the second control module, and the second control module provides the second control signal according to the second trigger signal.
2. An output stage circuit, comprising: a first input module and a second input module connected in parallel between the supply voltage and ground,
the first input module comprises a first transistor and a second transistor connected in series between the supply voltage and ground, the control terminals of the first transistor and the second transistor being for receiving an input signal, the first transistor being for providing a first charging path for the supply voltage to a load capacitance, the second transistor being for providing a first discharging path for the load capacitance,
the second input module comprises a third transistor and a fourth transistor connected in series between the supply voltage and ground, the control terminal of the third transistor being arranged to receive a first control signal, the third transistor being arranged to provide the supply voltage to a second charging path of the load capacitance, the control terminal of the fourth transistor being arranged to receive a second control signal, the fourth transistor being arranged to provide a second discharging path of the load capacitance,
the first input module and the second input module are used for charging and discharging the load capacitor to obtain an output signal,
wherein the output stage circuit further comprises:
the first control module is connected with the control end of the third transistor to provide the first control signal;
the second control module is connected with the control end of the fourth transistor to provide the second control signal;
the first voltage detection module is used for detecting the voltage value of the load capacitor, and when the voltage value is a first preset voltage, the first voltage detection module provides a third trigger signal for the first control module, and the first control module provides the first control signal according to the third trigger signal; and
the second voltage detection module is used for detecting the voltage value of the load capacitor, and when the voltage value is a second preset voltage, the second voltage detection module provides a fourth trigger signal for the second control module, and the second control module provides the second control signal according to the fourth trigger signal.
3. A control method for controlling the output stage circuit of claim 1, the output stage circuit comprising: a first input module and a second input module connected in parallel between a supply voltage and ground, wherein the control method comprises:
starting the first input module according to an input signal, and precharging a load capacitor;
detecting the charging time of the first input module;
when the charging time reaches a preset time, providing a first trigger signal;
obtaining a first control signal according to the first trigger signal;
and starting the second input module according to the first control signal, wherein the first input module and the second input module charge the load capacitor together to obtain an output signal.
4. A control method for controlling the output stage circuit of claim 2, the output stage circuit comprising: a first input module and a second input module connected in parallel between a supply voltage and ground, wherein the control method comprises:
starting the first input module according to an input signal, and precharging a load capacitor;
detecting a voltage value of the load capacitor;
when the voltage of the load capacitor reaches a preset voltage, providing a second trigger signal;
obtaining a second control signal according to the second trigger signal;
and starting the second input module according to the second control signal, wherein the first input module and the second input module charge the load capacitor together to obtain an output signal.
5. A driving device comprising a plurality of driving circuits, wherein each of the driving circuits comprises the output stage circuit of any one of claims 1 or 2.
6. The driving device according to claim 5, wherein the driving circuit comprises a gate driving chip or a source driving chip, and the driving device comprises a gate driving device or a source driving device.
7. A display device, comprising:
gate driving means for providing a plurality of gate driving signals;
a source driving device for providing a plurality of gray-scale data; and
a display panel including a plurality of pixel units arranged in an array, a plurality of gate lines and a plurality of data lines,
the display panel receives the plurality of gate driving signals via the plurality of gate lines to select the plurality of pixel cells in a row, and receives the plurality of gray scale data in a column via the plurality of data lines to be supplied to the selected pixel cells to realize image display,
wherein the gate driving means and/or the source driving means comprise the output stage circuit of any one of claims 1 or 2.
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