CN110806779A - Push-pull type LDO circuit based on voltage flip follower structure - Google Patents

Push-pull type LDO circuit based on voltage flip follower structure Download PDF

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CN110806779A
CN110806779A CN201911141377.8A CN201911141377A CN110806779A CN 110806779 A CN110806779 A CN 110806779A CN 201911141377 A CN201911141377 A CN 201911141377A CN 110806779 A CN110806779 A CN 110806779A
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transistor
gate
drain
source
voltage
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鲁纬
段志奎
于昕梅
蒋业文
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Foshan University
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    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
    • G05F3/02—Regulating voltage or current
    • G05F3/08—Regulating voltage or current wherein the variable is dc
    • G05F3/10—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
    • G05F3/16—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
    • G05F3/20—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
    • G05F3/26—Current mirrors

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Abstract

The invention discloses a push-pull type LDO circuit based on a voltage flip follower structure, which comprises: the circuit comprises an input voltage end, an output voltage end, a grounding end, a biasing circuit and a control circuit. The fourteenth transistor, the fifteenth transistor and the power tube form a voltage reversal follower structure, and a bias circuit and a control circuit are utilized, so that the transient response capability of the whole circuit is improved. The invention is mainly used in the technical field of integrated circuits.

Description

Push-pull type LDO circuit based on voltage flip follower structure
Technical Field
The invention relates to the technical field of integrated circuits, in particular to a push-pull LDO (low dropout regulator) circuit based on a voltage flip follower structure.
Background
With the rapid development of semiconductor process technology, the supply voltage of an integrated circuit is lower and lower, which puts higher and higher requirements on the accuracy of the output voltage of an input voltage end, the response speed, the noise performance and the like. Therefore, the input voltage terminal management module plays an increasingly important role in the electronic industry. The LDO is used as an important input voltage end management module, and is widely applied to SoC chip design due to its characteristics of low noise, low cost, fast transient characteristics, and the like. How to further improve the output accuracy and transient response performance of the LDO is an urgent need in practical applications.
Disclosure of Invention
The present invention is directed to a push/pull LDO circuit based on a voltage flip-follower structure, which solves one or more of the problems in the prior art and provides at least one of the advantages.
The solution of the invention for solving the technical problem is as follows: a push-pull LDO circuit based on a voltage flip-follower structure, comprising: the circuit comprises an input voltage end, an output voltage end, a grounding end, a biasing circuit and a control circuit;
the bias circuit includes: a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, and a resistor, wherein a source of the first transistor, a gate of the second transistor, a source of the third transistor, a source of the fourth transistor, and a source of the sixth transistor are all connected to the input voltage terminal, a gate of the first transistor is connected to a gate of the fourth transistor and a gate of the sixth transistor, respectively, a drain of the first transistor is connected to a gate of the third transistor and a drain of the second transistor, a drain of the third transistor is connected to a drain of the fourth transistor, a drain of the fifth transistor and a gate of the fifth transistor, a gate of the fifth transistor is connected to a gate of the seventh transistor, and a drain of the seventh transistor is connected to a drain of the sixth transistor and a gate of the sixth transistor, respectively, the source electrode of the seventh transistor is connected with the upper end of the resistor, and the lower end of the resistor, the source electrode of the fifth transistor and the source electrode of the second transistor are respectively connected with the ground terminal;
the control circuit includes: the power supply circuit comprises an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor, a twelfth transistor, a thirteenth transistor, a fourteenth transistor, a fifteenth transistor, a sixteenth transistor, a seventeenth transistor, an eighteenth transistor, a nineteenth transistor and a power tube, wherein a source of the eighth transistor, a source of the twelfth transistor, a source of the fourteenth transistor and a source of the power tube are all connected with an input voltage end, a source of the ninth transistor is connected with a drain of the eighth transistor, a gate of the eighth transistor is connected with a gate of the sixth transistor, a gate of the ninth transistor is respectively connected with a gate of the fourteenth transistor and a gate of the twelfth transistor, a drain of the ninth transistor is respectively connected with a gate of the ninth transistor and a source of the tenth transistor, and a gate of the tenth transistor is respectively connected with a drain of the tenth transistor, A gate of the sixteenth transistor is connected to a drain of the tenth transistor, a gate of the eleventh transistor is connected to a drain of the eleventh transistor and a gate of the seventeenth transistor, a drain of the twelfth transistor is connected to a drain of the thirteenth transistor and a gate of the fifteenth transistor, a drain of the fifteenth transistor is connected to a drain of the fourteenth transistor and a gate of the power transistor, a drain of the power transistor, a source of the sixteenth transistor, a drain of the eighteenth transistor, a gate of the eighteenth transistor and a gate of the nineteenth transistor are all connected to the output voltage terminal, a source of the eighteenth transistor is connected to a gate of the thirteenth transistor and a drain of the nineteenth transistor, a source of the thirteenth transistor, a source of the eleventh transistor, a source of the seventeenth transistor, a drain of the seventeenth transistor, a gate of the fifteenth transistor, a drain of the power transistor, a, And the sources of the nineteenth transistor are all connected with the ground terminal.
Further, the first transistor, the third transistor, the fourth transistor and the sixth transistor are all PMOS transistors, and the second transistor, the fifth transistor and the seventh transistor are all NMOS transistors.
Further, the eighth transistor, the ninth transistor, the tenth transistor, the twelfth transistor, the fourteenth transistor, the sixteenth transistor and the power transistor are all PMOS transistors, and the eleventh transistor, the thirteenth transistor, the fifteenth transistor, the seventeenth transistor, the eighteenth transistor and the nineteenth transistor are all NMOS transistors.
The invention has the beneficial effects that: the fourteenth transistor, the fifteenth transistor and the power tube form a voltage reversal follower structure, and a bias circuit and a control circuit are utilized, so that the transient response capability of the whole circuit is improved.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings used in the description of the embodiments will be briefly described below. It is obvious that the described drawings are only a part of the embodiments of the invention, not all embodiments, and that a person skilled in the art will be able to derive other designs and drawings from these drawings without the exercise of inventive effort.
FIG. 1 is a schematic diagram of a circuit connection structure of a push-pull LDO circuit based on a voltage flip-follower structure.
Detailed Description
Reference will now be made in detail to the present preferred embodiments of the present invention, examples of which are illustrated in the accompanying drawings, wherein like reference numerals refer to like elements throughout.
In the description of the present invention, it should be understood that the orientation or positional relationship referred to in the description of the orientation, such as up, down, front, rear, left, right, etc., is the orientation or positional relationship shown in the drawings, and is only for convenience of description and simplification of the description of the present invention, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus, should not be construed as limiting the present invention.
In the description of the invention, if words such as "a number" or the like are used, the meaning is one or more, the meaning of a plurality is two or more, more than, less than, more than, etc. are understood as not including the number, and more than, less than, more than, etc. are understood as including the number.
In the description of the present invention, unless otherwise explicitly defined, terms such as setup, installation, connection, and the like should be understood in a broad sense, and those skilled in the art can reasonably determine the specific meanings of the terms in the present invention in combination with the detailed contents of the technical solutions.
Embodiment 1, referring to fig. 1, a push-pull LDO circuit based on a voltage flip-follower structure includes: an input voltage terminal VDD, an output voltage terminal VOUT, and a ground terminal GND. Further comprising: a bias circuit 100 and a control circuit 200. The bias circuit 100 includes: a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, a fifth transistor M5, a sixth transistor M6, a seventh transistor M7 and a resistor Rs, wherein a source of the first transistor M1, a gate of the second transistor M2, a source of the third transistor M3, a source of the fourth transistor M4 and a source of the sixth transistor M6 are all connected to the input voltage terminal VDD, a gate of the first transistor M1 is respectively connected to a gate of the fourth transistor M4 and a gate of the sixth transistor M6, a drain of the first transistor M1 is respectively connected to a gate of the third transistor M3 and a drain of the second transistor M2, a drain of the third transistor M3 is respectively connected to a drain of the fourth transistor M847, a drain of the fifth transistor M5 and a gate of the fifth transistor M5, a gate of the fifth transistor M5 is respectively connected to a drain of the seventh transistor M5, and a drain of the seventh transistor M5 are respectively connected to a drain of the sixth transistor M36 4 and a drain of the fifth transistor M5, The gate of the sixth transistor M6 is connected, the source of the seventh transistor M7 is connected to the upper end of the resistor Rs, and the lower end of the resistor Rs, the source of the fifth transistor M5, and the source of the second transistor M2 are connected to the ground GND, respectively.
The control circuit 200 includes: an eighth transistor M8, a ninth transistor M9, a tenth transistor M10, an eleventh transistor M11, a twelfth transistor M12, a thirteenth transistor M13, a fourteenth transistor M14, a fifteenth transistor M15, a sixteenth transistor M16, a seventeenth transistor M17, an eighteenth transistor M18, a nineteenth transistor M19 and a power transistor MP, wherein a source of the eighth transistor M8, a source of the twelfth transistor M12, a source of the fourteenth transistor M14 and a source of the power transistor MP are all connected with the input voltage terminal VDD, a source of the ninth transistor M9 is connected with a drain of the eighth transistor M8, a gate of the eighth transistor M8 is connected with a gate of the sixth transistor M6, a gate of the ninth transistor M9 is connected with a gate of the fourteenth transistor M14, a gate of the twelfth transistor M12, respectively, and a drain of the ninth transistor M9 is connected with a gate of the ninth transistor M9, A source of a tenth transistor M10, a gate of the tenth transistor M10 is connected to a drain of the tenth transistor M10 and a gate of the sixteenth transistor M16, a drain of the tenth transistor M10 is connected to a drain of the eleventh transistor M11, a gate of the eleventh transistor M11 is connected to a drain of the eleventh transistor M11 and a gate of the seventeenth transistor M17, a drain of the twelfth transistor M12 is connected to a drain of the thirteenth transistor M13 and a gate of the fifteenth transistor M15, a drain of the fifteenth transistor M15 is connected to a drain of the fourteenth transistor M14 and a gate of the power transistor MP, a drain of the power transistor MP, a source of the sixteenth transistor M16, a drain of the eighteenth transistor M18, a gate of the eighteenth transistor M18 and a gate of the nineteenth transistor M19 are all connected to the output voltage terminal VOUT, and a source of the eighteenth transistor M18 is connected to a gate of the thirteenth transistor M13, The drain of the nineteenth transistor M19 is connected, and the source of the thirteenth transistor M13, the source of the eleventh transistor M11, the source of the seventeenth transistor M17, and the source of the nineteenth transistor M19 are all connected to the ground GND. The first transistor M1, the third transistor M3, the fourth transistor M4 and the sixth transistor M6 are all PMOS transistors, and the second transistor M2, the fifth transistor M5 and the seventh transistor M7 are all NMOS transistors. The eighth transistor M8, the ninth transistor M9, the tenth transistor M10, the twelfth transistor M12, the fourteenth transistor M14, the sixteenth transistor M16 and the power transistor MP are all PMOS transistors, and the eleventh transistor M11, the thirteenth transistor M13, the fifteenth transistor M15, the seventeenth transistor M17, the eighteenth transistor M18 and the nineteenth transistor M19 are all NMOS transistors.
In the bias circuit 100, the first transistor M1, the second transistor M2, and the third transistor M3 constitute a start-up circuit, which can drive the circuit to get rid of a degenerated bias point when the input voltage terminal VDD is powered on, so as to ensure the start-up of the whole bias circuit 100, and after the bias circuit 100 is started, the third transistor M3 is kept off. Before the input voltage terminal VDD is not energized, all the transistors are in an off state, after the input voltage terminal VDD is energized, the gate-source voltage of the third transistor M3 increases, the third transistor M3 starts to conduct as a start-up transistor, the gate of the second transistor M2 is directly connected to the input voltage terminal VDD, the second transistor M2 also starts to conduct, the drain of the third transistor M3 is connected to the gate of the fifth transistor M5, the fifth transistor M5, the fourth transistor M4, the seventh transistor M7, and the sixth transistor M6 start to conduct, the fourth transistor M4 and the sixth transistor M6 form a current mirror, the fifth transistor M5 and the seventh transistor M7 form a current mirror, the current flowing through the sixth transistor M6 and the seventh transistor M7 is related to the parameters of the transistors themselves, the resistance Rs, and is irrelevant to the input voltage terminal VDD, and the currents generated by the sixth transistor M6 and the seventh transistor M7 provide the reference voltage to the control circuit 200, at the same time, the gate voltage of the first transistor M1 begins to decrease, the current flowing through the first transistor M1 increases, the drain voltage of the first transistor M1 is pulled high, the gate voltage of the third transistor M3 increases, and the current of the third transistor M3 decreases until it is turned off.
In the control circuit 200, as shown in fig. 1, for convenience of description, a node a is disposed between the source of the eighteenth transistor M18 and the drain of the nineteenth transistor M19, and a node B is disposed between the drain of the fourteenth transistor M14 and the drain of the fifteenth transistor M15.
When the voltage of the output voltage terminal VOUT increases, the voltage of the node a increases, the gate voltage of the thirteenth transistor M13 increases, the current flowing through the thirteenth transistor M13 increases, the drain voltage of the thirteenth transistor M13 is pulled down, the current flowing through the twelfth transistor M12 is not changed, the gate voltage of the fifteenth transistor M15 decreases, the current flowing through the fifteenth transistor M15 decreases, the current flowing through the fourteenth transistor M14 remains unchanged, the voltage of the node B is pulled up, the gate voltage of the power tube MP increases, the current flowing through the power tube MP decreases, and the voltage of the output voltage terminal VOUT is pulled down to return to a normal state. When the voltage of the output voltage terminal VOUT increases rapidly, the current flowing through the sixteenth transistor M16 increases, the current flowing through the seventeenth transistor M17 remains constant, the current flowing through the fifteenth transistor M15 decreases more rapidly, the voltage at the node B is pulled up rapidly, the gate voltage of the power transistor MP increases rapidly, the current flowing through the power transistor MP decreases, and the voltage at the output voltage terminal VOUT is pulled down rapidly to return to a normal state.
When the voltage of the output voltage terminal VOUT decreases, the voltage of the node a decreases, the gate voltage of the thirteenth transistor M13 increases, the current flowing through the thirteenth transistor M13 decreases, the drain voltage of the thirteenth transistor M13 is pulled up, the current flowing through the twelfth transistor M12 does not change, the gate voltage of the fifteenth transistor M15 increases, the current flowing through the fifteenth transistor M15 increases, the current flowing through the fourteenth transistor M14 remains unchanged, the voltage of the node B is pulled down, the gate voltage of the power tube MP decreases, the current flowing through the power tube MP increases, and the voltage of the pulled-up voltage terminal VOUT returns to a normal state; when the voltage of the output voltage terminal VOUT decreases rapidly, the current flowing through the sixteenth transistor M16 decreases, the current flowing through the seventeenth transistor M17 remains constant, the current flowing through the fifteenth transistor M15 increases rapidly, the voltage at the node B is pulled down, the voltage at the gate of the power transistor MP decreases, the current flowing through the power transistor MP increases, and the voltage at the output voltage terminal VOUT is pulled up to return to a normal state.
In the embodiment, the fourteenth transistor M14, the fifteenth transistor M15 and the power transistor MP form a voltage flip follower structure, and the bias circuit 100 is utilized to improve the transient response capability of the whole circuit.
The LDO circuit created by the present invention was quantitatively analyzed as follows:
the formula notation explains: voutExpressed as the voltage, mu, of the output voltage terminal VOUTnIs the mobility of electrons, CoxIs the gate capacitance per unit area. W is the conduction channel width, L is the conduction channel length, RsExpressed as the resistance value of the resistor Rs, VGSiDenoted as gate-source voltage, V, of the ith transistorTHExpressed as the threshold voltage of the transistor, IiExpressed as the current through the ith transistor, (W/L)iDenoted as transistor parameter of the ith transistor, KiDenoted as transistor parameter of the ith transistor, Ki＝μpCox(W/L)iThe subscript i denotes the reference number of the transistor, for example, when i is 4, it is denoted as a fourth transistor M4.
1. The bias circuit 100 is analyzed:
the circuit composed of the fourth transistor M4, the fifth transistor M5, the sixth transistor M6, and the seventh transistor M7 may generate a bias current regardless of the input voltage terminal VDD. The fourth transistor M4 and the sixth transistor M6 form a current mirror, and the fifth transistor M5 and the seventh transistor M7 form a current mirror.
Assume that the current flowing through the fourth transistor M4 and the fifth transistor M5 is I4The current flowing through the sixth transistor M6 and the seventh transistor M7 is IrefThen, one can write:
VGs5＝VGs5+IrefRSor
Figure BDA0002281036340000061
Neglecting the body effect, will
Figure BDA0002281036340000062
It is thus possible to obtain:
Figure BDA0002281036340000071
as can be seen from equation (1), the current I flowing through the sixth transistor M6 and the seventh transistor M7refIndependent of the input voltage terminal VDD voltage, and only dependent on process and temperature parameters, the current flowing from the bias circuit 100 remains constant.
As can be seen from fig. 1, the sixth transistor M6 and the eighth transistor M8 form a current mirror structure, which provides a bias current, and the current flowing through the sixth transistor M6 and the eighth transistor M8 are constant, and the relationship between them is:
2. the control circuit 200 is analyzed.
Representing the voltage of node A as electricityPressure VfbThe voltage of the output voltage terminal VOUT is expressed as a voltage Vout。
Voltage V of node afbIs V along with the output voltage terminal VOUToutSynchronously changing. As can be seen from fig. 1, the eighteenth transistor M18 is diode-connected and therefore in the saturation region, and the nineteenth transistor M19 is in the triode region, so that:
Figure BDA0002281036340000073
Figure BDA0002281036340000074
I18＝I19(5)，
the combined type (3) and (5) can obtain:
VGS19＝Vout(7)，
VDS19＝Vfb(8)，
VGS18＝Vout-Vfb(9)，
the following formulas (4), (6), (7), (8) and (9) can be obtained:
Figure BDA0002281036340000076
the derivation of equation (10) can be:
Figure BDA0002281036340000077
as can be seen from equation (11), the derivative between the voltage at the node a and the voltage at the output voltage terminal VOUT is greater than zero, and therefore, there is a direct proportional relationship therebetween. The voltage at node a increases with increasing output. The current flowing through the thirteenth transistor M13 is:
Figure BDA0002281036340000081
VGS13＝Vfb(13)
the united type (12) and (13) can obtain:
Figure BDA0002281036340000082
as can be seen from equation (14), the current flowing through the thirteenth transistor M13 increases as the voltage of the node a increases. When the currents flowing through the twelfth transistor M12 and the thirteenth transistor M13 are equal, then:
I12＝I13(15)，
the twelfth transistor M12 and the fourteenth transistor M14 form a current mirror structure, and the current flowing through the twelfth transistor M12 and the fourteenth transistor M14 is related to:
the fourteenth transistor M14 is diode-connected, the current flowing through the fifteenth transistor M15 is equal to the current flowing through the fourteenth transistor M14, and then:
I15＝I14(17)，
as can be seen from the setting of the process device parameters, the currents flowing through the fifteenth transistor M15 and the seventeenth transistor M17 are set in a certain proportion
Figure BDA0002281036340000084
Then:
Figure BDA0002281036340000085
the ninth transistor M9, the tenth transistor M10, and the eleventh transistor M11 are all diode-connected, so that the currents flowing therebetween are equal and constant, and then:
I11＝I10＝I9＝I8(19)，
the eleventh transistor M11 and the seventeenth transistor M17 form a current mirror structure, and the current flowing through the eleventh transistor M11 and the seventeenth transistor M17 is in the following relationship:
Figure BDA0002281036340000086
the united type (2), (18), (19) and (20) can obtain:
Figure BDA0002281036340000087
the vertical type (14), (15), (16), (17) can obtain:
Figure BDA0002281036340000088
the output voltage terminal VOUT is connected to the source of the sixteenth transistor M16, and the voltage V of the output voltage terminal VOUT can be known by considering the channel modulation effectoutAnd a current I flowing through a sixteenth transistor M1616The relationship is:
VDS16＝Vout-Vo17(24)。
in the current expression of the PMOS tube, the negative sign inside does not represent the magnitude but represents the direction, the expression (23) represents that the current direction flows from the drain to the source, the current direction is specified to flow from the source to the drain, and the source leakage current expression of the PMOS tube can be obtained by considering the channel modulation effect
Figure BDA0002281036340000092
When the voltage V of the output voltage terminal VOUToutChange is made, and the change amount is set as DeltaVoutThe drain-source voltage of the sixteenth transistor M16 and the voltage V of the output voltage terminal VOUToutThe variation of (c) is as follows:
ΔVDS16＝ΔVout-VD17(26)，
the total current flowing through the seventeenth transistor M17 is not changed, so when the current flowing through the sixteenth transistor M16 is changed, the current flowing through the fifteenth transistor M15 is changed accordingly, that is:
ΔI16＝-ΔI15(27)，
from the equations (25), (26) and (27), the current flowing through the fifteenth transistor M15 and the voltage V of the output voltage terminal VOUToutThe following relationships exist:
Figure BDA0002281036340000093
from the formula (28), Δ VoutWhen negative, Δ I15Is positive, i.e. the voltage V of the output voltage terminal VOUToutWhen decreasing, the current flowing through the fifteenth transistor M15 increases, VoutWhen increasing, the current flowing through the fifteenth transistor M15 decreases. The current flowing through the fifteenth transistor M15 decreases while the current flowing through the fourteenth transistor M14 remains unchanged, pulling the voltage at the node B high, the gate voltage through the power transistor MP increases.
The current flowing through the power tube MP is:
Figure BDA0002281036340000094
the gate voltage of the power transistor MP is increased and the gate-source voltage is decreased, and as can be seen from equation (29), the current flowing through the power transistor MP is decreased, so that V is decreasedoutPulling down to restore the normal state.
The output V can be obtained by the vertical combination of (10), (21) and (22)outExpression (2)
Figure BDA0002281036340000095
In summary, output VoutWhen the voltage rises, the voltage at the node a rises, and the gate voltage of the thirteenth transistor M13 also rises, as shown by the equation (11), and flows through the gate of the thirteenth transistor M13The current flowing through the thirteenth transistor M13 increases accordingly, and the twelfth transistor M12 and the ninth transistor M9 form a current mirror structure, so that the current flowing through the twelfth transistor M12 keeps unchanged, the gate voltage of the fifteenth transistor M15 is pulled down, as shown by the formula (28), the current flowing through the fifteenth transistor M15 decreases faster, as shown by the formula (16), the current flowing through the fourteenth transistor M14 keeps unchanged, the gate voltage of the power transistor MP is pulled up, as shown by the formula (28), the current flowing through the power transistor MP decreases accordingly, and V is reducedoutPulling down and recovering to a normal state.
Output VoutWhen the voltage at the node a decreases, the gate voltage of the thirteenth transistor M13 also decreases, as shown in equation (14), the current flowing through the thirteenth transistor M13 decreases, the twelfth transistor M12 and the ninth transistor M9 form a current mirror structure, so that the current flowing through the twelfth transistor M12 remains unchanged, the gate voltage of the fifteenth transistor M15 is pulled up, as shown in equation (28), the current flowing through the fifteenth transistor M15 increases more rapidly, as shown in equation (16), the current flowing through the fourteenth transistor M14 remains unchanged, the gate voltage of the power transistor MP is pulled down, and as shown in equation (28), the current flowing through the power transistor MP increases, and V is increasedoutThe pull-up is restored to the normal state.
As can be known from simulation experiments, compared with the LDO circuit in the prior art, the technical scheme has good transient response capability.
While the preferred embodiments of the present invention have been described in detail, it will be understood by those skilled in the art that the invention is not limited to the details of the embodiments shown, but is capable of various modifications and substitutions without departing from the spirit of the invention.

Claims (3)

1. A push-pull LDO circuit based on a voltage flip-follower structure, comprising: input voltage end, output voltage end and earthing terminal, its characterized in that still includes:
a bias circuit, comprising: a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, and a resistor, wherein a source of the first transistor, a gate of the second transistor, a source of the third transistor, a source of the fourth transistor, and a source of the sixth transistor are all connected to the input voltage terminal, a gate of the first transistor is connected to a gate of the fourth transistor and a gate of the sixth transistor, respectively, a drain of the first transistor is connected to a gate of the third transistor and a drain of the second transistor, a drain of the third transistor is connected to a drain of the fourth transistor, a drain of the fifth transistor and a gate of the fifth transistor, a gate of the fifth transistor is connected to a gate of the seventh transistor, and a drain of the seventh transistor is connected to a drain of the sixth transistor and a gate of the sixth transistor, respectively, the source electrode of the seventh transistor is connected with the upper end of the resistor, and the lower end of the resistor, the source electrode of the fifth transistor and the source electrode of the second transistor are respectively connected with the ground terminal;
a control circuit, comprising: the power supply circuit comprises an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor, a twelfth transistor, a thirteenth transistor, a fourteenth transistor, a fifteenth transistor, a sixteenth transistor, a seventeenth transistor, an eighteenth transistor, a nineteenth transistor and a power tube, wherein a source of the eighth transistor, a source of the twelfth transistor, a source of the fourteenth transistor and a source of the power tube are all connected with an input voltage end, a source of the ninth transistor is connected with a drain of the eighth transistor, a gate of the eighth transistor is connected with a gate of the sixth transistor, a gate of the ninth transistor is respectively connected with a gate of the fourteenth transistor and a gate of the twelfth transistor, a drain of the ninth transistor is respectively connected with a gate of the ninth transistor and a source of the tenth transistor, and a gate of the tenth transistor is respectively connected with a drain of the tenth transistor, A gate of the sixteenth transistor is connected to a drain of the tenth transistor, a gate of the eleventh transistor is connected to a drain of the eleventh transistor and a gate of the seventeenth transistor, a drain of the twelfth transistor is connected to a drain of the thirteenth transistor and a gate of the fifteenth transistor, a drain of the fifteenth transistor is connected to a drain of the fourteenth transistor and a gate of the power transistor, a drain of the power transistor, a source of the sixteenth transistor, a drain of the eighteenth transistor, a gate of the eighteenth transistor and a gate of the nineteenth transistor are all connected to the output voltage terminal, a source of the eighteenth transistor is connected to a gate of the thirteenth transistor and a drain of the nineteenth transistor, a source of the thirteenth transistor, a source of the eleventh transistor, a source of the seventeenth transistor, a drain of the seventeenth transistor, a gate of the fifteenth transistor, a drain of the power transistor, a, And the sources of the nineteenth transistor are all connected with the ground terminal.
2. The push-pull LDO circuit based on voltage flip-follower architecture as claimed in claim 1, wherein said first, third, fourth and sixth transistors are all PMOS transistors and said second, fifth and seventh transistors are all NMOS transistors.
3. The push-pull LDO circuit based on the voltage flip-follower structure of claim 1, wherein: the eighth transistor, the ninth transistor, the tenth transistor, the twelfth transistor, the fourteenth transistor, the sixteenth transistor and the power tube are all PMOS transistors, and the eleventh transistor, the thirteenth transistor, the fifteenth transistor, the seventeenth transistor, the eighteenth transistor and the nineteenth transistor are all NMOS transistors.
CN201911141377.8A 2019-11-20 2019-11-20 Push-pull type LDO circuit based on voltage flip follower structure Pending CN110806779A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI804237B (en) * 2022-03-16 2023-06-01 友達光電股份有限公司 Reference voltage generating circuit

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20150214903A1 (en) * 2014-01-27 2015-07-30 Montage Technology (Shanghai) Co., Ltd. Voltage Regulator and Method of Regulating Voltage
US20160118939A1 (en) * 2014-10-23 2016-04-28 Beken Corporation Amplifier and amplification method
CN107479612A (en) * 2017-10-16 2017-12-15 佛山科学技术学院 A kind of quick response LDO circuit
WO2018176968A1 (en) * 2017-04-01 2018-10-04 唯捷创芯(天津)电子技术股份有限公司 Envelope tracking power supply having series-parallel structure, chip, and communication terminal
CN108762363A (en) * 2018-06-25 2018-11-06 电子科技大学 A kind of LDO circuit of push-pull output stage
CN108803764A (en) * 2018-06-25 2018-11-13 电子科技大学 A kind of LDO circuit of fast transient response
CN109917847A (en) * 2019-03-26 2019-06-21 佛山市顺德区德雅军民融合创新研究院 Voltage stabilizing circuit and voltage stabilizing chip
CN210835777U (en) * 2019-11-20 2020-06-23 佛山科学技术学院 Push-pull type LDO circuit based on voltage flip follower structure

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20150214903A1 (en) * 2014-01-27 2015-07-30 Montage Technology (Shanghai) Co., Ltd. Voltage Regulator and Method of Regulating Voltage
US20160118939A1 (en) * 2014-10-23 2016-04-28 Beken Corporation Amplifier and amplification method
WO2018176968A1 (en) * 2017-04-01 2018-10-04 唯捷创芯(天津)电子技术股份有限公司 Envelope tracking power supply having series-parallel structure, chip, and communication terminal
CN107479612A (en) * 2017-10-16 2017-12-15 佛山科学技术学院 A kind of quick response LDO circuit
CN108762363A (en) * 2018-06-25 2018-11-06 电子科技大学 A kind of LDO circuit of push-pull output stage
CN108803764A (en) * 2018-06-25 2018-11-13 电子科技大学 A kind of LDO circuit of fast transient response
CN109917847A (en) * 2019-03-26 2019-06-21 佛山市顺德区德雅军民融合创新研究院 Voltage stabilizing circuit and voltage stabilizing chip
CN210835777U (en) * 2019-11-20 2020-06-23 佛山科学技术学院 Push-pull type LDO circuit based on voltage flip follower structure

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI804237B (en) * 2022-03-16 2023-06-01 友達光電股份有限公司 Reference voltage generating circuit

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