CN102681580B - Current source circuit - Google Patents

Abstract

The invention embodiment provides a current source circuit. The current source circuit comprises two PMOS (P-channel metal oxide semiconductor) pipes, three NMOS (N-channel Mental-oxide-semiconductor) pipes as well as a resistor; compared with the traditional current source circuit, and the current source circuit increases one NMOS pipe, namely a design parameter; and the temperature coefficient of the current source circuit is lower, and the current source circuit can be applied to application occasions with higher temperature coefficient requirements of the current source circuit, such as family intelligent systems.

Description

A kind of current source circuit

Technical field

The present invention relates to technical field of integrated circuits, be specifically related to a kind of current source circuit.

Background technology

Current source circuit is one of very important basic circuit in integrated circuit (IC) system, and the normal work that it is other modules in chip provides necessary bias current, and therefore its performance has affected the overall performance of chip to a great extent.As shown in Figure 1, be the circuit structure diagram of traditional current source circuit, this current source circuit comprises four metal-oxide-semiconductor M1, M2, M3, M4 and a resistance; Wherein metal-oxide-semiconductor M3 and M4 form common-source common-gate current mirror structure, so, the source-drain current proportion relation of the source-drain current of M3 and M4.Current source circuit can be exported comparatively stable reference current conventionally; But due to the impact of environment temperature or chip working time, chip temperature around can change to some extent, cause the reference current of current source circuit output to change to some extent.The reference current variation with temperature coefficient of current source circuit output is commonly referred to the temperature coefficient of current source circuit.In prior art, the temperature coefficient of the current source current of most application is all larger, as is 1000ppm/ DEG C of left and right, and the temperature coefficient of current source circuit cannot reach less scope.This just causes a lot of current source circuits in some has the circuit of particular requirement, to use, for example, in the application scenarios such as household intelligent system, conventionally require the temperature coefficient of current source circuit as far as possible low, but existing most of current source circuits all cannot meet this requirement.

Summary of the invention

In view of this, the object of the present invention is to provide the current source circuit that a kind of temperature coefficient is lower, to meet the requirement of different application occasion to current source circuit low-temperature coefficient.

For achieving the above object, the embodiment of the present invention provides a kind of current source circuit, comprises two PMOS pipes, three NMOS pipes and a resistance, wherein,

The source electrode of the one PMOS pipe is connected to power supply, and grid is connected with drain electrode;

The source electrode of the 2nd PMOS pipe is connected to described power supply, and grid is connected with the grid of a described PMOS pipe;

The source ground of the one NMOS pipe, drain electrode is connected with the drain electrode of a described PMOS pipe;

The source electrode of the 2nd NMOS pipe is connected with the grid of a described NMOS pipe, and grid is connected with drain electrode, and is connected with the drain electrode of described the 2nd PMOS pipe;

The source electrode of the 3rd NMOS pipe is by the first resistance eutral grounding, and grid is connected with the grid of described the 2nd NMOS pipe, and drain electrode is connected with the grid of a described NMOS pipe;

A described PMOS pipe, the 2nd PMOS pipe, a NMOS pipe, the 2nd NMOS pipe and described the 3rd NMOS pipe are all operated in saturation region.

Preferably, the channel width-over-length ratio of a described PMOS pipe is identical with the channel width-over-length ratio of described the 2nd PMOS pipe.

Preferably, the resistance value R of described the first resistance meets:

$R=\frac{V_{\mathrm{TH}}}{I_{\mathrm{DS}}}\frac{k_{{\mathrm{\μ}}_n}+2k_{V_{\mathrm{TH}}}}{k_{{\mathrm{\μ}}_n}}-2\frac{1}{k_{{\mathrm{\μ}}_n}}\frac{\mathrm{dR}}{\mathrm{dT}}$

Wherein, $k_{{\mathrm{\μ}}_n}=\frac{1}{{\mathrm{\μ}}_n}\·\frac{d{\mathrm{\μ}}_n}{\mathrm{dT}},k_{V_{\mathrm{TH}}}=\frac{1}{V_{\mathrm{TH}}}\·\frac{{\mathrm{dV}}_{\mathrm{TH}}}{\mathrm{dT}},I_{\mathrm{DS}}={\mathrm{\μ}}_n{C}_{\mathrm{ox}}\left(\frac{W}{L}\right){(V_{\mathrm{GS}}-V_{\mathrm{TH}})}^2;$

Wherein, V _tHfor the threshold voltage of described the 2nd NMOS pipe, I _dSfor the drain-source current of described the 2nd NMOS pipe, _{μ n}for the mobility of described the 2nd NMOS pipe, C _oxfor the gate oxide electric capacity of the unit area of described the 2nd NMOS pipe, for the channel width-over-length ratio of described the 2nd NMOS pipe, V _gSpoor for the gate source voltage of described the 2nd NMOS pipe, T is kelvin degree.

Preferably, described current source circuit also comprises the first start-up circuit, and described the first start-up circuit comprises a PMOS pipe and two NMOS pipes, wherein,

The source electrode of the 3rd PMOS pipe is connected to described power supply, and grid is connected with the grid of a described NMOS pipe;

The source ground of the 4th NMOS pipe, grid is connected with the grid of described the 3rd PMOS pipe, and drain electrode is connected with the source electrode of described the 3rd PMOS pipe;

The source ground of the 5th NMOS pipe, grid is connected with the drain electrode of described the 3rd PMOS pipe, and drain electrode is connected with the grid of a described PMOS pipe.

Preferably, the channel width-over-length ratio of described the 3rd PMOS pipe is greater than the channel width-over-length ratio of described the 4th NMOS pipe.

Preferably, described current source circuit also comprises the second start-up circuit, and described the second start-up circuit comprises a PMOS pipe, a NMOS pipe and a resistance, wherein,

The source electrode of the 4th PMOS pipe is connected to described power supply, and drain electrode is connected with the drain electrode of described the 2nd PMOS pipe, and grid is by the second resistance eutral grounding;

The source ground of the 6th NMOS pipe, grid is connected and passes through described the second resistance eutral grounding with drain electrode.

The embodiment of the present invention provides a kind of current source circuit, comprises two PMOS pipes, three NMOS pipes and a resistance; Compared with traditional current source circuit, this current source circuit has increased a NMOS pipe, increase a design parameter, made the temperature coefficient of current source circuit lower, can be applied to the application scenario that household intelligent system etc. is had relatively high expectations to the temperature coefficient of current source circuit.

Brief description of the drawings

In order to be illustrated more clearly in the embodiment of the present invention or technical scheme of the prior art, to the accompanying drawing of required use in embodiment or description of the Prior Art be briefly described below, apparently, accompanying drawing in the following describes is some embodiments of the present invention, for those of ordinary skill in the art, do not paying under the prerequisite of creative work, can also obtain according to these accompanying drawings other accompanying drawing.

Fig. 1 is the circuit structure diagram of current source circuit traditional in prior art;

Fig. 2 is the circuit structure diagram of the current source circuit of the embodiment of the present invention one;

Fig. 3 is the output reference electric current variation with temperature curve map of the current source circuit of the embodiment of the present invention two;

Fig. 4 is the circuit structure diagram of the current source circuit of the embodiment of the present invention three;

Fig. 5 is the circuit structure diagram of the current source circuit of the embodiment of the present invention four.

Embodiment

For making object, technical scheme and the advantage of the embodiment of the present invention clearer, below in conjunction with the accompanying drawing in the embodiment of the present invention, technical scheme in the embodiment of the present invention is clearly and completely described, obviously, described embodiment is the present invention's part embodiment, instead of whole embodiment.Based on the embodiment in the present invention, those of ordinary skill in the art, not making the every other embodiment obtaining under creative work prerequisite, belong to the scope of protection of the invention.

In prior art, for traditional current source circuit, its temperature coefficient is generally higher, and for example, 1000ppm/ DEG C of left and right, therefore, these traditional current source circuits cannot meet the requirement of some application scenario to current source circuit low-temperature coefficient.Current source circuit as shown in Figure 1, metal-oxide-semiconductor M3 and the channel width-over-length ratio proportion relation of M4: the 1:m of formation common-source common-gate current mirror structure, can be obtained by Kirchhoff's second law, and the grid voltage of metal-oxide-semiconductor M1 and M2 meets following formula:

mI _DSR+V _GS2=V _GS1…………………………………………………………（1）

Wherein, I _dSfor the source-drain current of metal-oxide-semiconductor M2, flow through the electric current of resistance R; In the time that the each metal-oxide-semiconductor in Fig. 1 is operated in saturation region, according to the source-drain current formula of saturation region, the I in (1) formula _dSmeet:

$I_{\mathrm{DS}}={\mathrm{\μ}}_n{C}_{\mathrm{ox}}\left(\frac{W}{L}\right){(V_{\mathrm{GS}}-V_{\mathrm{TH}})}^2...\left(2\right)$

Wherein, μ _nfor the mobility of NMOS pipe, C _oxthe gate oxide electric capacity of the unit area of NMOS pipe, for the channel width-over-length ratio of NMOS pipe, V _gSfor NMOS pipe gate source voltage poor, V _tHfor the threshold voltage of NMOS pipe.

By (2) formula substitution (1) formula, and to (1) formula two ends differentiate, can obtain Jie's temperature coefficient relational expression of the reference current of the current source circuit output shown in Fig. 1:

$\frac{1}{I}\frac{\mathrm{dI}}{\mathrm{dT}}=-\frac{1}{{\mathrm{\μ}}_n}\frac{d{\mathrm{\μ}}_n}{\mathrm{dT}}-\frac{2}{R}\frac{\mathrm{dR}}{\mathrm{dT}}...\left(3\right)$

Wherein, I is the reference current of output, μ _nfor the mobility of NMOS pipe, R is the resistance value of resistance in circuit.

Visible, the temperature coefficient of the current source circuit shown in Fig. 1 is an amount relevant with the mobility of metal-oxide-semiconductor with the resistance value R of resistance, and wherein the mobility of metal-oxide-semiconductor is determined, so the temperature coefficient of current source circuit is mainly determined by the resistance value R in circuit.And resistance value R in current source circuit is determined by the design parameter of design technology and foundries conventionally; And these parameters can only change within the specific limits, therefore, under normal circumstances, the temperature coefficient of the current source circuit shown in Fig. 1 is larger, for example, be greater than 1000ppm/ DEG C.This makes traditional current source circuit cannot meet the requirement to current source circuit low-temperature coefficient, more cannot be applied in the occasion that low-temperature coefficient is had relatively high expectations.

On the basis of the circuit structure of the conventional current source circuit shown in Fig. 1, inventor finds through analysing in depth, by increase a NMOS pipe on the basis of this circuit structure, increase a design parameter, can obtain a current source circuit that temperature coefficient is lower; This current source circuit can meet the requirement of current source circuit low-temperature coefficient, can be applied to the application scenario that the low-temperature coefficient of current source circuit is had relatively high expectations.

The invention provides a kind of current source circuit, this current source circuit comprises two PMOS pipes, three NMOS pipes and a resistance; Compared with conventional current source circuit, this current source circuit has increased a NMOS pipe, increase a design parameter, made the temperature coefficient of current source circuit lower, can be applied to the application scenario that household intelligent system etc. is had relatively high expectations to the low-temperature coefficient of current source circuit.

Embodiment mono-

The embodiment of the present invention provides a kind of current source circuit, and as shown in Figure 2, this current source circuit comprises two PMOS pipes, three NMOS pipes and a resistance to its circuit structure diagram, wherein,

The one PMOS pipe M1, source electrode is connected to power supply V _dd, grid is connected with drain electrode;

The 2nd PMOS pipe M2, source electrode is connected to power supply V _dd, grid is connected with the grid of a PMOS pipe M1;

PMOS pipe M1 and M2 connect into common-source common-gate current mirror form, have determined the electric current multiple relation of M1 and M2; In design process, the channel length that PMOS can be managed to M1 and M2 is designed to be greater than the minimum channel length of 3 times, to reduce the impact of channel-length modulation on current mirror.

It should be noted that, the grid of M1 and M2 can also be connected other PMOS pipe or current output circuits;

The one NMOS pipe M3, source ground, drain electrode is connected with the drain electrode of a PMOS pipe M1;

The 2nd NMOS pipe M4, source electrode is connected with the grid of a NMOS pipe M3, and drain electrode is connected with grid, and is connected with the drain electrode of the 2nd PMOS pipe M2;

The 3rd NMOS pipe M5, source electrode is by the first resistance eutral grounding, and drain electrode is connected with the grid of a NMOS pipe M3 and the source electrode of the 2nd NMOS pipe M4, and grid is connected with the grid of the 2nd NMOS pipe M4;

The one PMOS pipe M1, the 2nd PMOS pipe M2, a NMOS pipe M3, the 2nd NMOS pipe M4 and the 3rd NMOS pipe M5 are all operated in saturation region.

It should be noted that, the channel width-over-length ratio of the PMOS pipe M1 in the embodiment of the present invention can be identical with the channel width-over-length ratio of the 2nd PMOS pipe M2; Now, a PMOS pipe M1 and the 2nd PMOS pipe M2 form desirable common-source common-gate current mirror structure, and the source-drain current of M1 and M2 equates.

In embodiments of the present invention, supply voltage V _ddafter connection, voltage source circuit is as shown in Figure 2 operated in the quiescent point of electric current non-zero, known according to Kirchhoff's second law, and the magnitude of voltage of node 201 meets:

I _DSR+V _GS5＝V _GS3+V _GS4……………………………………………………（4）

Wherein, I _dSbe the source-drain current of the 2nd NMOS pipe M4, flow through the electric current of the first resistance, R is the resistance value of the first resistance, V _gS3, V _gS4and V _gS5be respectively the voltage between grid and the source electrode of a NMOS pipe M3, the 2nd NMOS pipe M4 and the 3rd NMOS pipe M5.

Due in the time that this current source circuit is operated in the quiescent point of electric current non-zero, the one PMOS pipe M1, the 2nd PMOS pipe M2, a NMOS pipe M3, the 2nd NMOS pipe M4 and the 3rd NMOS pipe M5 all can be operated in saturation region, so according to the source-drain current formula of saturation region metal-oxide-semiconductor, the source-drain current of the 2nd NMOS pipe M4 can be expressed as:

$I_{\mathrm{DS}}={\mathrm{\μ}}_n{C}_{\mathrm{ox}}\left(\frac{W}{L}\right){(V_{\mathrm{GS}}-V_{\mathrm{TH}})}^2...\left(5\right)$

Wherein, μ _nfor the mobility of NMOS pipe, C _oxthe gate oxide electric capacity of the unit area of NMOS pipe, for the channel width-over-length ratio of NMOS pipe, V _gSfor the gate source voltage of NMOS pipe poor, V _tHfor the threshold voltage of NMOS pipe.

By (5) formula substitution (4) formula, and to (4) formula two ends differentiate, can obtain the single order temperature coefficient of reference current:

$k_{I_{\mathrm{DS}}}=\frac{V_{\mathrm{TH}}(k_{{\mathrm{\μ}}_n}+2k_{V_{\mathrm{TH}}})-I_{\mathrm{DS}}R(k_{{\mathrm{\μ}}_n}+2k_R)}{V_{\mathrm{TH}}+I_{\mathrm{DS}}R}...\left(6\right)$

Wherein, $k_{I_{\mathrm{DS}}}=\frac{1}{{\mathrm{I\μ}}_{\mathrm{DS}}}\·\frac{d{I}_{\mathrm{DS}}}{\mathrm{dT}},k_{{\mathrm{\μ}}_n}=\frac{1}{{\mathrm{\μ}}_n}\·\frac{{\mathrm{d\μ}}_n}{\mathrm{dT}},k_R=\frac{1}{R}\·\frac{\mathrm{dR}}{\mathrm{dT}},k_{V_{\mathrm{TH}}}=\frac{1}{V_{\mathrm{TH}}}\·\frac{{\mathrm{dV}}_{\mathrm{TH}}}{\mathrm{dT}};$

So, as long as regulate the value on equation (6) right side, can adjust the size of temperature coefficient.In equation (3), temperature coefficient is mainly definite by the resistance value of the first resistance, and therefore temperature coefficient can only change within the specific limits, cannot reach lower numerical value; And in equation (6), temperature coefficient not only relevant with the resistance value of the first resistance, also with the relating to parameters such as channel width-over-length ratio and threshold voltage of metal-oxide-semiconductor, by adjusting the channel width-over-length ratio of metal-oxide-semiconductor and the resistance value of the first resistance, can make the temperature coefficient of this current source circuit reach a very little numerical value, realize low-temperature coefficient.

In this circuit structure, NMOS pipe M3, M4, M5 and the first resistance complete the temperature compensation function to current source circuit.Compared with prior art, the first resistance in the embodiment of the present invention not only can be determined the occurrence of electric current in current source circuit, can also work and realize the temperature compensation to current source circuit with metal-oxide-semiconductor one, therefore can be called compensating resistance.

It should be noted that, metal-oxide-semiconductor M1, M2, M3, M4 and M5 can be dissipative type metal-oxide-semiconductors, can be also enhancement mode metal-oxide-semiconductors.

In addition, the first resistance can be N trap resistance, can be also intrinsic resistance; Can be variable resistor, as rheochord, can be also the fixing resistance of resistance.

The embodiment of the present invention provides a kind of current source circuit, comprises two PMOS pipes, three NMOS pipes and a resistance.This current source circuit, on the circuit structure basis of conventional current source circuit, increases a NMOS pipe and then has increased a design parameter, makes the temperature coefficient of current source circuit can reach a less numerical value; Can realize low-temperature coefficient current source circuit by the channel width-over-length ratio of the resistance of adjusting resistance, metal-oxide-semiconductor and other parameters, this current source circuit can be applied to the application scenario that household intelligent system etc. is had relatively high expectations to the temperature coefficient of current source circuit.

Embodiment bis-

The first resistance and metal-oxide-semiconductor acting in conjunction in the current source circuit of the embodiment of the present invention one can realize low-temperature coefficient, in another embodiment of the present invention, by setting the resistance value of the first resistance, can make the temperature coefficient of current source circuit level off to zero, the circuit structure diagram of this current source circuit is identical with the circuit structure diagram in the embodiment of the present invention one, and its difference is only to meet fixing relation between the resistance value of the first resistance and the channel width-over-length ratio of metal-oxide-semiconductor.

In the embodiment of the present invention two, the resistance value R of the first resistance meets as shown in Figure 2:

$R=\frac{V_{\mathrm{TH}}}{I_{\mathrm{DS}}}\frac{k_{{\mathrm{\μ}}_n}+2k_{V_{\mathrm{TH}}}}{k_{{\mathrm{\μ}}_n}}-2\frac{1}{k_{{\mathrm{\μ}}_n}}\frac{\mathrm{dR}}{\mathrm{dT}}...\left(7\right)$

Wherein, $k_{{\mathrm{\μ}}_n}=\frac{1}{{\mathrm{\μ}}_n}\·\frac{d{\mathrm{\μ}}_n}{\mathrm{dT}},k_{V_{\mathrm{TH}}}=\frac{1}{V_{\mathrm{TH}}}\·\frac{{\mathrm{dV}}_{\mathrm{TH}}}{\mathrm{dT}},I_{\mathrm{DS}}={\mathrm{\μ}}_n{C}_{\mathrm{ox}}\left(\frac{W}{L}\right){(V_{\mathrm{GS}}-V_{\mathrm{TH}})}^2;$

Wherein, V _tHbe the threshold voltage of the 2nd NMOS pipe M4, I _dSbe the drain-source current of the 2nd NMOS pipe M4, μ _nbe the mobility of the 2nd NMOS pipe M4, C _oxbe the gate oxide electric capacity of the unit area of the 2nd NMOS pipe M4, be the channel width-over-length ratio of the 2nd NMOS pipe M4, V _gSthe gate source voltage that is the 2nd NMOS pipe M4 is poor, and T is kelvin degree.

Describe the relation between the resistance value R of the first resistance and the channel width-over-length ratio of metal-oxide-semiconductor in detail below by the derivation of equation:

Based on equation (6), make the temperature coefficient in equation (6) left side equal zero, can obtain equation (7).

When the resistance value R of the first resistance meets be, time, the temperature coefficient of this current source circuit is infinitely close to zero, in certain temperature range, and the reference current of this current source circuit variation with temperature and changing hardly.

It should be noted that, because the mobility of metal-oxide-semiconductor is only relevant with the type of metal-oxide-semiconductor, equate with the mobility of the 2nd NMOS pipe M4 so a NMOS pipe M3 and the 3rd NMOS manage the mobility of M5, therefore the C in equation (2) _oxalso can be the mobility of the first NMOS pipe M3 or the 3rd NMOS pipe M5.

In addition, the channel width-over-length ratio of NMOS pipe M3, M4 and M5 can be identical, can be not identical yet, and the source-drain current of the 2nd NMOS pipe M4 in equation (2) does not change with the isoparametric variation of size of M1, M2.

It should be noted that, in the embodiment of the present invention, the physical size of a PMOS pipe M1 and the 2nd PMOS pipe M2 can be identical; And the channel width-over-length ratio of a PMOS pipe M1 and the 2nd PMOS pipe M2 can be identical.

When the one PMOS pipe M1, the 2nd PMOS pipe M2, a NMOS pipe M3, the 2nd NMOS pipe M4 and the 3rd NMOS pipe M5 are all operated in saturation region, according to the Sa formula equation of saturation region, the source-drain current I of a PMOS pipe M1 ₁source-drain current I with the 2nd PMOS pipe M2 ₂meet following relation:

$\frac{I_1}{I_2}=\frac{{(W/L)}_1}{{(W/L)}_2}...\left(8\right)$

Wherein, (W/L) ₁be the channel width-over-length ratio of a PMOS pipe M1, (W/L) ₂be the channel width-over-length ratio of the 2nd PMOS pipe M2,

Can be found out by equation (8), if the wide long proportion relation of raceway groove of a PMOS pipe M1 and the 2nd PMOS pipe M2, a PMOS pipe M1 also becomes identical proportionate relationship with the source-drain current of the 2nd PMOS pipe M2; If a PMOS pipe M1 is identical with the channel width-over-length ratio of the 2nd PMOS pipe M2, a PMOS pipe M1 is identical with the source-drain current of the 2nd PMOS pipe M2, so, just this current source circuit is closer to the current source circuit of perfect condition.

It should be noted that, the channel width-over-length ratio of metal-oxide-semiconductor can be certain fixed value, cannot be excessive, also cannot be too small, and this value can be determined according to the concrete technology condition of foundries.

Figure 3 shows that the reference current variation with temperature curve map of the embodiment of the present invention two current source circuits, can find out, in-40 DEG C～120 DEG C temperature ranges, the rate of change of the reference current of the embodiment of the present invention two current source circuits is only 12ppm/ DEG C.Visible, the embodiment of the present invention two can utilize the mobility of NMOS pipe and the different temperature coefficients of threshold voltage to carry out temperature compensation, realizes the current source circuit that temperature coefficient is extremely low.

Current source circuit in above-described embodiment one and embodiment bis-can normally be operated in the quiescent point of electric current non-zero, and still, when the quiescent point that is zero at electric current, the current source circuit in above-described embodiment one and embodiment bis-can not normally be worked.For this reason, the embodiment of the present invention also provides a kind of start-up circuit, when the quiescent point as zero, to start above-mentioned current source circuit at electric current, current source circuit can normally be worked.

Embodiment tri-

The embodiment of the present invention three provides a kind of current source circuit, as shown in Figure 4, for the circuit structure diagram of this current source circuit, as seen from the figure, the circuit structure of this current source circuit, part is identical with the circuit structure (being Fig. 2) of the current source circuit in above-described embodiment one and embodiment bis-, this part is called to the main body circuit of current source circuit; Different is, the embodiment of the present invention three is on the basis of the circuit structure of above-mentioned current source circuit, a kind of start-up circuit is also provided, taking the main body circuit at current source circuit in electric current the main body circuit of starting current source circuit when the quiescent point as zero, even if the quiescent point current source circuit that to make at electric current be zero also can be worked normally.

Particularly, the first start-up circuit 402 that the embodiment of the present invention three provides comprises a PMOS pipe and two NMOS pipes, wherein,

The 3rd PMOS pipe M6, source electrode is connected to power supply V _dd, grid is connected with grid, the source electrode of the 2nd NMOS pipe M4 and the drain electrode of the 3rd NMOS pipe M5 of a NMOS pipe M3;

The 4th NMOS pipe M7, source ground, drain electrode is connected with the drain electrode of the 3rd PMOS pipe M6, and grid is connected with the grid of the 3rd PMOS pipe M6, and is connected with the drain electrode of the 3rd NMOS pipe M5 with the grid of a NMOS pipe M3 and the source electrode of the 2nd NMOS pipe M4;

The 5th NMOS pipe M8, source ground, drain electrode is connected with the grid of the 2nd PMOS pipe M2 with the grid of a PMOS pipe M1, and grid is connected with the drain electrode of the 4th NMOS pipe M7 with the drain electrode of the 3rd PMOS pipe M6.

Particularly, the 3rd PMOS pipe M6 and the 4th NMOS pipe M7 connect into the pattern of phase inverter, and the input end of phase inverter is connected to the drain electrode of the 3rd NMOS pipe M5, and the output terminal of phase inverter is connected to the grid of the 5th NMOS pipe M8.

Particularly, after supply voltage is connected, be zero quiescent point if the main body circuit 401 of current source circuit is operated in electric current, this start-up circuit 402 is worked.As shown in Figure 4, the main body circuit 401 of current source circuit is in electric current while being zero quiescent point, and a PMOS pipe M1 and the 2nd PMOS pipe M2 are all operated in cut-off region; The 2nd NMOS pipe M4 and the 3rd NMOS pipe M5 are also operated in cut-off region, so the level of node 404 is supply voltage, the level of node 403 is zero, and the 3rd PMOS pipe M6 is operated in linear zone; The 4th NMOS pipe M7 is operated in cut-off region.Now, the output level of node 405 is supply voltage, thereby makes the 5th NMOS pipe M8 conducting, and is operated in linear zone, so the level of node 404 is dragged down, then, the main body circuit 401 of current source circuit returns to the stable operating point of electric current non-zero.

It should be noted that, the main body circuit 401 of current source circuit is operated in after the stable operating point of electric current non-zero, and the 3rd PMOS pipe M6, the 4th NMOS pipe M7 and the 5th NMOS pipe M8 are all operated in cut-off region.That is: complete after the start-up operation of the main body circuit 401 to current source circuit, start-up circuit 402 forwards cut-off state to, and now, start-up circuit 402 does not consume any DC power; In addition, after power connection, if the main body circuit 401 of current source circuit is operated in the quiescent point of electric current non-zero, start-up circuit 402 is not worked.

Under this mode of operation, start-up circuit, except consuming certain power consumption in the process of the main body circuit of starting current source circuit, does not consume any DC power in other processes, can greatly reduce the overall DC power of current source circuit.

It should be noted that, the channel width-over-length ratio of the 3rd PMOS pipe M6 in the embodiment of the present invention can be greater than the channel width-over-length ratio of the 4th NMOS pipe M7.

Threshold voltage formula according to phase inverter:

$V_M\≈\frac{r}{1+r}{V}_{\mathrm{DD}},r=\frac{{\mathrm{\μ}}_p{C}_{\mathrm{OX}}{(W/L)}_p{V}_{\mathrm{DSATp}}}{{\mathrm{\μ}}_n{C}_{\mathrm{OX}}{(W/L)}_n{V}_{\mathrm{DSATn}}}\∝\frac{{(W/L)}_p}{{(W/L)}_n}...\left(9\right)$

Visible, the threshold voltage of phase inverter mainly with the channel width-over-length ratio of PMOS pipe and the channel width-over-length ratio of NMOS pipe between ratio relevant.Therefore, suitably adjust the value of the channel width-over-length ratio of the 3rd PMOS pipe M6 and the 4th NMOS pipe M7, can make the level of node 403 higher than the threshold voltage of phase inverter, thereby make node 405 output low levels, and then improve the overall performance of current source circuit.

The main body circuit that adopts start-up circuit starting current source circuit when quiescent point that the embodiment of the present invention three is zero at the main body circuit working of current source circuit at electric current, has ensured the normal work of current source circuit; Complete after the start-up operation of the main body circuit to current source circuit, start-up circuit forwards cut-off state to, and now, start-up circuit does not consume any DC power; In addition, after power connection, if the main body circuit working of current source circuit in the quiescent point of electric current non-zero, start-up circuit is not worked.Visible, start-up circuit, except consuming certain power consumption in the process of the main body circuit of starting current source circuit, does not consume any DC power in other processes, can greatly reduce the overall DC power of current source circuit.Therefore, the embodiment of the present invention three provides the current source circuit that a kind of temperature coefficient is lower and power consumption is less.

It should be noted that, the start-up circuit in the embodiment of the present invention can also adopt the conventional start-up circuit in other this areas.For example, the start-up circuit providing in the embodiment of the present invention four.

Embodiment tetra-

The embodiment of the present invention four provides a kind of current source circuit, as shown in Figure 5, for the circuit structure diagram of this current source circuit, as seen from the figure, in the particular circuit configurations of this current source circuit, part is identical with the circuit structure (being Fig. 2) of the current source circuit in above-described embodiment one and embodiment bis-, this part is called to the main body circuit of current source circuit; Different is, the embodiment of the present invention four is on the basis of the circuit structure of above-mentioned current source circuit, a kind of start-up circuit is also provided, taking the main body circuit at current source circuit in electric current the main body circuit of starting current source circuit when the quiescent point as zero, even if the quiescent point current source circuit that to make at electric current be zero also can be worked normally.

Particularly, this second start-up circuit 502 comprises a PMOS pipe, a NMOS pipe and a resistance, wherein,

The source electrode of the 4th PMOS pipe M9 is connected with power supply, and drain electrode is connected with the drain electrode of the 2nd PMOS pipe M2, and grid is by the second resistance R 1 and power supply V _ddbe connected;

The source ground of the 6th NMOS pipe M10, drain electrode is connected with grid, and by the second resistance R 1 and power supply V _ddbe connected.

Particularly, when the main body circuit 501 of current source circuit is when to be operated in electric current be zero quiescent point, there is no the main body circuit 501 of electric current current flowing source circuit.Now, the electric current of the 4th PMOS pipe M9 in start-up circuit 502 will flow through main body circuit 501, thereby make main body circuit 501 enter normal duty.Along with main body circuit 501 enters normal operating conditions, the source voltage terminal of the 4th PMOS pipe in start-up circuit 502 constantly raises, and the electric current that flows through the 4th PMOS pipe is reduced to and is approximately zero gradually.

It should be noted that, in the current source circuit of the present embodiment four, start-up circuit completes after the start-up course of the main body circuit to current source circuit, and the metal-oxide-semiconductor in start-up circuit can't forward cut-off state to, but be operated in linear zone, still need to consume certain DC power.

The above is only the preferred embodiment of the present invention; it should be pointed out that for those skilled in the art, under the premise without departing from the principles of the invention; can also make some improvements and modifications, these improvements and modifications also should be considered as protection scope of the present invention.

Claims (6)

1. a current source circuit, is applied to the occasion that low-temperature coefficient is had relatively high expectations, and comprises two PMOS pipes, three NMOS pipes and a resistance, it is characterized in that,

The source electrode of the one PMOS pipe is connected to power supply, and grid is connected with drain electrode;

The source electrode of the 2nd PMOS pipe is connected to described power supply, and grid is connected with the grid of a described PMOS pipe;

The source ground of the one NMOS pipe, drain electrode is connected with the drain electrode of a described PMOS pipe;

The source electrode of the 2nd NMOS pipe is connected with the grid of a described NMOS pipe, and grid is connected with drain electrode, and is connected with the drain electrode of described the 2nd PMOS pipe;

The source electrode of the 3rd NMOS pipe is by the first resistance eutral grounding, and grid is connected with the grid of described the 2nd NMOS pipe, and drain electrode is connected with the grid of a described NMOS pipe;

A described PMOS pipe, the 2nd PMOS pipe, a NMOS pipe, the 2nd NMOS pipe and described the 3rd NMOS pipe are all operated in saturation region.

2. current source circuit according to claim 1, is characterized in that, the channel width-over-length ratio of a described PMOS pipe is identical with the channel width-over-length ratio of described the 2nd PMOS pipe.

3. current source circuit according to claim 1, is characterized in that, the resistance value R of described the first resistance meets:

$R=\frac{V_{\mathrm{TH}}}{I_{\mathrm{DS}}}\frac{k_{{\mathrm{\μ}}_n}+2k_{V_{\mathrm{TH}}}}{k_{{\mathrm{\μ}}_n}}-2\frac{1}{k_{{\mathrm{\μ}}_n}}\frac{\mathrm{dR}}{\mathrm{dT}}$

Wherein, $k_{{\mathrm{\μ}}_n}=\frac{1}{{\mathrm{\μ}}_n}\·\frac{d{\mathrm{\μ}}_n}{\mathrm{dT}},k_{V_{\mathrm{TH}}}=\frac{1}{V_{\mathrm{TH}}}\·\frac{{\mathrm{dV}}_{\mathrm{TH}}}{\mathrm{dT}},I_{\mathrm{DS}}={\mathrm{\μ}}_n{C}_{\mathrm{ox}}\left(\frac{W}{L}\right){(V_{\mathrm{GS}}-V_{\mathrm{TH}})}^2;$

Wherein, V _tHfor the threshold voltage of described the 2nd NMOS pipe, I _dSfor the drain-source current of described the 2nd NMOS pipe, _{μ n}for the mobility of described the 2nd NMOS pipe, C _oxfor the gate oxide electric capacity of the unit area of described the 2nd NMOS pipe, for the channel width-over-length ratio of described the 2nd NMOS pipe, V _gSpoor for the gate source voltage of described the 2nd NMOS pipe, T is kelvin degree.

4. according to the current source circuit described in any one in claims 1 to 3, it is characterized in that, described current source circuit also comprises the first start-up circuit, and described the first start-up circuit comprises a PMOS pipe and two NMOS pipes, wherein,

The source electrode of the 3rd PMOS pipe is connected to described power supply, and grid is connected with the grid of a described NMOS pipe;

The source ground of the 4th NMOS pipe, grid is connected with the grid of described the 3rd PMOS pipe, and drain electrode is connected with the drain electrode of described the 3rd PMOS pipe;

The source ground of the 5th NMOS pipe, grid is connected with the drain electrode of described the 3rd PMOS pipe, and drain electrode is connected with the grid of a described PMOS pipe.

5. current source circuit according to claim 4, is characterized in that, the channel width-over-length ratio of described the 3rd PMOS pipe is greater than the channel width-over-length ratio of described the 4th NMOS pipe.

6. according to the current source circuit described in claim 1-3 any one, it is characterized in that, described current source circuit also comprises the second start-up circuit, and described the second start-up circuit comprises a PMOS pipe, a NMOS pipe and a resistance, wherein,

The source electrode of the 4th PMOS pipe is connected to described power supply, and drain electrode is connected with the drain electrode of described the 2nd PMOS pipe, and grid connects power supply by the second resistance;

The source ground of the 6th NMOS pipe, grid is connected and connects power supply by described the second resistance with drain electrode.