CN105739586A - Current reference source circuit - Google Patents

Abstract

The invention belongs to the technical field of current sources, and discloses a current reference source circuit. Due to adoption of the current reference source circuit which comprises a starting module, a mirror image current module and a reference current generating module, after the current reference source circuit is electrified, the reference current generating module is controlled by the starting module to work, offset voltage is generated from a second branch unit of the reference current generating module, first current flowing into a first branch unit is mirrored to a third branch unit by the mirror image current module so as to generate second current; the second current is equal to first current, third current is generated by the second branch unit according to the first current, the second current and the offset voltage, the third current is mirrored to the a fourth output end of the mirror image current module by the mirror image current module so as to output reference current, and the reference current is equal to the third current, so that the problems that a conventional current reference source circuit is large in consumed chip area and low in precision can be solved.

Description

A kind of current reference source circuit

Technical field

The invention belongs to current source technology field, particularly relate to a kind of current reference source circuit.

Background technology

Reference current source refers to the current source of the high accuracy of the current reference being used as other circuit in Analogous Integrated Electronic Circuits, low-temperature coefficient, and current source is as the Key Circuit unit of Analogous Integrated Electronic Circuits, it is widely used in operational amplifier, A/D converter, D/A converter.Owing to reference current source is to export electric current to other modules of system, therefore, the precision of reference current source directly influences the precision and stability of whole system, and the principal element of the precision and stability affecting reference current source is temperature.

At present, affecting produced by variations in temperature to eliminate reference current source, prior art realizes mainly through band-gap reference source circuit.Band-gap reference source circuit obtains the bandgap voltage reference of a temperature-compensating mainly by bipolar transistor devices, and then is obtained the reference current of a not temperature influence by resistance device.But, owing to band-gap reference source circuit needs to use bipolar transistor, and the volume of bipolar transistor is big, the chip area thus resulting in band-gap reference source circuit consumption is big, and the high-order nonlinear factor of bipolar transistor can restrict the precision of the temperature coefficient of reference current, and then affects the precision of band-gap reference source circuit；In addition, due to the impact of processing technology, can there is deviation in the actual resistance of resistance and theoretical value, and resistance is the element that temperature is comparatively sensitive, its resistance value can change along with temperature increases, and therefore the precision of band-gap reference source circuit can be produced impact by the existence of resistance.

In sum, there is the problem that chip area is big and precision is low consumed in existing current reference source circuit.

Summary of the invention

It is an object of the invention to provide a kind of current reference source circuit, it is intended to solve existing current reference source circuit and there is the problem that chip area is big and precision is low consumed.

The present invention is achieved in that a kind of current reference source circuit, and described current reference source circuit includes starting module, image current module and reference current generation module；

nullDescribed reference current generation module includes the first tributary unit、Second tributary unit and the 3rd tributary unit，Described first tributary unit and described second tributary unit all include a MOS device，Described 3rd tributary unit includes multiple MOS device，The input of the input of described startup module and described image current module is connected to external power source altogether，First outfan of described image current module、Second outfan and the 3rd outfan respectively with the input of described first tributary unit、The input of described second tributary unit and the input of described 3rd tributary unit connect，The input of described second tributary unit is connected with the first outfan of described startup module，Second outfan of described startup module、The outfan of described first tributary unit、The outfan of described second tributary unit and the outfan of described 3rd tributary unit are connected to ground altogether；

After described current reference source circuit powers on, described startup module controls the work of described reference current generation module, second tributary unit of described reference current generation module produces offset voltage, described image current module will flow into the first current mirror of described first tributary unit to described 3rd tributary unit to produce the second electric current, and described second electric current is equal to described first electric current；Described second tributary unit produces the 3rd electric current according to described first electric current, described second electric current and described offset voltage, described image current module is by the 4th outfan of described 3rd current mirror to described image current module with output reference electric current, and described reference current is equal to described 3rd electric current.

In the present invention, by adopting the current reference source circuit including starting module, image current module and reference current generation module, make after current reference source circuit powers on, start module and control the work of reference current generation module, second tributary unit of reference current generation module produces offset voltage, image current module will flow into the first current mirror of the first tributary unit to the 3rd tributary unit to produce the second electric current, and the second electric current is equal to the first electric current；Second tributary unit produces the 3rd electric current according to the first electric current, the second electric current and offset voltage, image current module by the 4th outfan of the 3rd current mirror to image current module with output reference electric current, reference current is equal to the 3rd electric current, and then make this current reference source circuit without using bipolar transistor and resistance just can produce reference current, thus solve existing current reference source circuit there is the problem that chip area is big and precision is low consumed.

Accompanying drawing explanation

Fig. 1 is the modular structure schematic diagram of the current reference source circuit that one embodiment of the invention provides；

Fig. 2 is the exemplary circuit structure chart of the current reference source circuit shown in Fig. 1；

Fig. 3 is the threshold difference voltage Δ Vt in the current reference source circuit that one embodiment of the invention provides_h23The curve chart varied with temperature；

Fig. 4 is the temperature characteristics figure of the reference current that the current reference source circuit that one embodiment of the invention provides produces；

Fig. 5 is the temperature characteristics analogous diagram of the current reference source circuit that provides of one embodiment of the invention reference current under five kinds of process corner.

Detailed description of the invention

In order to make the purpose of the present invention, technical scheme and advantage clearly understand, below in conjunction with drawings and Examples, the present invention is further elaborated.Should be appreciated that specific embodiment described herein is only in order to explain the present invention, is not intended to limit the present invention.

Below in conjunction with concrete accompanying drawing, the realization of the present invention is described in detail:

Fig. 1 illustrates the modular structure of the current reference source circuit that one embodiment of the invention provides, and for the ease of illustrating, only illustrating part related to the present embodiment, details are as follows:

In the present embodiment, current reference source circuit includes starting module 10, image current module 20 and reference current generation module 30.nullWherein，Reference current generation module 30 includes the first tributary unit 301、Second tributary unit 302 and the 3rd tributary unit 303，First tributary unit 300 and the second tributary unit 302 all include a MOS device，3rd tributary unit 303 includes multiple MOS device，The input of the input and image current module 20 that start module 10 is connected to external power source VDD altogether，First outfan of image current module 20、Second outfan and the 3rd outfan respectively with the input of the first tributary unit 301、The input of the second tributary unit 302 and the input of the 3rd tributary unit 303 connect，The input of the second tributary unit 302 is connected with the first outfan starting module 10，Start the second outfan of module 10、The outfan of the first tributary unit 301、The outfan of the second branch road 302 and the outfan of the 3rd tributary unit 303 are connected to ground altogether.

Concrete, after current reference source circuit powers on, startup module 10 controls reference current generation module 30 and works, and the second tributary unit 302 of reference current generation module 30 produces offset voltage Δ V, and image current module 20 will flow into the first electric current I of the first tributary unit 301_D0Mirror image to the 3rd tributary unit 303 to produce the second electric current I_D1, the second electric current I_D1Equal to the first electric current I_D0；Second tributary unit 302 is according to the first electric current I_D0, the second electric current I_D1And offset voltage Δ V produces the 3rd electric current I_REF, image current module 20 is by the 3rd electric current I_REFMirror image is equal to the 3rd electric current I to the 4th outfan of image current module with output reference electric current I, reference current I_REF。

In the present embodiment, by adopting the current reference source circuit including starting module 10, image current module 20 and reference current generation module 30, make after current reference source circuit powers on, startup module 10 controls reference current generation module 30 and works, second tributary unit 302 of reference current generation module 30 produces offset voltage Δ V, and image current module 20 will flow into the first electric current I of the first tributary unit 301_D0Mirror image to the 3rd tributary unit 303 to produce the second electric current I_D1, the second electric current I_D1Equal to the first electric current I_D0；Second tributary unit 302 is according to the first electric current I_D0, the second electric current I_D0And offset voltage Δ V produces the 3rd electric current I_REF, image current module 20 is by the 3rd electric current I_REFMirror image is equal to the 3rd electric current I to the 4th outfan of image current module 20 with output reference electric current I, reference current I_REF, and then make this current reference source circuit without using bipolar transistor and resistance just can produce reference current I, thus solving existing current reference source circuit there is the problem that chip area is big and precision is low consumed.

Further, as one embodiment of the present invention, as in figure 2 it is shown, the first tributary unit 301 includes the first MOS device M0, the input of this first MOS device M0 is the input of the first tributary unit 301, and the outfan of this first MOS device M0 is the outfan of the first tributary unit 301.

Further, as one embodiment of the present invention, as in figure 2 it is shown, the 3rd tributary unit 303 includes the second MOS device M1, the input of the second MOS device M1 is the input of the 3rd tributary unit 303, and the outfan of the second MOS device M1 is the outfan of the 3rd tributary unit 303.

Further, as one embodiment of the present invention, as shown in Figure 2, second tributary unit 302 includes the 3rd MOS device M2, the 4th MOS device M3 and the 5th MOS device M4, and the 4th electric current that the 3rd MOS device M2 and the four MOS device M3 flows into the second tributary unit 302 according to image current module 20 produces offset voltage Δ V；The end that controls of the 3rd MOS device M2 connects the input forming the second tributary unit 302 altogether with input, the control end of the outfan of the 3rd MOS device M2 and the input of the 4th MOS device M3 and the second MOS device M1 connects, the control end controlling end and the 3rd MOS device M2 of the 4th MOS device M3 connects, the control end of the outfan of the 4th MOS device M3 and the input of the 5th MOS device M4, control end and the first MOS device M0 connects altogether, and the outfan of the 5th MOS device M4 is the outfan of the second tributary unit 302.

Further, as one embodiment of the present invention, first MOS device M0, the second MOS device M1, the 3rd MOS device M2, the 4th MOS device M3 and the 5th MOS device M4 are NMOS tube, and the grid of NMOS tube, drain electrode and source electrode be corresponding first MOS device M0, the second MOS device M1, the 3rd MOS device M2, the 4th MOS device M3 and the control end of the 5th MOS device M4, input and outfan respectively.

Further, as one embodiment of the present invention, as in figure 2 it is shown, start module 10 to include the 6th MOS device M5, the 7th MOS device M6, the 8th MOS device M7, the 9th MOS device M8, the tenth MOS device M9 and the 11st MOS device M10.

nullWherein，The control end of the 6th MOS device M5 and input、The control end of the 7th MOS device M6、The control end of the 8th MOS device M7、The control end of the 9th MOS device M8、The control end controlling end and outfan and the 11st MOS device M10 of the tenth MOS device M9 connects altogether，The input of the 11st MOS device M10 and the input of the 9th MOS device M8 connect altogether and form the input starting module 10，The outfan of the 9th MOS device M8 and the input of the tenth MOS device M9 connect，The outfan of the 11st MOS device M10 is the first outfan starting module 10，The outfan of the 6th MOS device M5 and the input of the 7th MOS device M6 connect，The outfan of the 7th MOS device M6 and the input of the 8th MOS device M7 connect，The outfan of the 8th MOS device M7 is the second outfan starting module 10.

Further, as one embodiment of the present invention, as in figure 2 it is shown, image current module 20 includes the 12nd MOS device M11, the 13rd MOS device M12, the 14th MOS device M13 and the 15th MOS device M14.

nullWherein，The input of the 12nd MOS device M11、The input of the 13rd MOS device M12、The input of the 14th MOS device M13 and the input of the 15th MOS device M14 connect the input forming image current module 20 altogether，The control end of the 12nd MOS device M11、The control end of the 13rd MOS device M12、The control end of the 14th MOS device M13、The outfan of the 14th MOS device M13 and the control end of the 15th MOS device M14 connect altogether，First outfan that outfan is image current module 20 of the 12nd MOS device M11，Second outfan that outfan is image current module 20 of the 13rd MOS device M12，The 3rd outfan that outfan is image current module 20 of the 14th MOS device M13，The 4th outfan that outfan is image current module 20 of the 15th MOS device M14.

Further, as one embodiment of the present invention, 12nd MOS device M11, the 13rd MOS device M12, the 14th MOS device M13 and the 15th MOS device M14 are PMOS, and the grid of PMOS, source electrode and drain electrode be corresponding 12nd MOS device M11, the 13rd MOS device M12, the 14th MOS device M13 and the control end of the 15th MOS device M14, input and outfan respectively.

Further, as one embodiment of the present invention, 12nd MOS device M11, the 13rd MOS device M12, the 14th MOS device M13 and the 15th MOS device M14 equivalently-sized, namely the breadth length ratio of the breadth length ratio of the 12nd MOS device M11, the breadth length ratio of the 13rd MOS device M12, the breadth length ratio of the 14th MOS device M13 and the 15th MOS device M14 is all identical.

For the physical circuit shown in Fig. 2, the operation principle of current reference source circuit provided by the invention is elaborated below:

nullAfter current reference source circuit powers on，6th MOS device M5、7th MOS device M6、8th MOS device M7、9th MOS device M8 and the tenth MOS device M9 flows through a certain amount of weak current，Due to the 6th MOS device M5、7th MOS device M6、8th MOS device M7、9th MOS device M8 and the tenth MOS device M9 disconnects，6th MOS device M5、7th MOS device M6、8th MOS device M7、9th MOS device M8 and the tenth MOS device M9 is now equivalent to the resistance that resistance is very big，Therefore，The grid of the 6th MOS device M5、The grid of the 7th MOS device M6、The grid of the 8th MOS device M7、The grid of the 9th MOS device M8 and the grid of the tenth MOS device M9 are in positive high-voltage state，Therefore，The grid of the 11st MOS device M10 is similarly in high-voltage state，And then the 11st MOS device M10 control reference current generation module 30 work.

After reference current generation module 30 works, the current mirror between the 12nd MOS device M11 and the 14 MOS device M13 will flow into the first electric current I of the first MOS device M0_D0Mirror image to the second MOS device M1 to produce the second electric current I_D1, the second electric current I_D1Equal to the first electric current I_D0, and the first electric current I_D0With the second electric current I_D1Can be represented by following two formula:

$I_{D0}=\frac{1}{2}{K}_n{S}_0{(V_{gs0}-V_{th0})}^2;---\left(1\right)$

$I_{D1}=\frac{1}{2}{K}_n{S}_1{(V_{gs1}-V_{th1})}^2;---\left(2\right)$

Wherein, K_n=μ * C_OX, C_OXFor the unit are grid oxygen electric capacity of MOS device, μ is carrier mobility, S₁With S₀The respectively size ratio of the second MOS device M1 and the first MOS device M0, V_th1With V_th0The respectively threshold voltage of the second MOS device M1 and the first MOS device M0, V_gs1It is the grid-source voltage of the second MOS device M1, V_gs0It it is the grid-source voltage of the first MOS device M0.

And the first electric current I can be obtained by image current module 20_D0, the second electric current I_D1The 3rd electric current I with the second tributary unit 302 generation_REFIt is equal, it may be assumed that

I_D1=I_D0=I_REF；(3)

And then can be obtained by formula (1), formula (2) and formula (3):

$I_{REF}=\frac{1}{2}{\mathrm{\μC}}_{OX}\·\frac{1}{{(\sqrt{\frac{1}{S_1}}-\sqrt{\frac{1}{S_0}})}^2}\·{(V_{gs1}-V_{gs0})}^2;---\left(4\right)$

And according to the annexation between the first MOS device M0, the second MOS device M1 and the 4th MOS device M3:

V_gs1-V_gs0=V_ds3；(5)

Δ V=V_ds3；(6)

Wherein, V_ds3It it is the dram-source voltage of the 4th MOS device M3.

Further, formula (4), formula (5) and formula (6) push away further:

$I_{REF}=\frac{1}{2}{\mathrm{\μC}}_{OX}\·\frac{1}{{(\sqrt{\frac{1}{S_1}}-\sqrt{\frac{1}{S_0}})}^2}\·{\left(\mathrm{\Δ}V\right)}^2;---\left(7\right)$

Further, after current reference source circuit powers on, 3rd MOS device M2 is very easy to be operated in linear zone, 4th MOS device M3 is usually operated at saturation region, and when image current module 20 has the 4th electric current to flow into the second tributary unit 302, second tributary unit 302 forms path according to the 4th electric current flowed into, and namely flows through the electric current I of the 3rd MOS device M2_D2With the electric current I flowing through the 4th MOS device M3_D3Equal, and electric current I_D2, electric current I_D3And electric current I_REFEqual, namely

I_D2=I_D3=I_REF；(8)

Further, can obtain according to the annexation between the 3rd MOS device M2 and the four MOS device M3:

V_gs3=V_gs2+V_ds3；(9)

Wherein, V_gs2With V_gs3The respectively grid-source voltage of the grid-source voltage of the 3rd MOS device M2 and the 4th MOS device M3.

And electric current I_D2, electric current I_D3Can be obtained by below equation:

$I_{D2}=\frac{1}{2}{K}_n{S}_2{(V_{gs2}-V_{th2})}^2;---\left(10\right)$

$I_{D3}=K_n{S}_3\[(V_{gs3}-V_{th3})\·V_{ds3}-\frac{1}{2}{V_{ds3}}^2\];---\left(11\right)$

Wherein, S₂With S₃The respectively size ratio of the 3rd MOS device M2 and the four MOS device M3, V_th2With V_th3The respectively threshold voltage of the 3rd MOS device M2 and the four MOS device M3.

Further, formula (8), formula (9), formula (10) and formula (11) offset voltage Δ V and V can be obtained_ds3Formula be:

$V_{ds3}=\sqrt{\frac{2I_{D2}}{K_n*S_2}}\[\sqrt{{(1-\frac{{\mathrm{\ΔV}}_{th23}}{\sqrt{\frac{2I_{D2}}{K_n\·S_2}}})}^2+\frac{S_2}{S_3}}+\frac{{\mathrm{\ΔV}}_{th23}}{\sqrt{\frac{2I_{D2}}{K_n\·S_2}}}-1\];---\left(12\right)$

Wherein, Δ V_th23It it is the threshold voltage difference between threshold voltage and the threshold voltage of the 4th MOS device M3 of the 3rd MOS device M2.

Further, can obtain in conjunction with formula (7) and formula (12):

$I_{REF}=\frac{1}{2}{S}_2\frac{K_n\·{\left({\mathrm{\ΔV}}_{th23}\right)}^2}{{\[1+\frac{3}{2}\·(\sqrt{\frac{S_2}{S_1}}-\sqrt{\frac{S_2}{S_0}})-\frac{\frac{S_2}{S_3}}{2\·(\sqrt{\frac{S_2}{S_1}}-\sqrt{\frac{S_2}{S_0}})}\]}^2};---\left(13\right)$

And image current module 20 is by the 3rd electric current I_REFMirror image is to the 4th outfan of image current module 20 with output reference electric current I, and this reference current I is equal to the 3rd electric current I_REF, say, that under the mirror image effect between the 13rd MOS device M12 and the 15 MOS device M14, reference current I and the three electric current I of the 15th MOS device M14 output_REFEqual, i.e. reference current I and the three electric current I of power reference source circuit output_REFEqual.

In the expression formula (13) of the 3rd electric current, K_n=μ * C_OXRelevant with concrete technique, and C_OXBeing the unit are grid oxygen electric capacity of transistor, be the technological parameter of a temperature independent system, μ is carrier mobility, and its temperature characterisitic can by formulaRepresent, by formulaIt can be seen that electron mobility μ has negative temperature characterisitic, its temperature coefficient is negative；Additionally, as it is shown on figure 3, threshold voltage difference Δ V_th23Raise along with the rising of temperature, say, that threshold voltage difference Δ V_th23Having positive temperature characterisitic, its temperature coefficient is just, therefore K_n·(ΔV_th23)²Temperature coefficient can be compensated, and then make the 3rd electric current I_REFSize temperature independent, namely the size of reference current I is temperature independent.

Fig. 4 illustrates the temperature characteristics figure of the reference current I that the current reference source circuit that one embodiment of the invention provides produces, wherein, what abscissa represented is temperature, that vertical coordinate represents is reference current I, as shown in Figure 4, when temperature changes between 1 degree Celsius to 110 degree Celsius, reference current I is changed between 9.00 μ Α and 9.15 μ Α, its intensity of variation is very little, and therefore, the reference current I of current reference source circuit provided by the invention output can eliminate the temperature impact on it.

nullFig. 5 illustrates the temperature characteristics analogous diagram of current reference source circuit that one embodiment of the invention the provides reference current I under different process angle，Wherein，What abscissa represented is temperature，That vertical coordinate represents is reference current I，What a represented is the temperature characteristics analogous diagram of the reference current I under FF process corner，What b represented is the temperature characteristics analogous diagram of the reference current I under FnSp process corner，What c represented is the temperature characteristics analogous diagram of the reference current I under TT process corner，What d represented is the temperature characteristics analogous diagram of the reference current I under SnFp process corner，What e represented is the temperature characteristics analogous diagram of the reference current I under SS process corner，As shown in Figure 5，The current reference source circuit that one embodiment of the invention provides reference current I under different process angle is along with variations in temperature is almost without change，That is，The reference current I of current reference source circuit provided by the invention output，When five kinds of process corner，All can realize temperature-compensating.

In the present embodiment, by comprising the current reference source circuit of the first MOS device M0 to the 15th MOS device M14, and each MOS device respectively PMOS or NMOS tube so that the 12nd MOS device M11 and the 14 MOS device M13 will flow through the first electric current I of the first MOS device M0_D0Mirror image to the second MOS device M1 to obtain and the first electric current I_D0The second equal electric current I_D1, and then make reference current output module 30 according to the 3rd MOS device M2 and the 4th MOS device M3 offset voltage Δ V, I produced_D0And I_D1Obtain threeth electric current I incoherent with temperature_REF, the 13rd MOS device M12 is according to the mirror image effect between itself and the 15th MOS device M14, by the 3rd electric current I_REFMirror image is to the outfan of the 15th MOS device M14, so that this current reference source circuit output reference electric current I, this reference current I and the three electric current I_REFEqual, so that the current reference source circuit that the embodiment of the present invention provides is without using bipolar transistor and resistance, integrated type of device is reduced, and then reduce the volume of current reference source circuit, and simple in construction, it is easily integrated, and eliminate the temperature impact on the reference current that current reference source circuit produces, and then solve the problem that chip area is big and precision is low that the existence of existing current reference source circuit consumes.

The foregoing is only presently preferred embodiments of the present invention, not in order to limit the present invention, all any amendment, equivalent replacement and improvement etc. made within the spirit and principles in the present invention, should be included within protection scope of the present invention.

Claims (9)

1. a current reference source circuit, it is characterised in that described current reference source circuit includes starting module, image current module and reference current generation module；

nullDescribed reference current generation module includes the first tributary unit、Second tributary unit and the 3rd tributary unit，Described first tributary unit and described second tributary unit all include a MOS device，Described 3rd tributary unit includes multiple MOS device，The input of the input of described startup module and described image current module is connected to external power source altogether，First outfan of described image current module、Second outfan and the 3rd outfan respectively with the input of described first tributary unit、The input of described second tributary unit and the input of described 3rd tributary unit connect，The input of described second tributary unit is connected with the first outfan of described startup module，Second outfan of described startup module、The outfan of described first tributary unit、The outfan of described second tributary unit and the outfan of described 3rd tributary unit are connected to ground altogether；

After described current reference source circuit powers on, described startup module controls the work of described reference current generation module, second tributary unit of described reference current generation module produces offset voltage, described image current module will flow into the first current mirror of described first tributary unit to described 3rd tributary unit to produce the second electric current, and described second electric current is equal to described first electric current；Described second tributary unit produces the 3rd electric current according to described first electric current, described second electric current and described offset voltage, described image current module is by the 4th outfan of described 3rd current mirror to described image current module with output reference electric current, and described reference current is equal to described 3rd electric current.

2. current reference source circuit according to claim 1, it is characterized in that, described first tributary unit includes the first MOS device, and the input of described first MOS device is the input of described first tributary unit, and the outfan of described first MOS device is the outfan of described first tributary unit.

3. current reference source circuit according to claim 2, it is characterized in that, described 3rd tributary unit includes the second MOS device, and the input of described second MOS device is the input of described 3rd tributary unit, and the outfan of described second MOS device is the outfan of described 3rd tributary unit.

4. current reference source circuit according to claim 3, it is characterized in that, described second tributary unit includes the 3rd MOS device, the 4th MOS device and the 5th MOS device, and the 4th electric current that described 3rd MOS device flows into described second tributary unit with described 4th MOS device according to described image current module produces described offset voltage；The end that controls of described 3rd MOS device connects, with input, the input forming described second tributary unit altogether, the outfan of described 3rd MOS device is connected with the input of described 4th MOS device and the control end of described second MOS device, the end that controls of described 4th MOS device is connected with the control end of described 3rd MOS device, the control end of the outfan of described 4th MOS device and the input of described 5th MOS device, control end and described first MOS device connects altogether, the outfan that outfan is described second tributary unit of described 5th MOS device.

5. current reference source circuit according to claim 4, it is characterized in that, described first MOS device, described second MOS device, described 3rd MOS device, described 4th MOS device and described 5th MOS device are NMOS tube, and the grid of described NMOS tube, drain electrode and source electrode be corresponding described first MOS device, described second MOS device, described 3rd MOS device, described 4th MOS device and the control end of described 5th MOS device, input and outfan respectively.

6. current reference source circuit according to claim 1, it is characterised in that described startup module includes the 6th MOS device, the 7th MOS device, the 8th MOS device, the 9th MOS device, the tenth MOS device and the 11st MOS device；

nullThe control end of described 6th MOS device and input、The control end of described 7th MOS device、The control end of described 8th MOS device、The control end of described 9th MOS device、The control end controlling end and outfan and described 11st MOS device of described tenth MOS device connects altogether，The input of described 11st MOS device and the input of described 9th MOS device connect the input forming described startup module altogether，The outfan of described 9th MOS device is connected with the input of described tenth MOS device，First outfan that outfan is described startup module of described 11st MOS device，The outfan of described 6th MOS device is connected with the input of described 7th MOS device，The outfan of described 7th MOS device is connected with the input of described 8th MOS device，Second outfan that outfan is described startup module of described 8th MOS device.

7. current reference source circuit according to claim 1, it is characterised in that described image current module includes the 12nd MOS device, the 13rd MOS device, the 14th MOS device and the 15th MOS device；

nullThe input of described 12nd MOS device、The input of described 13rd MOS device、The input of described 14th MOS device and the input of described 15th MOS device connect the input forming described image current module altogether，The control end of described 12nd MOS device、The control end of described 13rd MOS device、The control end of described 14th MOS device、The outfan of described 14th MOS device and the control end of described 15th MOS device connect altogether，First outfan that outfan is described image current module of described 12nd MOS device，Second outfan that outfan is described image current module of described 13rd MOS device，The 3rd outfan that outfan is described image current module of described 14th MOS device，The 4th outfan that outfan is described image current module of described 15th MOS device.

8. current reference source circuit according to claim 7, it is characterized in that, described 12nd MOS device, described 13rd MOS device, described 14th MOS device and described 15th MOS device are PMOS, and the grid of described PMOS, source electrode and drain electrode be corresponding described 12nd MOS device, described 13rd MOS device, described 14th MOS device and the control end of described 15th MOS device, input and outfan respectively.

9. current reference source circuit according to claim 8, it is characterised in that described 12nd MOS device, described 13rd MOS device, described 14th MOS device and described 15th MOS device equivalently-sized.