CN103869868A - Band-gap reference circuit with temperature compensation function - Google Patents

Abstract

The invention discloses a band-gap reference circuit with a temperature compensation function, and belongs to the technical field of microelectronics. By means of the band-gap reference circuit with the temperature compensation function, segmented current INL and current IP11 directly proportional to temperature T1.5 are added to the traditional first-order band-gap reference circuit, and namely the leakage current of a PMOS tube MP7 in a high-order temperature compensation circuit and the leakage current of a PMOS tube MP11 in the high-order temperature compensation circuit are added to a resistor R5 to achieve high-order temperature compensation so as to obtain a reference voltage. Due to the adoption of the technology, the reference voltage with the small temperature coefficient can be obtained.

Description

A kind of band-gap reference reference circuit with temperature compensation

Technical field

The invention belongs to microelectronics technology, particularly relate to a kind of band-gap reference reference circuit with temperature compensation.

Background technology

Band-gap reference circuit is widely used in Analogous Integrated Electronic Circuits and hydrid integrated circuit system, as data converter, power management and oscillator etc., its Main Function is to provide stable reference voltage or electric current for other unit of system, its temperature coefficient (TC, Temperature Coefficient) quality of decision systems performance to a great extent.

As shown in Figure 1, traditional band-gap reference circuit is NPN type transistor base and the emitter both end voltage V based on negative temperature coefficient _bEthermal voltage with positive temperature coefficient (PTC)

the principle of linear superposition, wherein k is Boltzmann constant, and T is absolute temperature, and q is electron charge.

According to superposition principle, can obtain bandgap voltage reference V _rEFexpression formula be V _rEF=V _bE+ m × V _t, wherein, thermal voltage V _tfor being proportional to the voltage of absolute temperature (PTAT, Proporational To Absolute Temperature), V _bEthere is negative temperature coefficient, rationally adjust the size of Coefficient m, in certain temperature range, just can obtain the band-gap reference reference voltage V of zero-temperature coefficient _rEF.

But, due to V _bEthe non-linear band-gap reference reference voltage that makes first compensation phase there is larger temperature coefficient, thereby restricted the application of single order band-gap reference circuit in High Precision Low Temperature degree coefficient system.

Summary of the invention

Because the above-mentioned defect of prior art, technical matters to be solved by this invention is to provide a kind of higher compensation stability that has, and can greatly reduce the band-gap reference reference circuit of output voltage temperature coefficient.

For achieving the above object, the invention provides a kind of band-gap reference reference circuit with temperature compensation, comprise start-up circuit, single order band-gap reference circuit and high-order temperature compensation circuit; The enabling signal output terminal of described start-up circuit connects respectively the enabling signal input end of described single order band-gap reference circuit and high-order temperature compensation circuit; The current signal output end of described single order band-gap reference circuit connects the current signal input end of described high-order temperature compensation circuit.

Described start-up circuit comprises: a PMOS pipe and the 2nd PMOS pipe, a NMOS pipe, the 2nd NMOS pipe, the 3rd NMOS pipe and the 4th NMOS pipe.

Described single order band-gap reference circuit comprises: the 3rd PMOS pipe, the 4th PMOS pipe, the 5th PMOS pipe, the 6th PMOS pipe and the 7th PMOS pipe, the first positive-negative-positive triode and the second positive-negative-positive triode, the first error amplifier and the second error amplifier, the first resistance, the second resistance, the 3rd resistance, the 4th resistance and the 5th resistance.

Described high-order temperature compensation circuit comprises: the 8th PMOS pipe, the 9th PMOS pipe, the tenth PMOS pipe, the 11 PMOS pipe, the 12 PMOS pipe, the 13 PMOS pipe, the 14 PMOS pipe and the 15 PMOS pipe, the 5th NMOS pipe, the 6th NMOS pipe, the 7th NMOS pipe, the 8th NMOS pipe, the 9th NMOS pipe and the tenth NMOS pipe.

The source electrode of a described PMOS pipe is connected with external power source, the drain electrode of a described PMOS pipe is connected with the source electrode of described the 2nd PMOS pipe, the grid of a PMOS pipe, the drain electrode of described the 2nd PMOS pipe is connected with the grid of the 2nd PMOS pipe, the drain electrode of a NMOS pipe, the grid of the 2nd NMOS pipe, the grid of the 3rd NMOS pipe, the grid of the 4th NMOS pipe, and the source electrode of a described NMOS pipe is connected with the source electrode of outside ground wire, the 2nd NMOS pipe, the source electrode of the 3rd NMOS pipe, the source electrode of the 4th NMOS pipe.

The source electrode of described the 3rd PMOS pipe is connected with the source electrode of external power source, the 4th PMOS pipe, the grid of the 3rd PMOS pipe is connected with the drain electrode of the 2nd NMOS pipe of the grid of the 4th PMOS pipe, the grid of the 7th PMOS pipe, the output terminal of the first error amplifier, described start-up circuit, the drain electrode of the 3rd PMOS pipe is connected with the reverse input end of the first error amplifier, the emitter of the first positive-negative-positive triode, and the base stage of the first positive-negative-positive triode is connected with the collector of the first positive-negative-positive triode, outside ground wire.

The drain electrode of described the 4th PMOS pipe is connected with the positive input of the first error amplifier, the reverse input end of the second error amplifier, one end of the first resistance, the other end of described the first resistance is connected with the emitter of the second positive-negative-positive triode, and the base stage of described the second positive-negative-positive triode is connected with the collector of outside ground wire GND, the second positive-negative-positive triode.

The source electrode of described the 5th PMOS pipe is connected with external power source, the grid of described the 5th PMOS pipe is connected with the drain electrode of the 3rd NMOS pipe of the output terminal of the second error amplifier, the grid of the 6th PMOS pipe, described start-up circuit, the drain electrode of described the 5th PMOS pipe is connected with the positive input of the second error amplifier, one end of the second resistance, and the other end of described the second resistance is connected with outside ground wire GND.

The source electrode of described the 6th PMOS pipe is connected with the source electrode of external power source, the 7th PMOS pipe, the drain electrode of described the 6th PMOS pipe is connected with one end of the 3rd resistance, one end of the 4th resistance, the grid of the one NMOS pipe of the drain electrode of the other end of described the 3rd resistance and the 7th PMOS pipe, single order band-gap reference circuit output terminal VREF, described start-up circuit is connected, the other end of described the 4th resistance is connected with one end of the 5th resistance, and the other end of described the 5th resistance is connected with outside ground wire GND.

The source electrode of described the 8th PMOS pipe is connected with external power source, the grid of described the 8th PMOS pipe is connected with the grid of the 4th PMOS pipe of described single order band-gap reference, the drain electrode of the 8th PMOS pipe is connected with the drain electrode of the 5th NMOS pipe, the grid of the 5th NMOS pipe, the grid of the 6th NMOS pipe, and the source electrode of described the 5th NMOS pipe is connected with the source electrode of the 6th NMOS pipe, outside ground wire.

The source electrode of described the 9th PMOS pipe is connected with external power source, the grid of described the 9th PMOS pipe is connected with the grid of the 5th PMOS pipe of described single order band-gap reference circuit, and the drain electrode of described the 9th PMOS pipe is connected with the grid of the tenth PMOS pipe, the drain electrode of the tenth PMOS pipe, the grid of the 11 PMOS pipe, the drain electrode of the 6th NMOS pipe.

The source electrode of described the 11 PMOS pipe is connected with the source electrode of external power source, the tenth PMOS pipe, and the drain electrode of described the 11 PMOS pipe is connected between described the 4th resistance and the 5th resistance.

The source electrode of described the 12 PMOS pipe is connected with external power source, the grid of described the 12 PMOS pipe is connected with the grid of the 4th PMOS pipe of described single order band-gap reference circuit, the drain electrode of described the 12 PMOS pipe is connected with the drain electrode of the 7th NMOS pipe, the grid of the 7th NMOS pipe, the grid of the 8th NMOS pipe, and the source electrode of described the 7th NMOS pipe is connected with the source electrode of the 8th NMOS pipe, outside ground wire.

The source electrode of described the 13 PMOS pipe and external power source, the source electrode of the 14 PMOS pipe is connected, described the 13 grid of PMOS pipe and the grid of the 14 PMOS pipe, the drain electrode of the 13 PMOS pipe, the drain electrode of the 9th NMOS pipe, the drain electrode of the 4th NMOS pipe of described start-up circuit is connected, the grid of the grid of described the 9th NMOS pipe and the tenth NMOS pipe, the drain electrode of the tenth NMOS pipe, the drain electrode of the 14 PMOS pipe is connected, the source electrode of described the 9th NMOS pipe is connected with the drain electrode of the 8th NMOS pipe, the source electrode of the source electrode of described the 8th NMOS pipe and the tenth NMOS pipe, outside ground wire GND is connected.

The source electrode of described the 15 PMOS pipe is connected with external power source, and the grid of described the 15 PMOS pipe is connected with the grid of the 13 PMOS pipe, and the drain electrode of described the 15 PMOS pipe is connected between described the 4th resistance and the 5th resistance.

The invention has the beneficial effects as follows: the band-gap reference of temperature compensation of the present invention is with reference to passing through segmented current I _nLand and temperature T ^1.5the electric current I being directly proportional _p11join in traditional single order band-gap reference circuit, by the leakage current of the leakage current of the 11 PMOS pipe MP7 in high-order temperature compensation circuit and the 15 PMOS pipe MP11 is joined in resistance R 5, realize high-order temperature compensated, obtain reference voltage, adopt this technology, can obtain the reference voltage of less temperature coefficient.

Brief description of the drawings

Fig. 1 is the basic principle schematic of traditional single order band-gap reference reference.

Fig. 2 is circuit theory schematic diagram of the present invention.

Fig. 3 is the electrical block diagram of the band-gap reference reference of temperature compensation of the present invention.

Fig. 4 is single order band-gap reference reference output voltage curve synoptic diagram.

Fig. 5 is the output voltage curve synoptic diagram of the band-gap reference reference of temperature compensation of the present invention.

Fig. 6 is the temperature characterisitic simulation curve schematic diagram of the output voltage of the band-gap reference reference of temperature compensation of the present invention.

Embodiment

Below in conjunction with drawings and Examples, the invention will be further described:

As shown in Figure 2 and Figure 3, a kind of band-gap reference reference circuit with temperature compensation, the enabling signal output terminal of described start-up circuit 1 connects respectively the enabling signal input end of described single order band-gap reference circuit 2 and high-order temperature compensation circuit 3; The current signal output end of described single order band-gap reference circuit 2 connects the current signal input end of described high-order temperature compensation circuit 3.Described start-up circuit 1 is normally worked for the band-gap reference circuit that makes temperature compensation, described single order band-gap reference circuit 2 produces the band gap reference voltage of low-temperature coefficient, and described high-order temperature compensation circuit 3 is for carrying out temperature compensation to described single order band-gap reference circuit 2.

Described start-up circuit 1 comprises: a PMOS pipe MSP1 and the 2nd PMOS pipe MSP2, a NMOS pipe MSN1, the 2nd NMOS pipe MSN2, the 3rd NMOS pipe MSN3 and the 4th NMOS pipe MSN4.

Described single order band-gap reference circuit 2 comprises: the 3rd PMOS pipe MP1, the 4th PMOS pipe MP2, the 5th PMOS pipe MP3, the 6th PMOS pipe MP12 and the 7th PMOS pipe MP13, the first positive-negative-positive triode Q1 and the second positive-negative-positive triode Q2, the first error amplifier A1 and the second error amplifier A2, the first resistance R 1, the second resistance R 2, the 3rd resistance R 3, the 4th resistance R 4 and the 5th resistance R 5.

Described high-order temperature compensation circuit 3 comprises: the 8th PMOS pipe MP4, the 9th PMOS pipe MP5, the tenth PMOS pipe MP6, the 11 PMOS pipe MP7, the 12 PMOS pipe MP8, the 13 PMOS pipe MP9, the 14 PMOS pipe MP10 and the 15 PMOS pipe MP11, the 5th NMOS pipe MN1, the 6th NMOS pipe MN2, the 7th NMOS pipe MN3, the 8th NMOS pipe MN4, the 9th NMOS pipe MN5 and the tenth NMOS pipe MN6.

The source electrode of a described PMOS pipe MSP1 is connected with external power source VDD, the source electrode of the drain electrode of a described PMOS pipe MSP1 and described the 2nd PMOS pipe MSP2, the grid of the one PMOS pipe MSP1 is connected, the grid of the drain electrode of described the 2nd PMOS pipe MSP2 and the 2nd PMOS pipe MSP2, the drain electrode of the one NMOS pipe MSN1, the grid of the 2nd NMOS pipe MSN2, the grid of the 3rd NMOS pipe MSN3, the grid of the 4th NMOS pipe MSN4 is connected, source electrode and the outside ground wire GND of a described NMOS pipe MSN1, the source electrode of the 2nd NMOS pipe MSN2, the source electrode of the 3rd NMOS pipe MSN3, the source electrode of the 4th NMOS pipe MSN4 is connected.

The source electrode of described the 3rd PMOS pipe MP1 is connected with the source electrode of external power source VDD, the 4th PMOS pipe MP2, the drain electrode of the output terminal of the grid of the grid of the 3rd PMOS pipe MP1 and the 4th PMOS pipe MP2, the grid of the 7th PMOS pipe MP13, the first error amplifier A1, the 2nd NMOS pipe MSN2 of described start-up circuit 1 is connected, the emitter of the 3rd PMOS pipe drain electrode of MP1 and the reverse input end of the first error amplifier A1, the first positive-negative-positive triode Q1 is connected, and the base stage of the first positive-negative-positive triode Q1 is connected with the collector of the first positive-negative-positive triode Q1, outside ground wire GND.

Described the 4th PMOS pipe drain electrode of MP2 and the positive input of the first error amplifier A1, the reverse input end of the second error amplifier A2, one end of the first resistance R 1 are connected, the other end of described the first resistance R 1 is connected with the emitter of the second positive-negative-positive triode Q2, and the base stage of described the second positive-negative-positive triode Q2 is connected with the collector of outside ground wire GND, the second positive-negative-positive triode Q2.

The source electrode of described the 5th PMOS pipe MP3 is connected with external power source VDD, the drain electrode of the grid of described the 5th PMOS pipe grid of MP3 and the output terminal of the second error amplifier A2, the 6th PMOS pipe MP12, the 3rd NMOS pipe MSN3 of described start-up circuit 1 is connected, one end of described the 5th PMOS pipe drain electrode of MP3 and the positive input of the second error amplifier A2, the second resistance R 2 is connected, and the other end of described the second resistance R 2 is connected with outside ground wire GND.

The source electrode of described the 6th PMOS pipe MP12 is connected with the source electrode of external power source VDD, the 7th PMOS pipe MP13, one end of described the 6th PMOS pipe drain electrode of MP12 and one end of the 3rd resistance R 3, the 4th resistance R 4 is connected, the grid of the one NMOS pipe MSN1 of the drain electrode of the other end of described the 3rd resistance R 3 and the 7th PMOS pipe MP13, single order band-gap reference circuit output terminal VREF, described start-up circuit 1 is connected, the other end of described the 4th resistance R 4 is connected with one end of the 5th resistance R 5, and the other end of described the 5th resistance R 5 is connected with outside ground wire GND.

The source electrode of described the 8th PMOS pipe MP4 is connected with external power source VDD, the grid of described the 8th PMOS pipe MP4 is connected with the grid of the 4th PMOS pipe MP2 of described single order band-gap reference 2, the drain electrode of described the 8th PMOS pipe MP4 is connected with the drain electrode of the 5th NMOS pipe MN1, the grid of the 5th NMOS pipe MN1, the grid of the 6th NMOS pipe MN2, and the source electrode of described the 5th NMOS pipe MN1 is connected with source electrode, the outside ground wire GND of the 6th NMOS pipe MN2.

The source electrode of described the 9th PMOS pipe MP5 is connected with external power source VDD, the grid of described the 9th PMOS pipe MP5 is connected with the grid of the 5th PMOS pipe MP3 of described single order band-gap reference circuit 2, and the drain electrode of described the 9th PMOS pipe MP5 is connected with the grid of the tenth PMOS pipe MP6, the drain electrode of the tenth PMOS pipe MP6, the grid of the 11 PMOS pipe MP7, the drain electrode of the 6th NMOS pipe MN2.

The source electrode of described the 11 PMOS pipe MP7 is connected with the source electrode of external power source VDD, the tenth PMOS pipe MP6, and the drain electrode of described the 11 PMOS pipe MP7 is connected between described the 4th resistance R 4 and the 5th resistance R 5;

The source electrode of described the 12 PMOS pipe MP8 is connected with external power source VDD, the grid of described the 12 PMOS pipe MP8 is connected with the grid of the 4th PMOS pipe MP2 of described single order band-gap reference circuit 2, the drain electrode of described the 12 PMOS pipe MP8 is connected with the drain electrode of the 7th NMOS pipe MN3, the grid of the 7th NMOS pipe MN3, the grid of the 8th NMOS pipe MN4, and the source electrode of described the 7th NMOS pipe MN3 is connected with source electrode, the outside ground wire GND of the 8th NMOS pipe MN4.

Source electrode and the external power source VDD of described the 13 PMOS pipe MP9, the source electrode of the 14 PMOS pipe MP10 is connected, the grid of the grid of described the 13 PMOS pipe MP9 and the 14 PMOS pipe MP10, the drain electrode of the 13 PMOS pipe MP9, the drain electrode of the 9th NMOS pipe MN5, the drain electrode of the 4th NMOS pipe MSN4 of described start-up circuit 1 is connected, the grid of the grid of described the 9th NMOS pipe MN5 and the tenth NMOS pipe MN6, the drain electrode of the tenth NMOS pipe MN6, the drain electrode of the 14 PMOS pipe MP10 is connected, the source electrode of described the 9th NMOS pipe MN5 is connected with the drain electrode of the 8th NMOS pipe MN4, the source electrode of the source electrode of described the 8th NMOS pipe MN4 and the tenth NMOS pipe MN6, outside ground wire GND is connected.

The source electrode of described the 15 PMOS pipe MP11 is connected with external power source VDD, the grid of described the 15 PMOS pipe MP11 is connected with the grid of the 13 PMOS pipe MP9, and the drain electrode of described the 15 PMOS pipe MP11 is connected between described the 4th resistance R 4 and the 5th resistance R 5.

Adopt above technical scheme, start-up circuit is normally worked band-gap reference circuit, produces bandgap voltage reference output.Start-up circuit only plays a role in the time that band-gap reference reference circuit powers on, and after band-gap reference reference circuit has started, start-up circuit quits work, and has avoided start-up circuit on the impact of circuit below.

Error amplifier A1 and A2 in described single order band-gap reference circuit are prior aries, do not repeat them here.

The first error amplifier A1 equates the input node A of the first error amplifier and the voltage of input Node B, i.e. V _a=V _b=V _eB1, wherein, V _eB1it is the emitter base voltage of the first positive-negative-positive triode Q1.

The 3rd PMOS pipe MP1 and the 4th PMOS pipe MP2 are just the same, the drain current I of the 4th PMOS pipe MP2 _pTAT0for:

$I_{\mathrm{<figure-callout\; id="0"\; label="PTAT"\; filenames="HDA0000480923880000051.png"\; state="\{\{state\}\}">PTAT</figure-callout>}0}=\frac{\mathrm{kT}}{q{R}_1}\ln N---\left(1\right)$

Described N is the ratio of the emitter area of the second positive-negative-positive triode Q2 and the first positive-negative-positive triode Q1, and k is Boltzmann constant, and T is absolute temperature, and q is electron charge, and all resistance is all that same material is realized simultaneously.The second error amplifier A2 equates the voltage of the input Node B of the first error amplifier and the input node C of the second error amplifier, i.e. V _b=V _c=V _eB1, the input Node B of described the first error amplifier is the input node of described the second error amplifier simultaneously, the drain current I of the 5th PMOS pipe MP3 _cTAT0for:

$I_{\mathrm{<figure-callout\; id="0"\; label="CTAT"\; filenames="HDA0000480923880000051.png"\; state="\{\{state\}\}">CTAT</figure-callout>}0}=\frac{V_{\mathrm{EB}1}}{R_2}---\left(2\right)$

The breadth length ratio of the 7th PMOS pipe MP13 is the K of the 4th PMOS pipe MP2 ₁times, the drain current I of the 7th PMOS pipe MP13 _pTAT1for:

$I_{\mathrm{PTAT}1}=K_1\&times;{\mathrm{<figure-callout\; id="0"\; label="I\; PTAT"\; filenames="HDA0000480923880000051.png"\; state="\{\{state\}\}">I</figure-callout>}}_{\mathrm{PTAT}}=K_1\&times;\frac{\mathrm{kT}}{q{R}_1}\ln N---\left(3\right)$

The breadth length ratio of the 6th PMOS pipe MP12 is the K of the 5th PMOS pipe MP3 ₂times, the drain current I of the 6th PMOS pipe MP12 _cTAT1for:

$I_{\mathrm{CTAT}1}=K_2\&times;{\mathrm{<figure-callout\; id="0"\; label="I\; CTAT"\; filenames="HDA0000480923880000051.png"\; state="\{\{state\}\}">I</figure-callout>}}_{\mathrm{CTAT}}=K_2\&times;\frac{V_{\mathrm{EB}1}}{R_2}---\left(4\right)$

The present invention is compensation V _eB1temperature high-order nonlinear item, adopt high-order temperature compensation circuit.The 8th PMOS pipe MP4 and the 4th PMOS pipe MP2 are duplicate, and the breadth length ratio of the 6th NMOS pipe MN2 is the K of the 5th NMOS pipe MN1 ₃times, the drain current I of the 6th NMOS pipe MN2 _pTAT2for:

$I_{\mathrm{PTAT}2}=K_3\&times;I_{\mathrm{<figure-callout\; id="0"\; label="PTAT"\; filenames="HDA0000480923880000051.png"\; state="\{\{state\}\}">PTAT</figure-callout>}0}=K_3\&times;\frac{\mathrm{kT}}{q{R}_1}\ln N---\left(5\right)$

The breadth length ratio of the 9th PMOS pipe MP5 is the K of the 5th PMOS pipe MP3 ₄times, the drain current I of the 9th PMOS pipe MP5 _cTAT2for:

$I_{\mathrm{CTAT}2}=K_4\&times;I_{\mathrm{CTAT}0}=K_4\&times;\frac{V_{\mathrm{EB}1}}{R_2}---\left(6\right)$

From formula (5), (6), in temperature T _r1under, by Optimal Parameters K ₃with K ₄, there is following relation:

I _CTAT2＝I _PTAT2 （7）

From Kirchhoff's current law (KCL), the drain current I of the tenth PMOS pipe MP6 _p6for:

I _P6＝I _PTAT2-I _CTAT2 （8）

The 11 PMOS manages MP7 and the tenth PMOS pipe MP6 forms current mirror pair, and the breadth length ratio of the 11 PMOS pipe MP7 is β times of the tenth PMOS pipe MP6.From formula (5), (6), (7), (8), the drain current I of the 11 PMOS pipe MP7 _nLfor:

$I_{\mathrm{NL}}=\left\{\begin{array}{cc}0& \mathrm{whenT}\&le;T_{r1}\\ \mathrm{\&beta;}\&times;K_3\&times;\frac{\mathrm{kT}}{q{R}_1}\ln N-\mathrm{\&beta;}\&times;K_4\&times;\frac{V_{\mathrm{EB}1}}{R_2}& \mathrm{whenT}>T_{r1}\end{array}\right.---\left(9\right)$

The breadth length ratio of the 12 PMOS pipe MP8 is the K of the 4th PMOS pipe MP2 ₅doubly, the drain current I of the 7th NMOS pipe MN3 _pTAT3for:

$I_{\mathrm{PTAT}3}=K_5\&times;I_{\mathrm{PTAT}0}=K_5\&times;\frac{\mathrm{kT}}{q{R}_1}\ln N---\left(10\right)$

In Fig. 2, the 7th NMOS pipe MN3 is operated in saturation region, and the 8th NMOS pipe MN4 is operated in dark linear zone, the drain-source resistance r of the 8th NMOS pipe MN4 _ds4for

$r_{\mathrm{ds}4}=\frac{\sqrt{{(W/L)}_3}}{{(W/L)}_4\sqrt{{2\mathrm{\&mu;}}_n{C}_{\mathrm{ox}}{K}_5{I}_{\mathrm{PTAT}0}}}---\left(11\right)$

(W/L) ₃the wide length of the 7th NMOS pipe MN3, (W/L) ₄the wide length of the 8th NMOS pipe MN4, μ _nelectron mobility, C _oXunit area gate oxide electric capacity.The 13 PMOS pipe MP9 has identical breadth length ratio with the 14 PMOS pipe MP10, and is all operated in saturation region.The 9th NMOS pipe MN5 and the tenth NMOS pipe MN6 are operated in sub-threshold region, and the breadth length ratio of the 9th NMOS pipe MN5 is α times of the tenth NMOS pipe MN6.Wherein, be operated in the drain current I of the metal-oxide-semiconductor of sub-threshold region _dfor:

$I_D\&ap;\frac{W}{\mathrm{<figure-callout\; id="0"\; label="L\; I\; D"\; filenames="HDA0000480923880000051.png"\; state="\{\{state\}\}">L</figure-callout>}}{I}_D{0}_{}\exp \left(\frac{V_{\mathrm{GS}}}{\mathrm{nkT}/q}\right)---\left(12\right)$

Here, W/L is the breadth length ratio of metal-oxide-semiconductor, V _gSthe gate source voltage of metal-oxide-semiconductor, I _d0be the parameter relevant to technique, n is one and is greater than 1 the imperfect factor.

The 15 PMOS pipe MP11 and the 13 PMOS pipe MP9 form current mirror pair, and the breadth length ratio of the 15 PMOS pipe MP11 is the K of the 13 PMOS pipe MP9 ₆doubly, from Fig. 2 and formula (10), (11), (12), the drain current I of the 15 PMOS pipe MP11 _p11for:

$I_{P11}=K_6\&times;n\left(\ln \mathrm{\&alpha;}\right){\left(\frac{W}{L}\right)}_4\frac{\sqrt{{2\mathrm{\&mu;}}_n{C}_{\mathrm{ox}}{K}_5\left(\ln N\right)}}{\sqrt{R_1{(W/L)}_3}}\frac{k^{1.5}}{q^{1.5}}\&times;T^{1.5}---\left(13\right)$

From formula (3), (4), (9), (13), the output voltage V of the band-gap reference reference of temperature compensation _rEFfor:

$V_{\mathrm{REF}}=V_{\mathrm{PTAT}}+V_{\mathrm{CTAT}}+V_{\mathrm{NL}}+V_{\mathrm{PTA}{T}^{1.5}}---\left(14\right)$

Here,

$V_{\mathrm{PTAT}}=K_1\&times;\frac{\mathrm{kT}}{q{R}_1}\left(\ln N\right)\&times;(R_3+R_4+R_5)---\left(15\right)$

$V_{\mathrm{CTAT}}=K_2\&times;\frac{V_{\mathrm{EB}1}}{R_2}\&times;(R_4+R_5)---\left(16\right)$

$V_{\mathrm{NL}}=\left\{\begin{array}{cc}0& \mathrm{whenT}\&le;T_{r1}\\ \mathrm{\&beta;}\&times;K_3\&times;\frac{{\mathrm{kTR}}_5}{q{R}_1}\ln N-\mathrm{\&beta;}\&times;K_4\&times;\frac{R_5{V}_{\mathrm{EB}1}}{R_2}& \mathrm{whenT}>T_{r1}\end{array}\right.---\left(17\right)$

$V_{\mathrm{PTA}{T}^{1.5}}=K_6\&times;n\left(\ln \mathrm{\&alpha;}\right){\left(\frac{W}{L}\right)}_4\frac{\sqrt{{2\mathrm{\&mu;}}_n{C}_{\mathrm{ox}}{K}_5\left(\ln N\right)}}{\sqrt{R_1{(W/L)}_3}}\frac{k^{1.5}}{q^{1.5}}{\&times;T}^{1.5}\&times;R_5---\left(18\right)$

From formula (15), V _pTATthe voltage of a positive temperature coefficient (PTC), the V in formula (16) _eB1the emitter base voltage of the first positive-negative-positive triode Q1, thereby by the parameter K in optimized-type (15) ₁, N and resistance R ₃, R ₄, R ₅, realize single order temperature compensation, obtain single order band-gap reference reference voltage, can obtain band-gap reference reference voltage curve as shown in Figure 4.

In fact, V _eB1there is high-order nonlinear temperature item, from Fig. 4 and formula (15), (16), V _pTATonly offset V _eB1temperature T once, therefore need to carry out high-order temperature compensated.The technology of the present invention is for introducing a segmented current I at single order band-gap reference on reference to basis _nLproduce circuit and one and temperature T ^1.5the electric current I being directly proportional _p11produce circuit, solve single order band-gap reference with reference to the problem existing.From formula (17), voltage V _nLa voltage with segmentation characteristic, simultaneously from formula (18), voltage

one and temperature T ^1.5the voltage being directly proportional, thereby by V _nLwith

two voltages are incorporated in the reference of single order band gap base, can effectively compensate V _eB1in the higher order term of temperature T, obtain high-order temperature compensation bandgap reference, can obtain the band-gap reference reference voltage curve of temperature compensation of the present invention as shown in Figure 5.Fig. 6 is the output reference voltage V of the band-gap reference reference of temperature compensation of the present invention _rEFtemperature characterisitic simulation curve, wherein horizontal ordinate is temperature, ordinate is band-gap reference output voltage.Simulation result shows, is-55 DEG C～125 DEG C in temperature range, and the band-gap reference of this temperature compensation is with reference to the temperature coefficient that has reached 2.54ppm/ DEG C.

Here, when start-up circuit starts, due to band-gap reference reference output voltage V _rEFrelatively low, the one NMOS pipe MNS1 cut-off, make the 2nd NMOS pipe MSN2, the grid potential of the 3rd NMOS pipe MSN3 and the 4th NMOS pipe MSN4 is noble potential, thereby make the 3rd PMOS pipe MP1, the 4th PMOS pipe MP2, the grid of the 5th PMOS pipe MP3 and the 14 PMOS pipe MP10 is electronegative potential, this has just formed the 3rd PMOS pipe MP1 to the first positive-negative-positive triode Q1, the 4th PMOS pipe MP2 is to the second positive-negative-positive triode Q2, the 5th PMOS pipe MP3 is to the current path of the second resistance R the 2 and the 14 PMOS pipe MP10 to the ten NMOS pipe MN6, make circuit depart from zero condition, enter duty.But, V _rEFrise to NMOS threshold voltage when above, the one NMOS pipe MSN1 conducting, make the grid of the 2nd NMOS pipe MSN2, the 3rd NMOS pipe MSN3 and the 4th NMOS pipe MSN4 be electronegative potential and be operated in cut-off region, start-up circuit is no longer exerted an influence to band-gap reference reference circuit below, and startup completes.

The present invention has adopted a segmented current I _nLproduce circuit and and temperature T ^1.5the electric current I being directly proportional _p11the compensation technique that produces circuit, makes band-gap reference reference output voltage have very high stability, meets the requirement of low voltage operating due to circuit simultaneously, makes the present invention have range of application very widely.

More than describe preferred embodiment of the present invention in detail.Should be appreciated that those of ordinary skill in the art just can design according to the present invention make many modifications and variations without creative work.Therefore, all technician in the art, all should be in by the determined protection domain of claims under this invention's idea on the basis of existing technology by the available technical scheme of logical analysis, reasoning, or a limited experiment.

Claims (2)

1. the band-gap reference reference circuit with temperature compensation, comprises start-up circuit (1) and single order band-gap reference circuit (2), it is characterized in that: also comprise high-order temperature compensation circuit (3); The enabling signal output terminal of described start-up circuit (1) connects respectively the enabling signal input end of described single order band-gap reference circuit (2) and high-order temperature compensation circuit (3); The current signal output end of described single order band-gap reference circuit (2) connects the current signal input end of described high-order temperature compensation circuit (3).

2. a kind of band-gap reference reference circuit with temperature compensation as claimed in claim 1, it is characterized in that: described start-up circuit (1) comprising: a PMOS pipe (MSP1) and the 2nd PMOS pipe (MSP2), a NMOS pipe (MSN1), the 2nd NMOS pipe (MSN2), the 3rd NMOS pipe (MSN3) and the 4th NMOS pipe (MSN4);

Described single order band-gap reference circuit (2) comprising: the 3rd PMOS pipe (MP1), the 4th PMOS pipe (MP2), the 5th PMOS pipe (MP3), the 6th PMOS pipe (MP12) and the 7th PMOS pipe (MP13), the first positive-negative-positive triode (Q1) and the second positive-negative-positive triode (Q2), the first error amplifier (A1) and the second error amplifier (A2), the first resistance (R1), the second resistance (R2), the 3rd resistance (R3), the 4th resistance (R4) and the 5th resistance (R5);

Described high-order temperature compensation circuit (3) comprising: the 8th PMOS pipe (MP4), the 9th PMOS pipe (MP5), the tenth PMOS pipe (MP6), the 11 PMOS pipe (MP7), the 12 PMOS pipe (MP8), the 13 PMOS pipe (MP9), the 14 PMOS pipe (MP10) and the 15 PMOS pipe (MP11), the 5th NMOS pipe (MN1), the 6th NMOS pipe (MN2), the 7th NMOS pipe (MN3), the 8th NMOS pipe (MN4), the 9th NMOS pipe (MN5) and the tenth NMOS pipe (MN6);

The source electrode of a described PMOS pipe (MSP1) is connected with external power source (VDD), the source electrode of the drain electrode of a described PMOS pipe (MSP1) and described the 2nd PMOS pipe (MSP2), the grid of the one PMOS pipe (MSP1) is connected, the grid of the drain electrode of described the 2nd PMOS pipe (MSP2) and the 2nd PMOS pipe (MSP2), the drain electrode of the one NMOS pipe (MSN1), the grid of the 2nd NMOS pipe (MSN2), the grid of the 3rd NMOS pipe (MSN3), the grid of the 4th NMOS pipe (MSN4) is connected, source electrode and the outside ground wire (GND) of a described NMOS pipe (MSN1), the source electrode of the 2nd NMOS pipe (MSN2), the source electrode of the 3rd NMOS pipe (MSN3), the source electrode of the 4th NMOS pipe (MSN4) is connected,

Source electrode and the external power source (VDD) of described the 3rd PMOS pipe (MP1), the source electrode of the 4th PMOS pipe (MP2) is connected, the grid of the grid of the 3rd PMOS pipe (MP1) and the 4th PMOS pipe (MP2), the grid of the 7th PMOS pipe (MP13), the output terminal of the first error amplifier (A1), the drain electrode of the 2nd NMOS pipe (MSN2) of described start-up circuit (1) is connected, the 3rd PMOS pipe drain electrode of (MP1) and the reverse input end of the first error amplifier (A1), the emitter of the first positive-negative-positive triode (Q1) is connected, the collector of the base stage of the first positive-negative-positive triode (Q1) and the first positive-negative-positive triode (Q1), outside ground wire (GND) is connected,

Described the 4th PMOS pipe drain electrode of (MP2) and the positive input of the first error amplifier (A1), the reverse input end of the second error amplifier (A2), one end of the first resistance (R1) are connected, the other end of described the first resistance (R1) is connected with the emitter of the second positive-negative-positive triode (Q2), and the base stage of described the second positive-negative-positive triode (Q2) is connected with the collector of outside ground wire GND, the second positive-negative-positive triode (Q2);

The source electrode of described the 5th PMOS pipe (MP3) is connected with external power source (VDD), the drain electrode of the grid of described the 5th PMOS pipe grid of (MP3) and the output terminal of the second error amplifier (A2), the 6th PMOS pipe (MP12), the 3rd NMOS pipe (MSN3) of described start-up circuit (1) is connected, one end of described the 5th PMOS pipe drain electrode of (MP3) and the positive input of the second error amplifier (A2), the second resistance (R2) is connected, and the other end of described the second resistance (R2) is connected with outside ground wire GND;

Source electrode and the external power source (VDD) of described the 6th PMOS pipe (MP12), the source electrode of the 7th PMOS pipe (MP13) is connected, described the 6th PMOS pipe drain electrode of (MP12) and one end of the 3rd resistance (R3), one end of the 4th resistance (R4) is connected, the drain electrode of the other end of described the 3rd resistance (R3) and the 7th PMOS pipe (MP13), single order band-gap reference circuit output terminal VREF, the grid of the one NMOS pipe (MSN1) of described start-up circuit (1) is connected, the other end of described the 4th resistance (R4) is connected with one end of the 5th resistance (R5), the other end of described the 5th resistance (R5) is connected with outside ground wire GND,

The source electrode of described the 8th PMOS pipe (MP4) is connected with external power source (VDD), the grid of described the 8th PMOS pipe (MP4) is connected with the grid of the 4th PMOS pipe (MP2) of described single order band-gap reference, the drain electrode of the 8th PMOS pipe (MP4) and the 5th NMOS manages the drain electrode of (MN1), the grid of the 5th NMOS pipe (MN1), the grid that the 6th NMOS manages (MN2) and are connected, and the source electrode that described the 5th NMOS manages (MN1) is managed the source electrode of (MN2) with the 6th NMOS, outside ground wire (GND) is connected;

The source electrode of described the 9th PMOS pipe (MP5) is connected with external power source (VDD), the grid of described the 9th PMOS pipe (MP5) is connected with the grid of the 5th PMOS pipe (MP3) of described single order band-gap reference circuit (2), and the drain electrode of described the 9th PMOS pipe (MP5) and the tenth PMOS manage the grid of (MP6), the drain electrode that the tenth PMOS manages (MP6), the grid that the 11 PMOS manages (MP7), the drain electrode that the 6th NMOS manages (MN2) and be connected;

The source electrode of described the 11 PMOS pipe (MP7) is connected with the source electrode of external power source (VDD), the tenth PMOS pipe (MP6), and the drain electrode of described the 11 PMOS pipe (MP7) is connected between described the 4th resistance (R4) and the 5th resistance (R5);

The source electrode of described the 12 PMOS pipe (MP8) is connected with external power source (VDD), the grid of described the 12 PMOS pipe (MP8) is connected with the grid of the 4th PMOS pipe (MP2) of described single order band-gap reference circuit (2), the drain electrode of described the 12 PMOS pipe (MP8) and the 7th NMOS manages the drain electrode of (MN3), the grid of the 7th NMOS pipe (MN3), the grid that the 8th NMOS manages (MN4) and are connected, and the source electrode that described the 7th NMOS manages (MN3) is managed the source electrode of (MN4) with the 8th NMOS, outside ground wire (GND) is connected;

Source electrode and the external power source (VDD) of described the 13 PMOS pipe (MP9), the source electrode of the 14 PMOS pipe (MP10) is connected, the grid of the grid of described the 13 PMOS pipe (MP9) and the 14 PMOS pipe (MP10), the drain electrode of the 13 PMOS pipe (MP9), the drain electrode of the 9th NMOS pipe (MN5), the drain electrode of the 4th NMOS pipe (MSN4) of described start-up circuit (1) is connected, the grid of the grid of described the 9th NMOS pipe (MN5) and the tenth NMOS pipe (MN6), the drain electrode of the tenth NMOS pipe (MN6), the drain electrode of the 14 PMOS pipe (MP10) is connected, the source electrode of described the 9th NMOS pipe (MN5) is connected with the drain electrode that the 8th NMOS manages (MN4), the source electrode of the source electrode of described the 8th NMOS pipe (MN4) and the tenth NMOS pipe (MN6), outside ground wire GND is connected,

The source electrode of described the 15 PMOS pipe (MP11) is connected with external power source (VDD), the grid of described the 15 PMOS pipe (MP11) is connected with the grid that the 13 PMOS manages (MP9), and the drain electrode of described the 15 PMOS pipe (MP11) is connected between described the 4th resistance (R4) and the 5th resistance (R5).

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