CN103472878A - Reference current source - Google Patents

Abstract

The invention relates to the integrated circuit technology, in particular to a reference current source. The reference current source is characterized by comprising a reference current generating circuit and a starting biasing circuit which are connected. The reference current generating circuit comprises a first p-channel metal oxide semiconductor (PMOS) pipe, a second PMOS pipe, a third PMOS pipe, a first triode, a second triode, a third triode, a fourth triode, a sixth triode, a first resistor and a second resistor. The starting biasing circuit comprises a fifth triode, a third resistor and a fourth resistor. The reference current source has the advantages of being simple in structure, low in starting voltage and easy to integrate, has high precision and low starting voltage and reduces production cost.

Description

A kind of reference current source

Technical field

The present invention relates to integrated circuit technique, relate to specifically a kind of reference current source.

Background technology

In integrated circuit fields, current reference is the very important circuit of a class.Along with the continuous expansion of integrated circuit scale, to the also raising thereupon of performance requirement of chip, the current precision that this provides current reference source requires more and more higher.The way of traditional current reference is to produce an accurate bandgap voltage reference Vref, then obtains needed current value with bandgap voltage reference Vref divided by resistance.The principle of the generation of bandgap voltage reference Vref is: have the Vbe of negative temperature coefficient and have the single order item of the Δ Vbe of positive temperature coefficient according to certain ratio elimination temperature coefficient.Yet this way needs an amplifier to guarantee that two node voltages equate, thereby has increased circuit complexity, and has strengthened the area of chip and increased cost, and the trigger voltage of this reference source is high simultaneously.

Summary of the invention

Technical matters to be solved by this invention, be exactly for the problems referred to above, proposes a kind of reference current source.

The present invention solves the problems of the technologies described above adopted technical scheme: a kind of reference current source, it is characterized in that, comprise the reference current generating circuit be connected and start biasing circuit, described reference current generating circuit comprises a PMOS pipe M1, the 2nd PMOS pipe M2, the 3rd PMOS pipe M3, the first triode Q1, the second triode Q2, the 3rd triode Q3, the 4th triode Q4, the 6th triode Q6, the first resistance R 1, the second resistance R 2, and described startup biasing circuit comprises the 5th triode Q5 and the 3rd resistance R 3, the 4th resistance R 4;

The emitter of source electrode, the first triode Q1 and the second triode Q2 of the one PMOS pipe M1, the 2nd PMOS pipe M2 and the 3rd PMOS pipe M3 and the emitter of the 5th triode Q5 all meet power vd D;

The grid of the one PMOS pipe M1, the 2nd PMOS pipe M2 and the 3rd PMOS pipe M3 is connected with the drain electrode of a PMOS pipe M1, the collector of the 6th triode Q6;

The drain electrode of the 2nd PMOS pipe M2 is connected with the emitter of the 3rd triode Q3 with an end of the first resistance R 1, the emitter of the 6th triode Q6;

The output terminal Iref that the drain electrode of the 3rd PMOS pipe M3 is reference current source;

The collector of the first triode Q1 is connected with the base stage of base stage, the 4th triode Q4 with the collector of the 3rd triode Q3;

The base stage of the first triode Q1 is connected with an end of the 3rd resistance R 3 with the base stage of the second triode Q2, the collector of the 5th triode Q5;

The collector of the second triode Q2 is connected with the base stage of the 6th triode Q6, the collector of the 4th triode Q4;

The emitter of the 4th triode Q4 is connected with an end of the second resistance R 2;

The base stage of the 5th triode Q5 connects the other end of the 3rd resistance R 3 and an end of the 4th resistance R 4;

The equal ground connection of the other end of the other end of the other end of the first resistance R 1, the second resistance R 2 and the 4th resistance R 4.

Concrete, the ratio of the emitter area of described the 3rd triode Q3 and the 4th triode Q4 is 8:1.

Beneficial effect of the present invention is, have advantages of simple in structure, trigger voltage is low and it is integrated to be easy to, also there is higher precision and lower trigger voltage simultaneously, and reduced production cost.

The accompanying drawing explanation

Fig. 1 is reference current source circuit structural representation of the present invention;

Fig. 2 is reference current source principle of work schematic diagram of the present invention.

Embodiment

Below in conjunction with accompanying drawing, describe technical scheme of the present invention in detail:

Reference current source of the present invention, it is characterized in that, comprise the reference current generating circuit be connected and start biasing circuit, described reference current generating circuit comprises a PMOS pipe M1, the 2nd PMOS pipe M2, the 3rd PMOS pipe M3, the first triode Q1, the second triode Q2, the 3rd triode Q3, the 4th triode Q4, the 6th triode Q6, the first resistance R 1, the second resistance R 2, and described startup biasing circuit comprises the 5th triode Q5 and the 3rd resistance R 3, the 4th resistance R 4;

The emitter of source electrode, the first triode Q1 and the second triode Q2 of the one PMOS pipe M1, the 2nd PMOS pipe M2 and the 3rd PMOS pipe M3 and the emitter of the 5th triode Q5 all meet power vd D;

The grid of the one PMOS pipe M1, the 2nd PMOS pipe M2 and the 3rd PMOS pipe M3 is connected with the drain electrode of a PMOS pipe M1, the collector of the 6th triode Q6;

The drain electrode of the 2nd PMOS pipe M2 is connected with the emitter of the 3rd triode Q3 with an end of the first resistance R 1, the emitter of the 6th triode Q6;

The output terminal Iref that the drain electrode of the 3rd PMOS pipe M3 is reference current source;

The collector of the first triode Q1 is connected with the base stage of base stage, the 4th triode Q4 with the collector of the 3rd triode Q3;

The base stage of the first triode Q1 is connected with an end of the 3rd resistance R 3 with the base stage of the second triode Q2, the collector of the 5th triode Q5;

The collector of the second triode Q2 is connected with the base stage of the 6th triode Q6, the collector of the 4th triode Q4;

The emitter of the 4th triode Q4 is connected with an end of the second resistance R 2;

The base stage of the 5th triode Q5 connects the other end of the 3rd resistance R 3 and an end of the 4th resistance R 4;

The equal ground connection of the other end of the other end of the other end of the first resistance R 1, the second resistance R 2 and the 4th resistance R 4.

For convenient narration, the first to the 3rd PMOS pipe replaces with M1, M2, M3 respectively successively, and the first to the 6th triode replaces with Q1, Q2, Q3, Q4, Q5, Q6 respectively successively, and first to fourth resistance replaces with R1, R2, R3, R4 respectively successively, as shown in Figure 1

Reference current source of the present invention comprises startup biasing circuit and reference current generating circuit, supply voltage VDD, earth terminal GND, reference current output terminal Iref; Wherein,

The source electrode of reference current generating circuit: M1, M2, M3 is connected with supply voltage VDD, and the grid of M1, M2, M3 tri-pipes links together and M1 is the diode connected mode, the output I that the drain electrode of M3 is reference current _refthe emitter of the drain electrode of M2, R1, Q6, the emitter of Q3 connect, the drain electrode of M1 is connected with the collector of Q6, the emitter of Q1, Q2 is connected with supply voltage VDD, the base stage of Q1, Q2 connects and is connected with the collector of Q5 in starting bias voltage circuit, the collector of Q1 is connected with the Q3 collector of diode connected mode, the base stage of Q3, Q4 links together, the collector of the collector of Q4, the base stage of Q6, Q2 connects, the emitter of Q4 is connected with resistance R 2, and the other end of R1, R2 is connected with ground.

The emitter that starts biasing circuit: Q5 is connected with supply voltage VDD, and the Q1 in the collector of Q5, R3, reference current generating circuit, the base stage of Q2 connect, and the base stage of Q5 is connected with R3, R4, and the other end of R4 is connected with ground.

Principle of work of the present invention is:

As shown in Figure 2, start biasing circuit work Q5 conducting when VDD has a very low voltage, produce a voltage at B point and cause Q1, Q2, Q3, Q4 conducting, thereby whole reference current generating circuit works.R3, R4 is the effect for Limited Current.After the circuit normal operation, the base voltage of Q1, Q2 equates, therefore I _c1=I _c2.By the circuit electrical specification, can be obtained: I _c2=I _c4+ I _b6, I _c1=I _c3+ I _b, according to I _c1=I _c2can obtain I _c4+ I _b6=I _c3+ I _b, I _bbe the base current of two times, due to I _c=β I _band β is very large, therefore I _c3≈ I _c4, the effect of Q6 is exactly to have reduced I _c3with I _c4error.

Q3 is the 8:1 relation with the ratio of the emitter area of Q4, has:

${\mathrm{<figure-callout\; id="1"\; label="I"\; filenames="HDA0000379141880000011.png,HDA0000379141880000012.png"\; state="\{\{state\}\}">I</figure-callout>}}_1=\frac{V_a-V_{\mathrm{be}3}}{\mathrm{<figure-callout\; id="1"\; label="R"\; filenames="HDA0000379141880000011.png,HDA0000379141880000012.png"\; state="\{\{state\}\}">R</figure-callout>}1};$

$I_2=\frac{V_a-V_{\mathrm{be}4}}{R2};$

Equate with R2 as R1 and for temperature coefficient be

during positive temperature coefficient:

$I_1-I_2=\frac{V_{\mathrm{be}4}-V_{\mathrm{be}3}}{R1}=\frac{{\mathrm{\&Delta;V}}_{\mathrm{be}}}{R1};$

Due to I _c3≈ I _c4therefore:

$I_1-I_2=I_3+I_4=\frac{{\mathrm{\&Delta;V}}_{\mathrm{be}}}{\mathrm{<figure-callout\; id="1"\; label="R"\; filenames="HDA0000379141880000011.png,HDA0000379141880000012.png"\; state="\{\{state\}\}">R</figure-callout>}1};$

The twice of the W/L that the W/L that supposes M3 is M2, M3, M2, M3 are the M1 of mirror image:

$I_{\mathrm{ref}}=\frac{{\mathrm{\&Delta;V}}_{\mathrm{be}}}{\mathrm{<figure-callout\; id="1"\; label="R"\; filenames="HDA0000379141880000011.png,HDA0000379141880000012.png"\; state="\{\{state\}\}">R</figure-callout>}1},$

And by:

$I_c=I_s\exp \left(\frac{q{V}_{\mathrm{be}}}{\mathrm{kT}}\right),$

Can obtain:

$V_{\mathrm{be}}=\frac{\mathrm{kT}}{q}\ln \left(\frac{I_C}{I_S}\right);$

I wherein _sfor the BJT reverse saturation current, have:

$\mathrm{\&Delta;}{V}_{\mathrm{be}}{=V}_{\mathrm{be}4}-V_{\mathrm{be}3}=\frac{\mathrm{kT}}{q}\ln \left(\frac{I_{C4}}{I_S}\right)-\frac{\mathrm{kT}}{q}\ln \left(\frac{8I_{C4}}{I_S}\right)$

$=-\frac{\mathrm{<figure-callout\; id="8"\; label="kT\; q\; ln"\; filenames="HDA0000379141880000011.png,HDA0000379141880000012.png"\; state="\{\{state\}\}">kT</figure-callout>}}{q}\ln 8.$

In sum

adopt R1, R2 to there is suitable positive temperature coefficient technique, make reference current source I _refhaving good precision, is a kind of simple in structure, very practical reference current source circuit that trigger voltage is low.

Claims (2)

1. a reference current source, it is characterized in that, comprise the reference current generating circuit be connected and start biasing circuit, described reference current generating circuit comprises a PMOS pipe M1, the 2nd PMOS pipe M2, the 3rd PMOS pipe M3, the first triode Q1, the second triode Q2, the 3rd triode Q3, the 4th triode Q4, the 6th triode Q6, the first resistance R 1, the second resistance R 2, and described startup biasing circuit comprises the 5th triode Q5 and the 3rd resistance R 3, the 4th resistance R 4;

The emitter of source electrode, the first triode Q1 and the second triode Q2 of the one PMOS pipe M1, the 2nd PMOS pipe M2 and the 3rd PMOS pipe M3 and the emitter of the 5th triode Q5 all meet power vd D;

The grid of the one PMOS pipe M1, the 2nd PMOS pipe M2 and the 3rd PMOS pipe M3 is connected with the drain electrode of a PMOS pipe M1, the collector of the 6th triode Q6;

The drain electrode of the 2nd PMOS pipe M2 is connected with the emitter of the 3rd triode Q3 with an end of the first resistance R 1, the emitter of the 6th triode Q6;

The output terminal Iref that the drain electrode of the 3rd PMOS pipe M3 is reference current source;

The collector of the first triode Q1 is connected with the base stage of base stage, the 4th triode Q4 with the collector of the 3rd triode Q3;

The base stage of the first triode Q1 is connected with an end of the 3rd resistance R 3 with the base stage of the second triode Q2, the collector of the 5th triode Q5;

The collector of the second triode Q2 is connected with the base stage of the 6th triode Q6, the collector of the 4th triode Q4;

The emitter of the 4th triode Q4 is connected with an end of the second resistance R 2;

The base stage of the 5th triode Q5 connects the other end of the 3rd resistance R 3 and an end of the 4th resistance R 4;

The equal ground connection of the other end of the other end of the other end of the first resistance R 1, the second resistance R 2 and the 4th resistance R 4.

2. a kind of reference current source according to claim 1, is characterized in that, the ratio of the emitter area of described the 3rd triode Q3 and the 4th triode Q4 is 8:1.

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