WO2022161356A1 - Power-on control circuit and related device thereof - Google Patents

Abstract

Disclosed is a power-on control circuit and a related device thereof. The circuit comprises: a power-on control unit (10) and an anti-leakage circuit (20); a first port (11) of the power-on control unit (10) being connected to a power-on control pin of a chip, a second port (12) of the power-on control unit (10) being grounded, a third port (13) of the power-on control unit (10) being connected to a first port (21) of the anti-leakage circuit (20), a second port (22) of the anti-leakage circuit (20) being connected to a power source, and a third port (23) of the anti-leakage circuit (20) being grounded, wherein the power-on control unit (10) is used for controlling the level of the power-on control pin after receiving a power-on signal sent by the anti-leakage circuit (20), thereby realizing the function of automatic power-on of the chip, and the anti-leakage circuit (20) is used for discharging in the first time period after receiving a turn-on signal sent by the power-on control unit (10), thereby realizing the function of anti-leakage of the chip. The design of the circuit is greatly simplified, and the usage efficiency of the circuit is improved.

Description

A power-on control circuit and related device

This application claims the priority of the Chinese patent application with the application number of 2021101282908 and the application title of "A startup control circuit and related devices", which was filed with the China Patent Office on January 29, 2021, the entire contents of which are incorporated herein by reference Applying.

technical field

The present application relates to the technical field of electronic circuits, and in particular, to a power-on control circuit and related devices.

Background technique

With the development of digital control technology in the field of electronic circuits, more and more occasions require automatic startup or shutdown control of equipment, especially for communication equipment or circuits with high energy consumption, such as a large number of 5G base stations arranged in 5G mobile communications , so that the energy consumption of 5G network increases exponentially. Therefore, it has become a common method to reduce energy consumption to automatically start or shut down the equipment.

At present, the general boot control method is to ground the boot control pin of the chip to achieve the purpose of automatically booting after power-on, or connect the boot control pin of the chip to the general transmission interface of the micro control unit (MCU), The automatic power-on or power-off of the chip is controlled by the MCU.

However, the above-mentioned method of grounding the power-on control pins of the chip will cause the problem of leakage after the chip is automatically turned on. The above-mentioned method of controlling the automatic power-on or shutdown of the chip through the MCU will result in complicated circuit structure design. Therefore, how to efficiently and conveniently realize the automatic power-on of the chip without leakage has become an important research topic for researchers in the technical field.

SUMMARY OF THE INVENTION

The embodiments of the present application provide a power-on control circuit and a related device. The potential of a power-on control pin is controlled by a control device, and a resistor-capacitance (RC) circuit is used for charging and discharging, so that the chip can be automatically powered on. , shutdown, and anti-leakage functions, and greatly simplify the circuit design and improve the efficiency of the circuit.

In a first aspect of the embodiments of the present application, a power-on control circuit is provided, including a power-on control unit and an anti-leakage circuit, wherein:

The first port of the power-on control unit is connected to the power-on control pin of the chip, the second port of the power-on control unit is grounded, the third port of the power-on control unit is connected to the first port of the anti-leakage circuit, and the The second port of the anti-leakage circuit is connected to the power supply, and the third port of the anti-leakage circuit is grounded;

The power-on control unit is used to control the level of the power-on control pin after receiving the power-on signal sent by the anti-leakage circuit, so as to realize the function of automatic power-on of the chip, and the anti-leakage circuit is used to receive the power-on signal. After the turn-on signal sent by the power-on control unit, the device is discharged within the first time period, so as to realize the function of preventing electric leakage of the chip.

In the embodiment of the present application, the pin in the chip that controls the power on is the power-on control pin, and the automatic power-on of the chip needs to satisfy the condition that the power-on control pin first maintains a low level, so that the chip starts normally, and then the power-on control pin remains high all the time In the case of high level, the internal circuit of the power-on control pin has no path to the ground, and no leakage will occur. Therefore, after the anti-leakage circuit in the embodiment of the present application is powered on, it sends a power-on signal to the power-on control unit. After the power-on control unit receives the power-on signal, the power-on control unit is turned on, and the level of the power-on control pin is pulled down. Realize the automatic power-on function of the chip. After the chip is automatically powered on, the anti-leakage circuit receives the conduction signal sent by the power-on control unit, and discharges it in the first period of time, the power-on control unit is cut off, and the level of the power-on control pin is pulled up. , to achieve the function of anti-leakage of the chip, so the potential of the boot control pin is controlled by the control device, and the anti-leakage circuit is used for charging and discharging, which can realize the function of automatic power-on, shutdown, and anti-leakage of the chip, and greatly simplifies the circuit design. , saving the cost of circuit hardware and improving the efficiency of circuit use.

In a possible implementation, the power-on control unit is configured to control the level of the power-on control pin after receiving the power-on signal sent by the anti-leakage circuit, including:

After the power-on control unit receives the power-on signal sent by the anti-leakage circuit, the power-on control unit is turned on, and the level of the power-on control pin is pulled down to realize the function of automatic power-on of the chip.

In the embodiment of the present application, because the automatic power-on of the chip needs to meet the condition that the power-on control pin is kept at a low level first, the embodiment of the present application turns on the power-on control unit to pull down the level of the power-on control pin, thereby realizing The function of automatic power-on when the chip is powered on.

In a possible implementation manner, the anti-leakage circuit is configured to discharge within a first period of time after receiving the turn-on signal sent by the power-on control unit, including:

After the anti-leakage circuit receives the conduction signal sent by the power-on control unit, the anti-leakage circuit discharges in the first time period, the power-on control unit is cut off, and the level of the power-on control pin is pulled. high, to realize the anti-leakage function of the chip.

In the embodiment of the present application, after the chip is powered on and automatically powered on, if the power-on control pin of the chip remains at a low level, a leakage phenomenon will occur. Therefore, the anti-leakage circuit in the embodiment of the present application is turned on after the power-on control unit is turned on. Discharge in the first period of time, so that the power-on control unit is cut off, so that the level of the power-on control pin is pulled up, and the function of preventing leakage of the chip is realized.

In a possible implementation manner, the power-on control unit includes:

boot control device;

The first port of the boot control device is connected to the boot control pin, the second port of the boot control device is grounded, and the third port of the boot control device is connected to the first port of the anti-leakage circuit;

After the power-on control device receives the power-on signal sent by the anti-leakage circuit, the power-on control device is turned on, and the level of the power-on control pin is pulled down to realize the function of automatic power-on of the chip.

In the embodiment of the present application, the power-on control unit includes a power-on control device. When the power-on control device is turned on, the power-on control pin is grounded and the level is pulled down. When the power-on control device is cut off, the power-on control pin is pulled up. The power-on control device realizes the automatic power-on and power-off functions of the chip by controlling the potential of the power-on control pins of the chip, and realizes the function of preventing leakage when the chip is powered on.

In a possible implementation, the anti-leakage circuit includes:

a first capacitor and a first resistor;

The first port of the first capacitor is connected to the power supply, the second port of the first capacitor is connected to the first port of the first resistor and the third port of the power-on control device, and the first port of the first resistor is connected to the power supply. The port is connected to the third port of the boot control device, and the second port of the first resistor is grounded;

The first capacitor is charged after being powered on, the level of the third port of the power-on control device is pulled up, the power-on control device is turned on, and the level of the power-on control pin is pulled down, so that the chip automatically The power-on function, after the power-on control device is turned on, the first capacitor is discharged within the first time period, the third port of the power-on control device is discharged through the first resistor, and the power-on control The level of the third port of the device is pulled down, the power-on control device is turned off, and the level of the power-on control pin is pulled up to realize the function of preventing electric leakage of the chip.

In the embodiment of the present application, the anti-leakage circuit includes a first capacitor and a first resistor. After the chip is powered on, the first capacitor is charged, the level of the third port of the power-on control device is pulled up, the power-on control device is turned on, and the power-on control device is turned on. The level of the pin is pulled low, the chip is automatically powered on after power-on, the first capacitor is discharged within the first time period after the boot control device is turned on, the level of the third port of the boot control device is pulled low, and the boot control device is turned off. If the power-on control pin is turned off, the level of the power-on control pin is pulled high. In the case of a high level, the power-on control pin of the chip has no path to the ground, and no leakage occurs, and the anti-leakage function is realized.

In a possible implementation manner, the anti-leakage circuit further includes:

reverse diode;

The first port of the reverse diode is connected to the second port of the first resistor and the ground wire, and the second port of the reverse diode is connected to the second port of the first capacitor and the second port of the first resistor. a port, and a third port of the boot control device;

When the chip is powered on and then powered off, the reverse diode is turned on, the level of the third port of the power-on control device is pulled down, and the power-on control device is turned off, so that the next power-on In case the chip is automatically turned on and anti-leakage functions.

In the embodiment of the present application, in order to prevent the problem that the third port of the power-on control device discharges slowly and fails to power on when the chip is quickly powered on, off and then powered on again, the anti-leakage circuit further includes a reverse diode. When the chip is powered on quickly When the power is turned off again, the voltage across the first capacitor cannot change abruptly. The anti-leakage circuit can speed up the discharge speed by connecting a reverse diode in parallel. Prepare for electricity, so as to achieve the purpose of fast switching on and off without leakage.

In a possible implementation manner, the power-on control device is turned on, including:

When the voltage difference between the first port of the power-on control device and the third port of the power-on control device is greater than the first threshold, the power-on control device is turned on;

The power-on control device is turned off, including:

When the voltage difference between the first port of the power-on control device and the third port of the power-on control device is less than the second threshold, the power-on control device is turned off.

In the embodiment of the present application, during the power-on process of the chip, the level of the third port of the power-on control device is pulled high, and the voltage difference between the third port of the power-on control device and the first port of the power-on control device is greater than the first threshold. In this case, the power-on control device is turned on, and the level of the power-on control pin is pulled low to realize the function of automatic power-on after the chip is powered on. When the voltage difference between the three ports and the first port of the power-on control device is less than the second threshold, the power-on control device is turned off, and the level of the power-on control pin is pulled up, thereby realizing the function of preventing leakage of the chip.

In a possible implementation manner, the power-on control device is an N-type metal-oxide-semiconductor MOS transistor or a triode.

In the embodiment of the present application, an N-type MOS transistor or a triode can be used to realize the conversion of the power-on control pin from a low level to a high level, wherein the N-type MOS transistor is a voltage control device, the triode is a current control device, and the N Type MOS transistors are more energy efficient than triodes and have better thermal stability.

In a second aspect of the embodiments of the present application, a power-on control device is provided, including a power supply, a chip, and the power-on control circuit described in any one of the first aspect of the embodiments of the present application.

In a possible implementation manner, the power supply includes a first auxiliary power supply and a second auxiliary power supply, the first auxiliary power supply is used for powering the power-on control circuit, and the second auxiliary power supply is used for supplying the power to the power-on control circuit. Chip power supply.

In a possible implementation manner, the power-on control circuit includes a power-on control unit and an anti-leakage circuit, wherein:

The first port of the power-on control unit is connected to the power-on control pin of the chip, the second port of the power-on control unit is grounded, the third port of the power-on control unit is connected to the first port of the anti-leakage circuit, and the The second port of the anti-leakage circuit is connected to the power supply, and the third port of the anti-leakage circuit is grounded;

The power-on control unit is used to control the level of the power-on control pin after receiving the power-on signal sent by the anti-leakage circuit, so as to realize the function of automatic power-on of the chip, and the anti-leakage circuit is used to receive the power-on signal. After the turn-on signal sent by the power-on control unit, the device is discharged within the first time period, so as to realize the function of preventing electric leakage of the chip.

In the embodiment of the present application, the pin in the chip that controls the power on is the power-on control pin, and the automatic power-on of the chip needs to satisfy the condition that the power-on control pin first maintains a low level, so that the chip starts normally, and then the power-on control pin remains high all the time In the case of high level, the internal circuit of the power-on control pin has no path to the ground, and no leakage will occur. Therefore, after the anti-leakage circuit in the embodiment of the present application is powered on, it sends a power-on signal to the power-on control unit. After the power-on control unit receives the power-on signal, the power-on control unit is turned on, and the level of the power-on control pin is pulled down. Realize the automatic power-on function of the chip. After the chip is automatically powered on, the anti-leakage circuit receives the conduction signal sent by the power-on control unit, and discharges it in the first period of time, the power-on control unit is cut off, and the level of the power-on control pin is pulled up. , to achieve the function of anti-leakage of the chip, so the potential of the boot control pin is controlled by the control device, and the anti-leakage circuit is used for charging and discharging, which can realize the function of automatic power-on, shutdown, and anti-leakage of the chip, and greatly simplifies the circuit design. , saving the cost of circuit hardware and improving the efficiency of circuit use.

By implementing the embodiment of the present application, the potential of the power-on control pin can be controlled by the control device, and the RC circuit can be used for charging and discharging, which can realize the functions of automatic power-on, power-off, and anti-leakage of the chip, and greatly simplifies the circuit design and improves the performance. circuit efficiency.

Description of drawings

In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following will briefly introduce the accompanying drawings used in the description of the embodiments or the prior art. Obviously, the drawings in the following description are only These are some embodiments of the present application. For those of ordinary skill in the art, other drawings can also be obtained based on these drawings without any creative effort.

1 is a schematic structural diagram of an on-board circuit of a power-on control pin disclosed in an embodiment of the application;

FIG. 2 is a schematic diagram of a control signal of a power-on control pin disclosed in an embodiment of the application;

3 is a schematic structural diagram of a power-on control circuit disclosed in an embodiment of the application;

FIG. 4 is a schematic structural diagram of another power-on control circuit disclosed in an embodiment of the present application;

FIG. 5 is a schematic signal diagram of a power-on control circuit disclosed in an embodiment of the present application;

FIG. 6 is a signal schematic diagram of another power-on control circuit disclosed in an embodiment of the present application;

7 is a schematic diagram of a control signal of a power-on control circuit disclosed in an embodiment of the application;

FIG. 8 is a schematic structural diagram of a power-on control device disclosed in an embodiment of the present application.

Detailed ways

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are some, but not all, embodiments of the present application.

Embodiments of the present application provide a power-on control circuit and a related device, which will be described in detail below.

The terms "first", "second", etc. involved in the embodiments of the present application are used to distinguish different objects, rather than to describe a specific order. In addition, the terms "include" and "have" and any of their modifications are intended to be Override non-exclusive includes.

Please refer to FIG. 1 . FIG. 1 is a schematic structural diagram of an on-board circuit of a power-on control pin disclosed in an embodiment of the present application. As shown in FIG. 1 , the power-on control pin described in the embodiment of the present application is the pin PBINT in the figure, and the power-on control pin PBINT inside the chip is pulled up to the battery voltage (voltage battery, VBAT) through a 20kΩ resistor. , Among them, the 20kΩ pull-up resistor cannot be turned off. When the chip is turned on, it needs to be powered on by pulling the power-on control pin PBINT down for a period of time. , for the convenience of description, the embodiment of the present application takes the time length of continuously pulling down for 1 s as an example for description.

Based on the on-board circuit of the power-on control pin in the above Figure 1, it can be known that the level of the internal power-on control pin needs to be continuously pulled down for a period of time to boot normally. At present, the following methods are usually used to start up:

First, ground the power-on control pin PBINT, so that the chip can be powered on directly after power-on;

Second, the power is turned on through the physical button, specifically, the power-on control pin PBINT is grounded through the physical button, and the button is released after each button is turned on;

Third, the startup is controlled by the microcontroller MCU, specifically, the startup control pin PBINT is connected to the general input/output port of the MCU.

However, the above booting methods have some shortcomings. If the first boot method above is used for the chip, then after booting, when the device is powered normally, the boot control pin PBINT first maintains a low level for a length of time greater than 1s, so that the chip starts normally, and then keeps a high level. In the case of high level, since the power-on control pin PBINT is always grounded, leakage will occur through the path to ground. When the battery voltage VBAT takes a typical value of 4.0V, a leakage of VBAT/20KΩ=200uA will occur, which will cause the system There will be an additional power consumption of about 200uA in deep sleep and power saving model (PSM), far exceeding the standard specification of chip power consumption. If the above-mentioned second booting method is used for the chip, the key is turned on and then released, which can achieve the purpose of preventing leakage, but this booting method cannot achieve the purpose of automatic booting. If the above-mentioned third booting method is used for the chip, an additional MCU is required to control the level of the booting control pin. This booting method relies on an external MCU, which is expensive and complicated in circuit design.

After analysis, in order to achieve the purpose of automatically starting up after power-on without leakage, after the chip is powered on, the power-on control pin PBINT must be disconnected from the ground wire, and no current path will be formed. Therefore, it is necessary to control the power-on control by adding a power-on control device. The level of the pin PBINT, and use the RC circuit to charge and discharge to achieve the function of preventing leakage.

Please refer to FIG. 2 , which is a schematic diagram of a control signal of a power-on control pin disclosed in an embodiment of the present application. As shown in FIG. 2 , when the chip is powered on, the power-on control pin PBINT needs to meet the logic requirements of the control signal in FIG. 2 . That is, when the device is powered normally, the power-on control pin must be kept at a low level for a period of time (such as 1s), so that the chip starts normally, and then it remains at a high-level state. Among them, the power-on control pin PBINT turns from low level to The high level can be realized by adding a power-on control device. When turning to a high level, an additional anti-leakage circuit is required to discharge to realize the anti-leakage function.

Please refer to FIG. 3 , which is a schematic structural diagram of a power-on control circuit disclosed in an embodiment of the present application. As shown in FIG. 3 , the power-on control circuit described in the embodiment of the present application includes a power-on control unit 10 and an anti-leakage circuit 20, wherein:

The first port 11 of the power-on control unit 10 is connected to the power-on control pin PBINT of the chip, the second port 12 of the power-on control unit 10 is grounded to GND, and the third port 13 of the power-on control unit 10 is connected to the first port 21 of the anti-leakage circuit 20 , The second port 22 of the anti-leakage circuit 20 is connected to the power supply, and the third port 23 of the anti-leakage circuit 20 is grounded to GND;

The power-on control unit 10 is used to control the level of the power-on control pin PBINT after receiving the power-on signal sent by the anti-leakage circuit 20 to realize the function of automatic power-on of the chip. After the signal is received, it is discharged within the first time period to realize the function of preventing leakage of the chip.

In the embodiment of the present application, the pin that controls the power-on of the chip is the power-on control pin PBINT, and the automatic power-on of the chip needs to satisfy the condition that the power-on control pin PBINT first maintains a low level, so that the chip starts normally, and then the power-on control pin PBINT It keeps high level all the time. In the case of high level, the internal circuit of the power-on control pin PBINT has no path to the ground, and no leakage occurs. Therefore, after the anti-leakage circuit 20 in the embodiment of the present application is powered on, it sends a power-on signal to the power-on control unit 10. After the power-on control unit 10 receives the power-on signal, the power-on control unit 10 is turned on, and the power-on control pin PBINT is turned on. The level is pulled low to realize the automatic power-on function of the chip. After the chip is automatically turned on, the anti-leakage circuit 20 receives the turn-on signal sent by the power-on control unit 10, and discharges it in the first time period, the power-on control unit 10 is cut off, and the power is turned on. The level of the control pin PBINT is pulled up to realize the function of preventing leakage of the chip. Therefore, the potential of the power-on control pin PBINT is controlled by the control device, and the leakage prevention circuit 20 is used to charge and discharge, so that the chip can be automatically turned on, off, and It has the function of preventing leakage, and greatly simplifies the circuit design, saves the cost of circuit hardware, and improves the efficiency of circuit use.

Please refer to FIG. 4 , which is a schematic structural diagram of another power-on control circuit disclosed in an embodiment of the present application. As shown in FIG. 4 , the power-on control circuit described in the embodiment of the present application includes a power-on control unit 10 and an anti-leakage circuit 20, wherein:

The power-on control unit 10 includes a power-on control device 101;

The first port 111 of the boot control device 101 is connected to the boot control pin PBINT, the second port 112 of the boot control device 101 is grounded to GND, and the third port 113 of the boot control device 101 is connected to the first port of the anti-leakage circuit 20;

After the power-on control device 101 receives the power-on signal sent by the anti-leakage circuit 20 , the power-on control device 101 is turned on, and the level of the power-on control pin PBINT is pulled low to realize the function of automatic power-on of the chip.

In this embodiment, when the power-on control device 101 is turned on, the power-on control pin PBINT is grounded, and the level is pulled low. Control the potential of the power-on control pin PBINT of the chip to realize the automatic power-on and power-off functions of the chip, and realize the function of preventing leakage when the chip is powered on.

The anti-leakage circuit 20 includes a first capacitor C1 and a first resistor R1;

The first port 211 of the first capacitor C1 is connected to the power supply VBAT, the second port 212 of the first capacitor C1 is connected to the first port 213 of the first resistor R1 and the third port 113 of the power-on control device 101, and the first port 212 of the first resistor R1 The port 213 is connected to the third port 113 of the boot control device 101, and the second port 214 of the first resistor R1 is grounded to GND;

The first capacitor C1 is charged after being powered on, the level of the third port 113 of the power-on control device 101 is pulled high, the power-on control device 101 is turned on, and the level of the power-on control pin PBINT is pulled down to realize the function of automatic power-on of the chip. After the power-on control device 101 is turned on, the first capacitor C1 is discharged within a first time period (more than 1 s), the third port 113 of the power-on control device 101 is discharged through the first resistor R1, and the third port 113 of the power-on control device 101 is discharged. When the level is pulled low, the power-on control device 101 is turned off, and the level of the power-on control pin PBINT is pulled up to realize the function of preventing leakage of the chip.

In this embodiment, after the chip is powered on, the first capacitor C1 is charged, the level of the third port 113 of the power-on control device 101 is pulled high, the power-on control device 101 is turned on, and the level of the power-on control pin PBINT is pulled down, After the chip is powered on, it is automatically powered on, the first capacitor C1 is discharged within the first time period after the power-on control device 101 is turned on, the level of the third port 113 of the power-on control device 101 is pulled down, the power-on control device 101 is turned off, and the power-on control device 101 is turned on. The level of the control pin PBINT is pulled high. In the case of a high level, the power-on control pin PBINT of the chip has no path to the ground, and no leakage occurs, and the anti-leakage function is realized.

The anti-leakage circuit 20 further includes a reverse diode D1;

The first port 215 of the reverse diode D1 is connected to the second port 214 of the first resistor R1 and the ground line GND, and the second port 216 of the reverse diode D1 is connected to the second port 212 of the first capacitor C1 and the second port 212 of the first resistor R1. a port 213, and the third port 113 of the boot control device 101;

In the case of power-off after the chip is powered on, the reverse diode D1 is turned on, the level of the third port 113 of the power-on control device 101 is pulled down, and the power-on control device 101 is turned off, so that the chip can automatically be powered on the next time. Power-on and anti-leakage functions.

In this embodiment, in order to prevent the problem that the third port 113 of the power-on control device 101 discharges slowly and fails to power on when the chip is quickly powered on, off and then powered on again, the anti-leakage circuit 20 further includes a reverse diode D1. When the power is quickly turned on and off, the voltage across the first capacitor C1 cannot change abruptly. The anti-leakage circuit 20 can speed up the discharge speed by connecting a reverse diode D1 in parallel, and the level of the third port 113 of the power-on control device 101 is pulled down The speed is accelerated to prepare for the next power-on of the chip, so as to achieve the purpose of fast switching on and off without leakage.

It should be noted that, in this embodiment of the present application, the power-on control device 101 may be an N-type metal-oxide-semiconductor MOS transistor or a triode, and an N-type MOS transistor or a triode may be used to realize the power-on control pin PBINT from low level to high Level conversion, among them, the N-type MOS tube is a voltage control device, and the triode is a current control device. The N-type MOS tube is more energy-efficient than the triode and has better thermal stability. Here, the N-type MOS transistor is used as the boot control device 101 as an example for illustration. The gate of the N-type MOS transistor is used to control the on-off of the drain and the source, the drain is connected to the boot control pin PBINT, and the source is grounded. , the logic potential that the gate needs to provide is opposite to the boot control pin PBINT, specifically, the gate is high, the N-type MOS transistor is turned on, the boot control pin PBINT is grounded to low, the gate is low, N The type MOS tube is turned off, and the boot control pin PBINT is pulled high to a high level. Connect one end of the first capacitor C1 to VBAT, and the other end of the first capacitor C1 to the gate of the N-type MOS transistor. When VBAT is powered on, the first capacitor C1 is charged, and the gate potential of the N-type MOS transistor is pulled high. The MOS tube is turned on, the power-on control pin PBINT is pulled low, and the chip is powered on normally. After the chip is turned on, the power-on control pin PBINT must be pulled high. Therefore, the gate of the N-type MOS tube needs to be turned low. At this time, It can be realized by discharging through the first resistor R1 connected in parallel, and the gate timing wave diagram of the N-type MOS transistor is determined by the value of the first resistor R1.

In addition, the power-on control device 101 is turned on means that the power-on control device 101 is turned on when the voltage difference between the first port 111 of the power-on control device 101 and the third port 113 of the power-on control device 101 is greater than the first threshold; Similarly, turning off the power-on control device 101 means that when the voltage difference between the first port 111 of the power-on control device 101 and the third port 113 of the power-on control device 101 is less than the second threshold, the power-on control device 101 is turned off .

During the power-on process of the chip, the level of the third port 113 of the power-on control device 101 is pulled high, and the voltage difference between the third port 113 of the power-on control device 101 and the first port 111 of the power-on control device 101 is greater than the first threshold In this case, the power-on control device 101 is turned on, and the level of the power-on control pin PBINT is pulled low to realize the function of automatic power-on after the chip is powered on. When the voltage difference between the third port 113 of the control device 101 and the first port 111 of the power-on control device 101 is smaller than the second threshold, the power-on control device 101 is turned off, and the level of the power-on control pin PBINT is pulled high to realize chip protection. leakage function.

Please refer to FIG. 5 , which is a schematic diagram of a signal of a power-on control circuit disclosed in an embodiment of the present application. As shown in Figure 5, the three curves represent the waveforms of each point of the power-on control circuit that manually controls VBAT at 25°C. Specifically, the curve a represents the waveform of the battery voltage VBAT changing with time, and the curve b represents the power-on control lead. The waveform of the voltage at the pin PBINT changes with time, and the curve c represents the waveform of the voltage at the third port of the power-on control device (the gate of the N-type MOS transistor) with time. It can be seen from Figure 5 that during the first stage, the chip is not powered on, and curves a, b, and c remain unchanged; during the second stage, the battery voltage VBAT is powered on, and the voltage value represented by curve a It soars to a high point and remains stable. At this time, the first capacitor C1 is charged, and the voltage value at the third port of the power-on control device (the gate of the N-type MOS transistor) represented by the curve c soars to a high point, and the N-type MOS transistor is turned on. , then the gate voltage of the N-type MOS tube is discharged through the first resistor R1, and at the same time, the voltage of the power-on control pin PBINT represented by the curve b remains low for a period of time (greater than 1s); in the third During the period, when the gate voltage of the N-type MOS tube continues to discharge and drops to a critical value, the N-type MOS tube is disconnected, the power-on control pin PBINT is pulled high through the internal circuit, and the curve b soars to a high point and remains stable.

On the other hand, the embodiments of the present application also provide a PSM leakage test, specifically, before and after adding the power-on control circuit, enter the PSM to perform a power consumption test between -40°C and 85°C, and the measured current value of the whole machine is shown in the following table. :

temperature(℃)	-40	-25	0	25	45	65	70	75	85
Without control circuit PSM current (uA)	2	2	2	3	3	4	4	5	6
Add control circuit PSM current (uA)	2	2	2	3	3	4	4	5	6

It can be seen from the above table that the leakage of the added control circuit is very small, and there is no significant difference in the current of the whole machine in the PSM mode before and after the control circuit is added from the voltage source. Therefore, the power-on control circuit added in the embodiment of the present application has no effect on the PSM mode. influences.

Please refer to FIG. 6 , which is a schematic signal diagram of another power-on control circuit disclosed in an embodiment of the present application. As shown in Figure 6, the three curves respectively represent the waveforms of each point of the power-on control circuit under the fast switching test. Specifically, the curve a represents the waveform of the battery voltage VBAT changing with time, and the curve b represents the power-on control pin PBINT. The waveform diagram of the voltage changing with time, the curve c represents the waveform diagram of the voltage changing with time at the third port of the power-on control device (the gate of the N-type MOS transistor). It can be seen from Figure 6 that during the first stage, after the chip is powered on, the VBAT voltage value represented by curve a remains high and stable, and the voltage of the power-on control pin PBINT represented by curve b is maintained for a period of time (greater than 1s) Low level, then soars to a high point and remains stable, the voltage value at the third port of the power-on control device (the gate of the N-type MOS transistor) represented by curve c soars to a high point, and then continues to discharge and drops to a critical value; in the second During the stage, the chip is suddenly powered off, the VBAT voltage value represented by curve a drops to a low point and remains unchanged, the power-on control pin PBINT represented by curve b drops to a low level, and the curve c represents the first power-on control device. The voltage value at the three ports (the gate of the N-type MOS transistor) instantly drops to -VBAT; in the third stage, the chip is powered on again, and the curves a, b, and c return to the changes in the first stage. It can be seen from the curves and waveforms of the above three stages that after a short power-off in the second stage, the gate of the N-type MOS tube can be quickly read and discharged through the reverse diode, returning to the state before power-on, and then in the third stage. It can be powered on again within the period of time, and the power-on control circuit can achieve the purpose of preventing leakage during the whole process of the quick switch-on test.

Please refer to FIG. 7 , which is a schematic diagram of a control signal of a power-on control circuit disclosed in an embodiment of the present application. As shown in FIG. 7 , the control signal described in this embodiment is a square wave signal with alternating high level and low level, the control signal may include a transmission control command, and may also include a data segment or a data block, In the control signal, "0" corresponds to a low level, and "1" corresponds to a high level. The above control signal takes the control command as an example. The control signal is low level "0" in the first time period, high level "1" in the second time period, and low level in the third time period. "0", a low level "0" in the fourth time period, and a high level "1" in the fifth time period, the sum of the durations of these five time periods can be regarded as a cycle, and in the next cycle The levels corresponding to these five time periods will appear repeatedly, which can be used to transmit the same control command periodically. It should be noted that the high level and the low level in the control signal do not correspond to voltages of two specific values, but correspond to two voltage ranges. The control signal described in this embodiment may be a power-on control signal in the power-on control circuit.

Please refer to FIG. 8 , which is a schematic structural diagram of a power-on control device disclosed in an embodiment of the present application. As shown in FIG. 8 , the power-on control device described in this embodiment includes a power supply, a chip, and a power-on control circuit as shown in any one of FIG. 3 or FIG. 4 , wherein:

The power supply includes a first auxiliary power supply 301 and a second auxiliary power supply. The output port of the first auxiliary power supply 301 is connected to the first port 211 of the first capacitor C1. The first auxiliary power supply 301 is used to power the power-on control circuit, and the second auxiliary power supply is used for to power the chip.

The power-on control circuit includes a power-on control unit 10 and an anti-leakage circuit 20, wherein:

The first port of the boot control unit 10 is connected to the boot control pin PBINT of the chip, the second port of the boot control unit 10 is grounded to GND, and the third port of the boot control unit 10 is connected to the first port of the anti-leakage circuit 20 , and the anti-leakage circuit 20 The second port is connected to the power supply VBAT, and the third port of the anti-leakage circuit 20 is grounded to GND;

The power-on control unit 10 is used to control the level of the power-on control pin PBINT after receiving the power-on signal sent by the anti-leakage circuit 20 to realize the function of automatic power-on of the chip. After the signal is received, it is discharged within the first time period to realize the function of preventing leakage of the chip.

In the embodiment of the present application, the pin in the chip that controls the power-on is the power-on control pin PBINT, and the automatic power-on of the chip needs to meet the condition that the power-on control pin PBINT is kept at a low level first, so that the chip starts normally, and then the power-on control pin PBINT It keeps high level all the time. In the case of high level, the internal circuit of the power-on control pin PBINT has no path to the ground, and no leakage occurs. Therefore, after the anti-leakage circuit 20 in the embodiment of the present application is powered on, it sends a power-on signal to the power-on control unit 10. After the power-on control unit 10 receives the power-on signal, the power-on control unit 10 is turned on, and the power-on control pin PBINT is turned on. The level is pulled low to realize the automatic power-on function of the chip. After the chip is automatically turned on, the anti-leakage circuit 20 receives the turn-on signal sent by the power-on control unit 10, and discharges it in the first period of time, the power-on control unit 10 is cut off, and the power is turned on. The level of the control pin PBINT is pulled high to realize the function of preventing leakage of the chip. Therefore, the potential of the power-on control pin PBINT is controlled by the control device, and the leakage prevention circuit 20 is used to charge and discharge, so that the chip can be automatically turned on, off, and It has the function of preventing leakage, and greatly simplifies the circuit design, saves the cost of circuit hardware, and improves the efficiency of circuit use.

Through the above application embodiment, the potential of the power-on control pin can be controlled by the control device, and the RC circuit can be used for charging and discharging, which can realize the functions of automatic power-on, power-off, and anti-leakage of the chip, and greatly simplifies the circuit design and improves the performance. The use efficiency of the circuit saves the cost of circuit hardware.

A power-on control circuit and related devices provided by the embodiments of the present application have been introduced in detail above. The principles and implementations of the present application are described in this paper by using specific examples. The descriptions of the above embodiments are only used to help understanding. The method of the present application and its core idea; at the same time, for those skilled in the art, according to the idea of the present application, there will be changes in the specific implementation and application scope. In summary, the content of this specification should not be It is construed as a limitation of this application.

Claims (20)

1. A power-on control circuit, characterized in that it includes:

   Start-up control unit and anti-leakage circuit;

   The first port of the power-on control unit is connected to the power-on control pin of the chip, the second port of the power-on control unit is grounded, the third port of the power-on control unit is connected to the first port of the anti-leakage circuit, and the The second port of the anti-leakage circuit is connected to the power supply, and the third port of the anti-leakage circuit is grounded;

   The power-on control unit is used to control the level of the power-on control pin after receiving the power-on signal sent by the anti-leakage circuit, so as to realize the function of automatic power-on of the chip, and the anti-leakage circuit is used to receive the power-on signal. After the turn-on signal sent by the power-on control unit, the device is discharged within the first time period, so as to realize the function of preventing electric leakage of the chip.
2. The power-on control circuit according to claim 1, wherein the power-on control unit is configured to control the level of the power-on control pin after receiving the power-on signal sent by the anti-leakage circuit, comprising:

   After the power-on control unit receives the power-on signal sent by the anti-leakage circuit, the power-on control unit is turned on, and the level of the power-on control pin is pulled down to realize the function of automatic power-on of the chip.
3. The power-on control circuit according to claim 1, wherein the anti-leakage circuit is configured to discharge within a first period of time after receiving the turn-on signal sent by the power-on control unit, comprising:

   After the anti-leakage circuit receives the conduction signal sent by the power-on control unit, the anti-leakage circuit discharges in the first time period, the power-on control unit is cut off, and the level of the power-on control pin is pulled. high, to realize the anti-leakage function of the chip.
4. The power-on control circuit according to any one of claims 1-3, wherein the power-on control unit comprises:

   boot control device;

   The first port of the boot control device is connected to the boot control pin, the second port of the boot control device is grounded, and the third port of the boot control device is connected to the first port of the anti-leakage circuit;

   After the power-on control device receives the power-on signal sent by the anti-leakage circuit, the power-on control device is turned on, and the level of the power-on control pin is pulled down to realize the function of automatic power-on of the chip.
5. power-on control circuit according to claim 4, is characterized in that, described anti-leakage circuit comprises:

   a first capacitor and a first resistor;

   The first port of the first capacitor is connected to the power supply, the second port of the first capacitor is connected to the first port of the first resistor and the third port of the power-on control device, and the first port of the first resistor is connected to the power supply. The port is connected to the third port of the boot control device, and the second port of the first resistor is grounded;

   The first capacitor is charged after being powered on, the level of the third port of the power-on control device is pulled up, the power-on control device is turned on, and the level of the power-on control pin is pulled down, so that the chip automatically The power-on function, after the power-on control device is turned on, the first capacitor is discharged within the first time period, the third port of the power-on control device is discharged through the first resistor, and the power-on control The level of the third port of the device is pulled down, the power-on control device is turned off, and the level of the power-on control pin is pulled up to realize the function of preventing electric leakage of the chip.
6. The power-on control circuit according to claim 5, wherein the anti-leakage circuit further comprises:

   reverse diode;

   The first port of the reverse diode is connected to the second port of the first resistor and the ground wire, and the second port of the reverse diode is connected to the second port of the first capacitor and the second port of the first resistor. a port, and a third port of the boot control device;

   When the chip is powered on and then powered off, the reverse diode is turned on, the level of the third port of the power-on control device is pulled down, and the power-on control device is turned off, so that the next power-on In case the chip is automatically turned on and anti-leakage functions.
7. The power-on control circuit according to claim 6, wherein the power-on control device is turned on, comprising:

   When the voltage difference between the first port of the power-on control device and the third port of the power-on control device is greater than the first threshold, the power-on control device is turned on;

   The power-on control device is turned off, including:

   When the voltage difference between the first port of the power-on control device and the third port of the power-on control device is less than the second threshold, the power-on control device is turned off.
8. The power-on control circuit according to claim 4, wherein the power-on control device is an N-type metal-oxide-semiconductor MOS transistor or a triode.
9. The power-on control circuit according to claim 8, wherein the N-type MOS transistor realizes the switching of the power-on control pin between a low level and a high level by controlling a voltage, and the transistor is controlled by current to realize the switching between the low level and the high level of the power-on control pin.
10. The power-on control circuit according to claim 8 or 9, wherein when the power-on control device is the N-type MOS transistor, the gate of the N-type MOS transistor controls the connection between the drain and the source of the N-type MOS transistor. On and off, the drain of the N-type MOS transistor is connected to the power-on control pin, and the source of the N-type MOS transistor is grounded;

    When the gate of the N-type MOS transistor is at a high level, the N-type MOS transistor is turned on, and the power-on control pin is at a low level. When the gate of the N-type MOS transistor is at a low level, the The N-type MOS transistor is turned off, and the power-on control pin is at a high level.
11. The power-on control circuit according to any one of claims 1 to 10, wherein the power level of the power-on control pin is controlled to be a square wave signal that alternates between a high level and a low level.
12. A power-on control device is characterized by comprising a power supply, a chip, and the power-on control circuit of any one of claims 1-11.
13. The power-on control device according to claim 12, wherein the power supply comprises a first auxiliary power supply and a second auxiliary power supply, the first auxiliary power supply is used for powering the power-on control circuit, and the second auxiliary power supply is used for powering the power-on control circuit. A power supply is used to power the chip.
14. The power-on control device according to claim 12 or 13, wherein the power-on control circuit comprises:

    Start-up control unit and anti-leakage circuit;

    The first port of the power-on control unit is connected to the power-on control pin of the chip, the second port of the power-on control unit is grounded, the third port of the power-on control unit is connected to the first port of the anti-leakage circuit, and the The second port of the anti-leakage circuit is connected to the power supply, and the third port of the anti-leakage circuit is grounded;

    The power-on control unit is used to control the level of the power-on control pin after receiving the power-on signal sent by the anti-leakage circuit, so as to realize the function of automatic power-on of the chip, and the anti-leakage circuit is used to receive the power-on signal. After the turn-on signal sent by the power-on control unit, the device is discharged within the first time period, so as to realize the function of preventing electric leakage of the chip.
15. The power-on control device according to claim 14, wherein the power-on control unit comprises:

    boot control device;

    The first port of the boot control device is connected to the boot control pin, the second port of the boot control device is grounded, and the third port of the boot control device is connected to the first port of the anti-leakage circuit;

    After the power-on control device receives the power-on signal sent by the anti-leakage circuit, the power-on control device is turned on, and the level of the power-on control pin is pulled down to realize the function of automatic power-on of the chip.
16. The power-on control device according to claim 14 or 15, wherein the anti-leakage circuit comprises:

    a first capacitor and a first resistor;

    The first port of the first capacitor is connected to the power supply, the second port of the first capacitor is connected to the first port of the first resistor and the third port of the power-on control device, and the first port of the first resistor is connected to the power supply. The port is connected to the third port of the boot control device, and the second port of the first resistor is grounded;

    The first capacitor is charged after being powered on, the level of the third port of the power-on control device is pulled up, the power-on control device is turned on, and the level of the power-on control pin is pulled down, so that the chip automatically The power-on function, after the power-on control device is turned on, the first capacitor is discharged within the first time period, the third port of the power-on control device is discharged through the first resistor, and the power-on control The level of the third port of the device is pulled down, the power-on control device is turned off, and the level of the power-on control pin is pulled up to realize the function of preventing electric leakage of the chip.
17. The power-on control device according to claim 16, wherein the anti-leakage circuit further comprises:

    reverse diode;

    The first port of the reverse diode is connected to the second port of the first resistor and the ground wire, and the second port of the reverse diode is connected to the second port of the first capacitor and the second port of the first resistor. a port, and a third port of the boot control device;

    When the chip is powered on and then powered off, the reverse diode is turned on, the level of the third port of the power-on control device is pulled down, and the power-on control device is turned off, so that the next power-on In case the chip is automatically turned on and anti-leakage functions.
18. A processor is characterized by comprising an input circuit, an output circuit and the power-on control circuit according to any one of claims 1-11.
19. A chip, characterized by comprising the power-on control circuit of any one of claims 1-11 or the processor of claim 18 .
20. A power-on control system, characterized by comprising the power-on control circuit according to any one of claims 1-11, or the power-on control device according to any one of claims 12-17, or the power-on control device according to claim 18 The processor, or the chip of claim 19.

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